ee121 john wakerly lecture #15
DESCRIPTION
EE121 John Wakerly Lecture #15. CPLDs FPGAs. CPLDs vs. FPGAs. CPLD architecture Small number of largish PLDs (e.g., “36V18”) on a single chip Programmable interconnect between PLDs. FPGA architecture Much larger number of smaller programmable logic blocks. - PowerPoint PPT PresentationTRANSCRIPT
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EE121 John Wakerly Lecture #15
CPLDs
FPGAs
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CPLDs vs. FPGAs• CPLD
architecture
• Small number of largish PLDs (e.g., “36V18”) on a single chip
• Programmable interconnect between PLDs
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• FPGAarchitecture
• Much larger number of smaller programmable logic blocks.
• Embedded in a sea of lots and lots of programmable interconnect.
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How to expand PLD architecture?• Increase # of inputs and outputs in a
conventional PLD?– E.g., 16V8 --> 20V8 --> 22V10.– Why not --> 32V16 --> 128V64 ?
• Problems: – n times the number of inputs and outputs requires n2 as much chip area -- too costly
– logic gets slower as number of inputs to AND array increases
• Solution: multiple PLDs with a relatively small programmable interconnect.– Less general than a single large PLD, but can use
software “fitter” to partition into smaller PLD blocks.
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CPLD families
• Identical individual PLD blocks (Xilinx “FBs”) replicated in different family members.– Different number of PLD blocks
– Different number of I/O pins
• Many CPLDs have fewer I/O pins than macrocells– “Buried” Macrocells -- provide needed logic terms
internally but these outputs are not connected externally.
– IC package size dictates # of I/O pins but not the total # of macrocells.
– Typical CPLD families have devices with differing resources in the same IC package.
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Xilinx CPLDs
• Notice overlap in resource availability in a particular package.
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Xilinx 9500-family CPLD architecture
72 ==>XC9572
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9500-family function blocks (FBs)
• 18 macrocells per FB• 36 inputs per FB (partitioning challenge, but
also reason for relatively compact size of FBs)• Macrocell outputs can go to I/O cells or back
into switch matrix to be routed to this or other FBs.
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9500-series macrocell (18 per FB)
Up to 5 product terms
Programmableinversion or XORproduct term
Global clock or product-term clock
Set control
Reset control
OE control
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9500-series product-term allocator
Share terms from above and below
programmablesteeringelements
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9500-series I/O block
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• Could be anything from a limited set of multiplexers to a full crossbar.
• Multiplexer -- small, fast, but difficult fitting• Crossbar -- easy fitting but large and slow
Switch matrix for XC95108
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FPGAs
• Historically, FPGA architectures and companies began around the same time as CPLDs
• FPGAs are closer to “programmable ASICs” -- large emphasis on interconnection routing– Timing is difficult to predict -- multiple hops vs. the
fixed delay of a CPLD’s switch matrix.– But more “scalable” to large sizes.
• FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD.
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General FPGA chip architecture
a.k.a. CLB --“configurable logicblock”
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Xilinx 4000-series FPGAs
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FPGA specsmanship
• Two flip-flops per CLB, plus two per I/O cell.• 25 “gates” per CLB if used for logic.• 32 bits of RAM per CLB if not used for logic.• All of this is valid only if your design has a
“perfect fit”.
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Configurable Logic Block (CLB)
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CLB function generators (F, G, H)
• Use RAM to store a truth table– F, G: 4 inputs, 16 bits of RAM each– H: 3 inputs, 8 bits of RAM– RAM is loaded from an external PROM at system
initialization.
• Broad capability using F, G, and H:– Any 2 funcs of 4 vars, plus a func of 3 vars– Any func of 5 vars– Any func of 4 vars, plus some funcs of 6 vars– Some funcs of 9 vars, including parity and 4-bit
cascadable equality checking
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CLB input and output connections -- buried in the sea of interconnect
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Detail
connectionscontrolled byRAM bits
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Programmable Switch Matrix
programmable switch element
turning the corner, etc.
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The fitter’s job
• Partition logic functions into CLBs• Arrange the CLBs• Interconnect the CLBs• Minimize the number of CLBs used• Minimize the size and delay of interconnect
used• Work with constraints
– “Locked” I/O pins– Critical-path delays– Setup and hold times of storage elements
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Oh, by the way -- I/O blocks
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Problems common to CPLDs and FPGAs
• Pin locking– Small changes, and certainly large ones, can cause
the fitter to pick a different allocation of I/O blocks and pinout.
– Locking too early may make the resulting circuit slower or not fit at all.
• Running out of resources– Design may “blow up” if it doesn’t all fit on a single
device.– On-chip interconnect resources are much richer
than off-chip; e.g., barrel-shifter example.– Larger devices are exponentially more expensive.
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Midterm Solutions Discussion
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Next Time
• Synchronous design methodology• Metastability