ee141 digital integrated circuit design manufacturing 1 manufacturing process digital integrated...

EE141Digital Integrated Circuit Design Manufacturing1

ManufacturingManufacturingProcessProcess

Digital Integrated Digital Integrated Circuit DesignCircuit DesignAndrea BonfantiDEIBVia Golgi 40, Milano


CMOS ProcessCMOS Process

n-well CMOS Processn-well CMOS Process


Twin-well CMOS ProcessTwin-well CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

Twin-well Trench-Isolated CMOS ProcessTwin-well Trench-Isolated CMOS Process


Triple-well CMOS ProcessTriple-well CMOS Process


Circuit Under DesignCircuit Under Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2


Its Layout ViewIts Layout View

metal1

poly

contact

nwell

p+ diffusion

p+ diffusion

n+ diffusion

n+ diffusion


Its Layout View (2)Its Layout View (2)


oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic ProcessPhoto-Lithographic Process


Patterning of SiOPatterning of SiO22

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch


CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers


CMOS Process Walk-ThroughCMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)


CMOS Process Walk-ThroughCMOS Process Walk-ThroughSiO2

(d) After trench filling, CMP planarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p



(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+ source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2



(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of via’s,

deposition and patterning ofsecond layer of Al.

AlSiO2


MetallizationMetallization


Advanced MetallizationAdvanced Metallization


Design RulesDesign Rules


3D Perspective3D Perspective

Polysilicon Aluminum


Design RulesDesign Rules

Interface between designer and process engineer

Guidelines for constructing process masks Unit dimension: minimum line width

scalable design rules: lambda parameter absolute dimensions (micron rules)


Single-well CMOS Process LayersSingle-well CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion (ntap, ptap)

Via

Well (n)

Active (diffuision n+ or p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (n+) Green


Layers in 0.25 Layers in 0.25 m CMOS processm CMOS process


Intra-Layer Design RulesIntra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole


Transistor Layout (PMOS)Transistor Layout (PMOS)

1

2

5

3

Tra

nsis

tor


Vias and ContactsVias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


Select LayerSelect Layer

1

3 3

2

2

2

WellSubstrate

Select3

5


CMOS Inverter LayoutCMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’


Layout EditorLayout Editor


Design Rule CheckerDesign Rule Checker


The final resultThe final result


PackagingPackaging


Packaging RequirementsPackaging Requirements

Electrical: low parasitics Mechanical: reliable and robust Thermal: efficient heat removal Economical: cheap


Bonding TechniquesBonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding


Tape-Automated Bonding (TAB)Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads


Flip-Chip BondingFlip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers


Package-to-Board InterconnectPackage-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount


Package TypesPackage Types


Package ParametersPackage Parameters


Multi-Chip ModulesMulti-Chip Modules

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