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EE1411
© Digital Integrated Circuits2ndCombinational Circuits
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
Designing CombinationalDesigning CombinationalLogic CircuitsLogic Circuits
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolić
November 2002.
EE1412
© Digital Integrated Circuits2ndCombinational Circuits
Combinational vs. Sequential LogicCombinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
CombinationalLogicCircuit
OutInCombinational
LogicCircuit
OutIn
State
EE1413
© Digital Integrated Circuits2ndCombinational Circuits
Static CMOS CircuitStatic CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
EE1414
© Digital Integrated Circuits2ndCombinational Circuits
Static Complementary CMOSStatic Complementary CMOSVDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks…
…
EE1415
© Digital Integrated Circuits2ndCombinational Circuits
NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
EE1416
© Digital Integrated Circuits2ndCombinational Circuits
PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
EE1417
© Digital Integrated Circuits2ndCombinational Circuits
Threshold DropsThreshold DropsVDD
VDD 0PDN
0 VDD
CL
CL
PUN
VDD
0 VDD - VTn
CL
VDD
VDD
VDD |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
EE1418
© Digital Integrated Circuits2ndCombinational Circuits
Complementary CMOS Logic StyleComplementary CMOS Logic Style
EE1419
© Digital Integrated Circuits2ndCombinational Circuits
Example Gate: NANDExample Gate: NAND
EE14110
© Digital Integrated Circuits2ndCombinational Circuits
Example Gate: NORExample Gate: NOR
EE14111
© Digital Integrated Circuits2ndCombinational Circuits
Complex CMOS GateComplex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
EE14112
© Digital Integrated Circuits2ndCombinational Circuits
Constructing a Complex GateConstructing a Complex Gate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifyingsub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
EE14113
© Digital Integrated Circuits2ndCombinational Circuits
Cell DesignCell Design
Standard Cells General purpose logic Can be synthesized Same height, varying width
Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width
EE14114
© Digital Integrated Circuits2ndCombinational Circuits
Standard Cell Layout Methodology – Standard Cell Layout Methodology – 1980s1980s
signals
Routingchannel
VDD
GND
EE14115
© Digital Integrated Circuits2ndCombinational Circuits
Standard Cell Layout Methodology – Standard Cell Layout Methodology – 1990s1990s
M2
No Routingchannels
VDD
GNDM3
VDD
GND
Mirrored Cell
Mirrored Cell
EE14116
© Digital Integrated Circuits2ndCombinational Circuits
Standard CellsStandard Cells
Cell boundary
N Well
Cell height 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objects
Cell height is “12 pitch”
2
Rails ~10
InOut
VDD
GND
EE14117
© Digital Integrated Circuits2ndCombinational Circuits
Standard CellsStandard Cells
InOut
VDD
GND
In Out
VDD
GND
With silicided diffusion
With minimaldiffusionrouting
OutIn
VDD
M2
M1
EE14118
© Digital Integrated Circuits2ndCombinational Circuits
Standard CellsStandard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
EE14119
© Digital Integrated Circuits2ndCombinational Circuits
Two Versions of C Two Versions of C •• (A + B) (A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
EE14120
© Digital Integrated Circuits2ndCombinational Circuits
Multi-Fingered TransistorsMulti-Fingered Transistors
One finger Two fingers (folded)
Less diffusion capacitance
EE14121
© Digital Integrated Circuits2ndCombinational Circuits
Properties of Complementary CMOS Gates Properties of Complementary CMOS Gates SnapshotSnapshot
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)
EE14122
© Digital Integrated Circuits2ndCombinational Circuits
CMOS PropertiesCMOS Properties
Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative
device sizes; ratioless Always a path to Vdd or Gnd in steady state;
low output impedance Extremely high input resistance; nearly zero
steady-state input current No direct path steady state between power and
ground; no static power dissipation Propagation delay function of load capacitance
and resistance of transistors
EE14123
© Digital Integrated Circuits2ndCombinational Circuits
Switch Delay ModelSwitch Delay Model
A
Req
A
Rp
A
Rp
A
Rn CL
A
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
NAND2 INVNOR2
EE14124
© Digital Integrated Circuits2ndCombinational Circuits
Input Pattern Effects on DelayInput Pattern Effects on Delay
Delay is dependent on the pattern of inputs
Low to high transition both inputs go low
– delay is 0.69 Rp/2 CL
one input goes low– delay is 0.69 Rp CL
High to low transition both inputs go high
– delay is 0.69 2Rn CL
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
EE14125
© Digital Integrated Circuits2ndCombinational Circuits
Delay Dependence on Input PatternsDelay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=10
A=1, B=10
A=1 0, B=1
time [ps]
Vo
ltage
[V]
Input Data
Pattern
Delay
(psec)
A=B=01 67
A=1, B=01 64
A= 01, B=1 61
A=B=10 45
A=1, B=10 80
A= 10, B=1 81
NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fF
EE14126
© Digital Integrated Circuits2ndCombinational Circuits
Transistor SizingTransistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
2
2
2 2
11
4
4
EE14127
© Digital Integrated Circuits2ndCombinational Circuits
Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
3
6
6
EE14128
© Digital Integrated Circuits2ndCombinational Circuits
Fan-In ConsiderationsFan-In Considerations
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model (Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.
EE14129
© Digital Integrated Circuits2ndCombinational Circuits
ttpp as a Function of Fan-In as a Function of Fan-In
tpLH
t p (
pse
c)
fan-in
Gates with a fan-in greater than 4 should be avoided.
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
EE14130
© Digital Integrated Circuits2ndCombinational Circuits
ttpp as a Function of Fan-Out as a Function of Fan-Out
2 4 6 8 10 12 14 16
tpNOR2
t p (
pse
c)
eff. fan-out
All gates have the same drive current.
tpNAND2
tpINV
Slope is a function of “driving strength”
EE14131
© Digital Integrated Circuits2ndCombinational Circuits
ttpp as a Function of Fan-In and Fan-Out as a Function of Fan-In and Fan-Out
Fan-in: quadratic due to increasing resistance and capacitance
Fan-out: each additional fan-out gate adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
EE14132
© Digital Integrated Circuits2ndCombinational Circuits
Fast Complex Gates:Fast Complex Gates:Design Technique 1Design Technique 1 Transistor sizing
as long as fan-out capacitance dominates Progressive sizing
InN CL
C3
C2
C1In1
In2
In3
M1
M2
M3
MNDistributed RC line
M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest)
Can reduce delay by more than 20%; decreasing gains as technology shrinks
EE14133
© Digital Integrated Circuits2ndCombinational Circuits
Fast Complex Gates:Fast Complex Gates:Design Technique 2Design Technique 2
Transistor ordering
C2
C1In1
In2
In3
M1
M2
M3 CL
C2
C1In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged1
01charged
charged1
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL
1
1
01 charged
discharged
discharged
EE14134
© Digital Integrated Circuits2ndCombinational Circuits
Fast Complex Gates:Fast Complex Gates:Design Technique 3Design Technique 3
Alternative logic structures
F = ABCDEFGH
EE14135
© Digital Integrated Circuits2ndCombinational Circuits
Fast Complex Gates:Fast Complex Gates:Design Technique 4Design Technique 4
Isolating fan-in from fan-out using buffer insertion
CLCL
EE14136
© Digital Integrated Circuits2ndCombinational Circuits
Fast Complex Gates:Fast Complex Gates:Design Technique 5Design Technique 5
Reducing the voltage swing
linear reduction in delay also reduces power consumption
But the following gate is much slower! Or requires use of “sense amplifiers” on the
receiving end to restore the signal level (memory design)
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
EE14137
© Digital Integrated Circuits2ndCombinational Circuits
Pass-TransistorPass-TransistorLogicLogic
EE14138
© Digital Integrated Circuits2ndCombinational Circuits
Pass-Transistor LogicPass-Transistor LogicIn
puts
Switch
Network
OutOut
A
B
B
B
• N transistors
• No static consumption
EE14139
© Digital Integrated Circuits2ndCombinational Circuits
Example: AND GateExample: AND Gate
B
B
A
F = AB
0
EE14140
© Digital Integrated Circuits2ndCombinational Circuits
NMOS-Only LogicNMOS-Only Logic
VDD
In
Outx
0.5m/0.25m0.5m/0.25m
1.5m/0.25m
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time [ns]
Vo
ltage
[V]
xOut
In
EE14141
© Digital Integrated Circuits2ndCombinational Circuits
NMOS-only SwitchNMOS-only Switch
A = 2.5 V
B
C = 2.5 V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
Threshold voltage loss causesstatic power consumption
VB does not pull up to 2.5V, but 2.5V - VTN
NMOS has higher threshold than PMOS (body effect)
EE14142
© Digital Integrated Circuits2ndCombinational Circuits
NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
EE14143
© Digital Integrated Circuits2ndCombinational Circuits
Restorer SizingRestorer Sizing
0 100 200 300 400 5000.0
1.0
2.0
W/Lr =1.0/0.25 W/Lr =1.25/0.25
W/Lr =1.50/0.25
W/Lr =1.75/0.25
Vol
tage
[V]
Time [ps]
3.0•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stack
EE14144
© Digital Integrated Circuits2ndCombinational Circuits
Solution 2: Single Transistor Pass Gate with Solution 2: Single Transistor Pass Gate with VVTT=0=0
Out
VDD
VDD
2.5V
VDD
0V 2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
EE14145
© Digital Integrated Circuits2ndCombinational Circuits
Complementary Pass Transistor LogicComplementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=AÝ
F=AÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
EE14146
© Digital Integrated Circuits2ndCombinational Circuits
Solution 3: Transmission GateSolution 3: Transmission Gate
A B
C
C
A B
C
C
B
CL
C = 0 V
A = 2.5 V
C = 2.5 V
EE14147
© Digital Integrated Circuits2ndCombinational Circuits
Resistance of Transmission GateResistance of Transmission Gate
Vout
0 V
2.5 V
2.5 VRn
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce
, oh
ms
Rn
Rp
Rn || Rp
EE14148
© Digital Integrated Circuits2ndCombinational Circuits
Pass-Transistor Based MultiplexerPass-Transistor Based Multiplexer
AM2
M1
B
S
S
S F
VDD
GND
VDD
In1
In2
S S
S S
EE14149
© Digital Integrated Circuits2ndCombinational Circuits
Transmission Gate XORTransmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
EE14150
© Digital Integrated Circuits2ndCombinational Circuits
Delay in Transmission Gate NetworksDelay in Transmission Gate Networks
V1 Vi-1
C
2.5 2.5
0 0
Vi Vi+1
CC
2.5
0
Vn-1 Vn
CC
2.5
0
In
V1 Vi Vi+1
C
Vn-1 Vn
CC
In
ReqReq Req Req
CC
(a)
(b)
C
Req Req
C C
Req
C C
Req Req
C C
Req
C
In
m
(c)
EE14151
© Digital Integrated Circuits2ndCombinational Circuits
Delay OptimizationDelay Optimization
EE14152
© Digital Integrated Circuits2ndCombinational Circuits
Transmission Gate Full AdderTransmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
EE14153
© Digital Integrated Circuits2ndCombinational Circuits
Dynamic LogicDynamic Logic
EE14154
© Digital Integrated Circuits2ndCombinational Circuits
Dynamic CMOSDynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors
EE14156
© Digital Integrated Circuits2ndCombinational Circuits
Dynamic GateDynamic Gate
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)
on
off
1
off
on
((AB)+C)
EE14157
© Digital Integrated Circuits2ndCombinational Circuits
Conditions on OutputConditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
EE14158
© Digital Integrated Circuits2ndCombinational Circuits
Properties of Dynamic GatesProperties of Dynamic Gates
Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect
the logic levels Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL
EE14159
© Digital Integrated Circuits2ndCombinational Circuits
Properties of Dynamic GatesProperties of Dynamic Gates
Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND
(including Psc) no glitching higher transition probabilities extra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock
EE14160
© Digital Integrated Circuits2ndCombinational Circuits
Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge Leakage
CL
Clk
Clk
Out
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
Dominant component is subthreshold current
EE14161
© Digital Integrated Circuits2ndCombinational Circuits
Solution to Charge LeakageSolution to Charge Leakage
CL
Clk
Clk
Me
Mp
A
B
Out
Mkp
Same approach as level restorer for pass-transistor logic
Keeper
EE14162
© Digital Integrated Circuits2ndCombinational Circuits
Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge Sharing
CL
Clk
Clk
CA
CB
B=0
A
OutMp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
EE14163
© Digital Integrated Circuits2ndCombinational Circuits
Charge Sharing ExampleCharge Sharing Example
CL=50fF
Clk
Clk
A A
B B B !B
CC
Out
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
EE14164
© Digital Integrated Circuits2ndCombinational Circuits
Charge SharingCharge Sharing
Mp
Me
VDD
Out
A
B = 0
CL
Ca
Cb
Ma
Mb
X
CLVDD CLVout t Ca VDD VTn VX – +=
or
Vout Vout t VDD–CaCL-------- VDD VTn VX
– –= =
Vout VDD
CaCa CL+----------------------
–=
case 1) if Vout < VTn
case 2) if Vout > VTnB 0
Clk
X
CL
Ca
Cb
A
Out
Mp
Ma
VDD
Mb
Clk Me
(Vout and Vx reach the same value)
(Vx reaches Vdd-Vt i.e. Ca /CL small)
EE14165
© Digital Integrated Circuits2ndCombinational Circuits
Solution to Charge RedistributionSolution to Charge Redistribution
Clk
Clk
Me
Mp
A
B
OutMkp
Clk
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
EE14166
© Digital Integrated Circuits2ndCombinational Circuits
Issues in Dynamic Design 3: Issues in Dynamic Design 3: Backgate CouplingBackgate Coupling
CL1
Clk
Clk
B=0
A=0
Out1Mp
Me
Out2
CL2
In
Dynamic NAND Static NAND
=1=0
EE14167
© Digital Integrated Circuits2ndCombinational Circuits
Backgate Coupling EffectBackgate Coupling Effect
-1
0
1
2
3
0 2 4 6
Vol
tage
Time, ns
Clk
In
Out1
Out2
EE14168
© Digital Integrated Circuits2ndCombinational Circuits
Issues in Dynamic Design 4: Clock Issues in Dynamic Design 4: Clock FeedthroughFeedthrough
CL
Clk
Clk
B
A
OutMp
Me
Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
EE14169
© Digital Integrated Circuits2ndCombinational Circuits
Clock FeedthroughClock Feedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In1
In2
In3
In4
Out
In &Clk
Out
Time, ns
Vol
tage
Clock feedthrough
Clock feedthrough
EE14170
© Digital Integrated Circuits2ndCombinational Circuits
Other EffectsOther Effects
Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)
EE14171
© Digital Integrated Circuits2ndCombinational Circuits
Cascading Dynamic GatesCascading Dynamic Gates
Clk
Clk
Out1
In
Mp
Me
Mp
Me
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2V
VTn
Only 0 1 transitions allowed at inputs!
EE14172
© Digital Integrated Circuits2ndCombinational Circuits
Domino LogicDomino Logic
In1
In2 PDN
In3
Me
Mp
Clk
ClkOut1
In4 PDN
In5
Me
Mp
Clk
ClkOut2
Mkp
1 11 0
0 00 1
EE14173
© Digital Integrated Circuits2ndCombinational Circuits
Why Domino?Why Domino?
Clk
Clk
Ini PDNInj
Ini
Inj
PDN Ini PDNInj
Ini PDNInj
Like falling dominos!
EE14174
© Digital Integrated Circuits2ndCombinational Circuits
Properties of Domino LogicProperties of Domino Logic
Only non-inverting logic can be implemented Very high speed
static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort
EE14175
© Digital Integrated Circuits2ndCombinational Circuits
Designing with Domino LogicDesigning with Domino Logic
Mp
Me
VDD
PDN
Clk
In1
In2
In3
Out1
Clk
Mp
Me
VDD
PDN
Clk
In4
Clk
Out2
Mr
VDD
Inputs = 0during precharge
Can be eliminated!