ee2174: digital logic and lab

EE2174: Digital Logic EE2174: Digital Logic and Laband Lab

Professor Shiyan HuProfessor Shiyan Hu

Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering

Michigan Technological UniversityMichigan Technological University

Combinational CircuitCombinational Circuit

Apr 20, 2023

PJF- 2Combinational Logic

OverviewOverview Combinatorial CircuitsCombinatorial Circuits

DefinitionDefinition Divide and ConquerDivide and Conquer

Three Design MethodologiesThree Design Methodologies Gate Library Based DesignGate Library Based Design Full Customer DesignFull Customer Design Programmable Logic Array Based DesignProgrammable Logic Array Based Design

Apr 20, 2023


Combinational CircuitsCombinational Circuits A combinational circuit consists of A combinational circuit consists of

logic gates whose outputs, at logic gates whose outputs, at any any timetime, are determined by combining , are determined by combining the values of the inputs.the values of the inputs.

For For nn input variables, there are 2 input variables, there are 2nn possible binary input combinations.possible binary input combinations.

For each binary combination of the For each binary combination of the input variables, there is one possible input variables, there is one possible output.output.

Apr 20, 2023


Combinational Circuits Combinational Circuits (cont.)(cont.)

Hence, a combinational circuit can be Hence, a combinational circuit can be described by:described by:

1.1. A truth table that lists the output values for A truth table that lists the output values for each combination of the input variables, oreach combination of the input variables, or

2.2. mm Boolean functions, one for each output Boolean functions, one for each output variable.variable.

CombinationalCircuit

n-inputs m-outputs••• •••

Apr 20, 2023


Combinational vs. Sequential Combinational vs. Sequential CircuitsCircuits

Combinational circuits are Combinational circuits are memory-less.memory-less. Thus, the output value depends ONLY on Thus, the output value depends ONLY on the current input values.the current input values.

Sequential circuits consist of Sequential circuits consist of combinational logic as well as memory combinational logic as well as memory elements (used to store certain circuit elements (used to store certain circuit states). Outputs depend on BOTH current states). Outputs depend on BOTH current input values and previous input values input values and previous input values (kept in the storage elements).(kept in the storage elements).

Apr 20, 2023


Combinational vs. Sequential Combinational vs. Sequential CircuitsCircuits


n-inputs m-outputs(Depend only on inputs)


n-inputs

m-outputs

StorageElementsNext

statePresentstate

Sequential Circuit

Combinational Circuit

Apr 20, 2023


Important Design ConceptsImportant Design Concepts

Modern digital design deals with various Modern digital design deals with various methodsmethods and and toolstools that are used to design that are used to design and verify complex circuits and systems. and verify complex circuits and systems.

Important concepts:Important concepts: Design HierarchyDesign Hierarchy Top-Down and Bottom-Up DesignTop-Down and Bottom-Up Design Computer-Aided-Design (CAD) toolsComputer-Aided-Design (CAD) tools Hardware Description Languages (HDLs)Hardware Description Languages (HDLs) Logic SynthesisLogic Synthesis

Apr 20, 2023


Design HierarchyDesign Hierarchy

““Divide-and-Conquer”Divide-and-Conquer” approach approach used to cope with the challenges of used to cope with the challenges of designing complex circuits and designing complex circuits and systems (many times in the order of systems (many times in the order of millions of gates).millions of gates).

Circuit is broken into Circuit is broken into blocksblocks, , repetitively.repetitively.

Challenge: Challenge: VerifyVerify that the block-based that the block-based circuit performs its intended function.circuit performs its intended function.

Apr 20, 2023


Design Hierarchy Design Hierarchy Example: 9-input odd functionExample: 9-input odd function

Apr 20, 2023


Why is Hierarchy useful?Why is Hierarchy useful?

Reduces the complexity required to Reduces the complexity required to design and represent the overall design and represent the overall schematic of the circuit.schematic of the circuit.

ReuseReuse of blocks is possible. Identical of blocks is possible. Identical blocks can be used in various places blocks can be used in various places in a design, or in different designs.in a design, or in different designs.

Apr 20, 2023


Top-Down DesignTop-Down Design

Top-Down

Bottom-Up

Physical/Geometry

StructuralBehavioral

Processor

Hardware Modules

ALUs, RegistersGates, FFs

Transistors

SystemsAlgorithms

Register TransferLogic

Transfer Functions

Architectural

Algorithmic

Functional Block

Logic

Circuit

Rectangles

Cell, Module Plans

Floor Plans

Clusters

Physical Partitions

Gajski and Kuhn’s Y Chart

Apr 20, 2023


Reusable Functions and Reusable Functions and CADCAD Whenever possible, we try to decompose a complex Whenever possible, we try to decompose a complex

design into common, design into common, reusablereusable function blocks function blocks These blocks areThese blocks are

verified and well-documentedverified and well-documented placed in libraries for future useplaced in libraries for future use

Representative Computer-Aided Design Tools:Representative Computer-Aided Design Tools: Schematic CaptureSchematic Capture Logic SimulatorsLogic Simulators Timing VerifiersTiming Verifiers Hardware Description Languages Hardware Description Languages

Verilog and VHDLVerilog and VHDL Logic SynthesizersLogic Synthesizers Integrated Circuit LayoutIntegrated Circuit Layout

Apr 20, 2023


Top-Down versus Bottom-UpTop-Down versus Bottom-Up A A top-down designtop-down design proceeds from an abstract, high-level proceeds from an abstract, high-level

specification to a more and more detailed design by specification to a more and more detailed design by decomposition and successive refinementdecomposition and successive refinement

A A bottom-up designbottom-up design starts with detailed primitive blocks starts with detailed primitive blocks and combines them into larger and more complex and combines them into larger and more complex functional blocksfunctional blocks

Designs usually proceed from both directions Designs usually proceed from both directions simultaneouslysimultaneously Top-down design answers: What are we building? Top-down design answers: What are we building? Bottom-up design answers: How do we build it?Bottom-up design answers: How do we build it?

Top-down controls complexity while bottom-up focuses Top-down controls complexity while bottom-up focuses on the details on the details

Apr 20, 2023


Integrated CircuitsIntegrated Circuits Integrated circuit (informally, a “chip”) is a Integrated circuit (informally, a “chip”) is a

semiconductor crystal (most often silicon) semiconductor crystal (most often silicon) containing the electronic components for the containing the electronic components for the digital gates and storage elements which are digital gates and storage elements which are interconnected on the chip.interconnected on the chip.

Terminology - Levels of chip integrationTerminology - Levels of chip integration SSISSI ( (small-scale integratedsmall-scale integrated) - fewer than 10 gates) - fewer than 10 gates MSIMSI ( (medium-scale integratedmedium-scale integrated) - 10 to 100 gates) - 10 to 100 gates LSILSI ( (large-scale integratedlarge-scale integrated) - 100 to thousands of gates) - 100 to thousands of gates VLSIVLSI ( (very large-scale integratedvery large-scale integrated) - thousands to 100s of ) - thousands to 100s of

millions of gatesmillions of gates

Apr 20, 2023


Technology ParametersTechnology Parameters Specific gate implementation technologies are Specific gate implementation technologies are

characterized by the following parameters:characterized by the following parameters: Fan-inFan-in – the number of inputs available on a gate – the number of inputs available on a gate Fan-outFan-out – the number of standard loads driven by a gate – the number of standard loads driven by a gate

outputoutput Logic Levels Logic Levels – the signal value ranges for 1 and 0 on the – the signal value ranges for 1 and 0 on the

inputs and 1 and 0 on the outputs (see Figure 1-1)inputs and 1 and 0 on the outputs (see Figure 1-1) Noise MarginNoise Margin – the maximum external noise voltage – the maximum external noise voltage

superimposed on a normal input value that will not cause an superimposed on a normal input value that will not cause an undesirable change in the circuit outputundesirable change in the circuit output

Cost for a gateCost for a gate - a measure of the contribution by the gate to - a measure of the contribution by the gate to the cost of the integrated circuitthe cost of the integrated circuit

Propagation DelayPropagation Delay – The time required for a change in the – The time required for a change in the value of a signal to propagate from an input to an outputvalue of a signal to propagate from an input to an output

Power DissipationPower Dissipation – the amount of power drawn from the – the amount of power drawn from the power supply and consumed by the gatepower supply and consumed by the gate

Apr 20, 2023


Propagation DelayPropagation Delay Propagation delay is the time for a change on an input of a Propagation delay is the time for a change on an input of a

gate to propagate to the output.gate to propagate to the output. Delay is usually measured at the 50% point with respect to Delay is usually measured at the 50% point with respect to

the H and L output voltage levels.the H and L output voltage levels. High-to-low (tHigh-to-low (tPHLPHL) and low-to-high (t) and low-to-high (tPLHPLH) output signal ) output signal

changes may have different propagation delays.changes may have different propagation delays. High-to-low (HL) and low-to-high (LH) transitions are High-to-low (HL) and low-to-high (LH) transitions are

defined with respect to the output, defined with respect to the output, notnot the input. the input. An HL input transition causes:An HL input transition causes:

an LH output transition if the gate inverts andan LH output transition if the gate inverts and an HL output transition if the gate does not invert.an HL output transition if the gate does not invert.

Apr 20, 2023


Propagation Delay ExamplePropagation Delay ExampleFind tFind tPHLPHL, t, tPLHPLH and t and tpdpd for the signals given for the signals given

IN (

volt

s)O

UT

(vo

lts)

t (ns)1.0 ns per division

Apr 20, 2023


Fan-out Fan-out Fan-out can be defined in terms of a Fan-out can be defined in terms of a

standard loadstandard load Example: 1 standard load equals the load Example: 1 standard load equals the load

contributed by the input of 1 inverter.contributed by the input of 1 inverter. Transition timeTransition time -the time required for the gate -the time required for the gate

output to change from H to L, toutput to change from H to L, tHLHL, or from L to , or from L to H, tH, tLHLH

The The maximum fan-outmaximum fan-out that can be driven by a that can be driven by a gate is the number of standard loads the gate gate is the number of standard loads the gate can drive without exceeding its specified can drive without exceeding its specified maximummaximum transition timetransition time

Apr 20, 2023


Fan-out and DelayFan-out and Delay The fan-out loading a gate’s output affects The fan-out loading a gate’s output affects

the gate’s propagation delaythe gate’s propagation delay Example:Example:

One realistic equation for tOne realistic equation for tpdpd for a NAND gate for a NAND gate with 4 inputs is:with 4 inputs is:

ttpdpd = 0.07 + 0.021 SL ns = 0.07 + 0.021 SL ns SL is the number of standard loads the gate is SL is the number of standard loads the gate is

driving, i. e., its fan-out in standard loadsdriving, i. e., its fan-out in standard loads For SL = 4.5, tFor SL = 4.5, tpdpd = 0.165 ns = 0.165 ns

Apr 20, 2023


CostCost In an integrated circuit:In an integrated circuit:

The cost of a gate is proportional to the The cost of a gate is proportional to the chip areachip area occupied by the gateoccupied by the gate

The gate area is roughly proportional to the The gate area is roughly proportional to the number and number and size of the transistorssize of the transistors and the and the amount of wiringamount of wiring connecting themconnecting them

Ignoring the wiring area, the gate area is roughly Ignoring the wiring area, the gate area is roughly proportional to the proportional to the gate input countgate input count

So gate input count is a rough measure of gate costSo gate input count is a rough measure of gate cost If the actual chip layout area occupied by the If the actual chip layout area occupied by the

gate is known, it is a far more accurate measure gate is known, it is a far more accurate measure

Apr 20, 2023


Chip Design StylesChip Design Styles Full custom - the entire design of the chip down to the smallest Full custom - the entire design of the chip down to the smallest

detail of the layout is performeddetail of the layout is performed ExpensiveExpensive Justifiable only for dense, fast chips with high sales volumeJustifiable only for dense, fast chips with high sales volume

Standard cell - blocks have been design ahead of time or as part Standard cell - blocks have been design ahead of time or as part of previous designsof previous designs

Intermediate cost Intermediate cost Less density and speed compared to full customLess density and speed compared to full custom

Gate array - regular patterns of gate transistors that can be used Gate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections in many designs built into chip - only the interconnections between gates are specific to a designbetween gates are specific to a design

Lowest costLowest cost Less density compared to full custom and standard cellLess density compared to full custom and standard cell

Apr 20, 2023


Gate Library Based Design Gate Library Based Design MethodologyMethodology

1.1. SpecificationSpecification Write a specification for the circuit if one is not already Write a specification for the circuit if one is not already

availableavailable

2.2. FormulationFormulation Derive a truth table or initial Boolean equations that Derive a truth table or initial Boolean equations that

define the required relationships between the inputs define the required relationships between the inputs and outputs, if not in the specificationand outputs, if not in the specification

3.3. OptimizationOptimization Apply K-map and other optimizationsApply K-map and other optimizations Draw a logic diagram or provide a netlist for the Draw a logic diagram or provide a netlist for the

resulting circuit using ANDs, ORs, and invertersresulting circuit using ANDs, ORs, and inverters

Apr 20, 2023


Design ProcedureDesign Procedure

4.4. Technology MappingTechnology Mapping Map the logic diagram or netlist to the Map the logic diagram or netlist to the

implementation technology selectedimplementation technology selected

5.5. Convert to CMOSConvert to CMOS Replace each gate by its CMOS Replace each gate by its CMOS

implementations implementations

Apr 20, 2023


Design ExampleDesign Example1.1. Specification Specification

BCD to Excess-3 code converterBCD to Excess-3 code converter Transforms BCD code for the decimal digits to Transforms BCD code for the decimal digits to

Excess-3 code for the decimal digitsExcess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit BCD code words for digits 0 through 9: 4-bit

patterns 0000 to 1001, respectivelypatterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-Excess-3 code words for digits 0 through 9: 4-

bit patterns consisting of 3 (binary 0011) added bit patterns consisting of 3 (binary 0011) added to each BCD code wordto each BCD code word

Implementation: Implementation: multiple-level circuitmultiple-level circuit NAND gates (including inverters)NAND gates (including inverters)

Apr 20, 2023


Design Example Design Example (continued)(continued)2.2. FormulationFormulation

Conversion of 4-bit codes can be most easily Conversion of 4-bit codes can be most easily formulated by a truth tableformulated by a truth table

VariablesVariables- - BCDBCD:: A,B,C,D A,B,C,D

VariablesVariables- - Excess-3Excess-3 W,X,Y,Z W,X,Y,Z

Don’t CaresDon’t Cares- BCD 1010- BCD 1010 to 1111 to 1111

Input BCD A B C D

Output Excess-3 WXYZ

0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0

Apr 20, 2023


Design Example Design Example (continued)(continued)

3.3. OptimizationOptimizationa.a. 2-level using2-level using

K-mapsK-mapsW = A + BC + BDW = A + BC + BD

X = C + D + BX = C + D + B

Y = CD + Y = CD +

Z = Z =

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

11

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

11

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1 1

1

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1 1

1

X X X

X X

X

1

1

w

z y

x

B C DB

C DD

Apr 20, 2023


Design Example Design Example (continued)(continued)

3.3. Optimization (continued)Optimization (continued)b.b. Multiple-level using transformationsMultiple-level using transformations

W = A + BC + BDW = A + BC + BDX = C + D + BX = C + D + BY = CD + Y = CD + Z = Z =

Perform extraction, finding factor:Perform extraction, finding factor: TT11 = C + D = C + D

W = A + BTW = A + BT11 X = TX = T11 + B + BY = CD + Y = CD + Z =Z =

B CDBCD

D

B C DC D

D

Apr 20, 2023


Design Example Design Example (continued)(continued)3.3. Optimization (continued)Optimization (continued)

b.b. Multiple-level using transformationsMultiple-level using transformationsTT11 = C + D = C + DW = A + BTW = A + BT11 X = TX = T11 + B + BY = CD + Y = CD + Z =Z =

An additional extraction not shown in the text since it An additional extraction not shown in the text since it uses a uses a Boolean transformationBoolean transformation: ( = C + D = ):: ( = C + D = ):

W = A + BTW = A + BT11

X = TX = T11 + B + B Y = CD + Y = CD + Z =Z =

B CDCD

D

B T1

DT1

CD T1

Apr 20, 2023


Design Example Design Example (continued)(continued)4.4. Technology Mapping Technology Mapping

• Mapping with a library containing inverters and Mapping with a library containing inverters and 2-input NAND, 2-input NOR, and 2-2 AOI gates 2-input NAND, 2-input NOR, and 2-2 AOI gates

A

B

C

D

W

X

Y

Z

A

B

CD

W

X

Y

Z

Design Example (continued)Design Example (continued)

5. Convert to CMOS through 5. Convert to CMOS through replacing each gate to its CMOS replacing each gate to its CMOS implementationimplementation

Apr 20, 2023

PJF - 30Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)

Apr 20, 2023


Technology MappingTechnology Mapping Mapping TechniquesMapping Techniques

NAND gatesNAND gates NOR gatesNOR gates MUX gatesMUX gates Multiple gate typesMultiple gate types

Apr 20, 2023


Mapping to NAND gatesMapping to NAND gates

Assumptions:Assumptions: Gate loading and delay are ignoredGate loading and delay are ignored Cell library contains an inverter and Cell library contains an inverter and nn-input NAND gates, -input NAND gates,

nn = 2, 3, … = 2, 3, … An AND, OR, inverter schematic for the circuit is An AND, OR, inverter schematic for the circuit is

availableavailable

The mapping is accomplished by:The mapping is accomplished by: Replacing AND and OR symbols,Replacing AND and OR symbols, Pushing inverters through circuit fan-out points, andPushing inverters through circuit fan-out points, and Canceling inverter pairsCanceling inverter pairs

Apr 20, 2023


NAND Mapping AlgorithmNAND Mapping Algorithm1.1. Replace ANDs and ORs:Replace ANDs and ORs:

2.2. Repeat the following pair of actions until Repeat the following pair of actions until there is at most one inverter between :there is at most one inverter between :

a.a. A circuit input or driving NAND gate output, A circuit input or driving NAND gate output, andand

b.b. The attached NAND gate inputs.The attached NAND gate inputs.

.

.

....

.

.

....

.

.

....

Apr 20, 2023


NAND Mapping ExampleNAND Mapping ExampleA

B

C

D

F

E

(a)

AB

C7

5

1

6

2

4

9

X

Y

38DE

F

(b)

AB

C

D

E

F

(d)

X

5

5

7

6Y

(c)

OI

Full Custom Design Full Custom Design MethodologyMethodology

Similar to the CMOS implementation for Combinational GateSimilar to the CMOS implementation for Combinational Gate

Apr 20, 2023

Combinational LogicPJF - 35

Programmable Logic ArrayProgrammable Logic Array The set of functions to be implemented is first transformed The set of functions to be implemented is first transformed

to product termsto product terms Since output inversion is available, terms can implement Since output inversion is available, terms can implement

either a function or its complementeither a function or its complement

Apr 20, 2023


Programmable Logic Array Programmable Logic Array ExampleExample

To implementTo implement F1= A’B’C+A’BC’+AB’C’=(AB+AC+BC+A’B’C’)’F1= A’B’C+A’BC’+AB’C’=(AB+AC+BC+A’B’C’)’ F2=AB+AC+BCF2=AB+AC+BC

Apr 20, 2023


Programmable Logic Array Programmable Logic Array ExampleExample

Apr 20, 2023


XFuse intactFuse blown

01

F1

F2

A

B

C

C B AC B A

1

2

4

3

X X

X X

X X

X XX

X

X

X X

X

X

X

X

X

SummarySummary

Three design stylesThree design styles Full custom designFull custom design Gate library based designGate library based design PLA based designPLA based design

2023.04.20Combinational Lo

gic PJF- 39

ee2174: digital logic and lab

Documents

combinational logic

combinational logictop

combinational logicwhy

complex circuits

digital logic

current input values

previous input values

design hierarchytop