ee241 - spring 2011bwrcs.eecs.berkeley.edu/.../lecture5-models2.pdf · 3 velocity saturation l in...
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EE241 Spring 2011EE241 - Spring 2011Advanced Digital Integrated Circuits
Lecture 5: Transistor Models: I-V, Q-V, leakageleakage
Outline
Device I-V, Q-V models
Reading: Rabaey, LPDE, Ch. 2, papers from the website
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Device ModelsDevice Models
Drain Current
Current model
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l Saturation condition
LEVV
VVLEC
L
WI
CThGS
ThGSCoxeffDSat
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2
4
LEVV
LEVVV
CThGS
CThGSDSat
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Velocity Saturation
l In 0.13m technology, ECL is about 0.5VGS + 0.7V
l Can calculate VDSat (VTh ~ 0.25V)
VGS [V] 0.2 0.4 0.6 0.8 1.0 1.2
VDSat [V] 0 0.13 0.26 0.37 0.46 0.55
DSat ( Th )
l For VGS – VTh << ECL, (VGS < 1V)VDSat is close to VGS-VTh
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DSat GS Th
l For large VGS, VDSat would start bending upwards toward ECL, but we won’t even notice it with 1.2V supply.
l Therefore ECL can be frequently approximated with a constant term (ECL = 1.2V in 0.13m)
Velocity Saturation
7001 2V
200
300
400
500
600
I DS
[V]
0 6V
0.8V
1.0V
1.2V
6
0
100
0 0.2 0.4 0.6 0.8 1 1.2
V DS [V]
0.4V
0.6V
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Output Resistance
Slope in I-V characteristics caused by:Channel length modulation
Drain-induced barrier lowering (DIBL)
Both effects increase the saturation current beyond the saturation point
The simulations show approximately linear
Substrate current induced body effect
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dependence of Ids on Vds in saturation.
[BSIM 3v3 Manual]
Output Resistance
Channel length modulationAs the drain voltage increases beyond the saturation
lt V th t ti i t li htl l t voltage Vdsat, the saturation point moves slightly closer to the source (L)The equation is modified by replacing L with LTaylor expansion Ids = Idsat(1 + Vds/VA)
VGS
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L
S D
VDSG
Vdsatn n
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Output Resistance
DIBLIn a short channel device, source-drain distance is comparable to the depletion region widths, and the drain voltage can modulate the threshold
VTh = VTh - Vds
Taylor expansion
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ChannelL (D)0 (S)
Long channel
Short channel Vds = 0.2V Vds = 1.2V
[Taur, Ning]
Other Models: Alpha Power Law Model
Simple model, sometimes useful for hand analysis
ThGSoxDS VVCL
WI
2l Parameter is between
1 and 2.
l In 0.13 - 0.25m
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technology ~ 1.2.
[Sakurai, Newton, JSSC 4/90]
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Alpha Power Law Model
This is not a physical model
Simply empirical:p y pCan fit (in minimum mean squares sense) to variety of ’s, VTh
Need to find one with minimum square error – fitted VThcan be different from physical
Can also fit to 1
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Can also fit to = 1
What is VTh?
K(VGS –VTHZ) Model ( = 1)
Drain current vs. gate-source voltage
8 0E-04
4.0E-04
6.0E-04
8.0E 04
I DS
[A
]
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0.0E+00
2.0E-04
0 0.2 0.4 0.6 0.8 1 1.2
V GS [V]VTHZ
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Application of Models: NAND Gate
2-input NAND gate VDD
Out
B
A
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Sizing for equal transistions:• P/N ratio (-ratio) of 1.6 about• Upsizing stacks by a factor proportional to the stack height
Transistor Stacks
With transistor stacks, VDS,VGS reduce.Unified model assumes outVUnified model assumes VDSat = const.For a stack of two, appears that both have exactly double Rekv of an inverter with the same width
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Therefore, doubling the size of each, should make the pull down R equivalent to an inverter
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Velocity Saturation
As (VGS-VTh)/ECL changes, the depth of saturation changes
LEVV
VVLEC
L
WI
CThGS
ThGSCoxeffDSat
2
2
l For VGS, VDS = 1.2V, ECL is 1.3V l With double length, ECL is 2.6V (in this model)
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l Stacked transistors are less saturatedl VGS-VTh = 0.95V, IDSat ~ 2/3 of inverter IDSat (63%)l Therefore NAND2 should have pull-down sized 1.5Xl Check any library NAND2’s
Velocity Saturation
How about NAND3?
IDSat = 1/2 of inverter IDSat (instead of 1/3)
How about PMOS networks?
NOR2 – 1.8x, NOR3 – 2.4x
What is ECL for PMOS?
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Saturation Currents
Model Usage
WDelay estimates with VDD >> VTH
Long channel devices (rare in digital)
Delay estimates in a wider range of VDD’s
DS GS THZ
WI K V V
L
2
oxDS GS TH
CWI V V
L
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oxDS GS TH
CWI V V
L
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Universal model, easy to remember, does not handle stacks correctly
Handles stacks correctly
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2Dsat
DS ox GS TH DsatVW
I C V V VL
2
2C GS THox
DSGS TH C
E L V VCWI
L V V E L
Transistor Leakage
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Transistor Leakage
2.5
3
3.5
1m
Subthreshold slope
0
0.5
1
1.5
2
IDS
[uA
]
100u
1u
10u
19Leakage current is exponential with VGS
VDS = 1V
-1
-0.5
0 10 20 30 40 50 60 70 80 90 100
VGS [V]
100n
0 10.5
Transistor Leakage (130nm)
6
8
2
4
I DS
[nA
]
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Two effects:• diffusion current (like a bipolar transistor)• exponential increase with VDS (DIBL)
00 0.2 0.4 0.6 0.8 1 1.2 1.4
V DS [V]
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Transistor Leakage (45nm PTM)
100
120
20
40
60
80ID
S [n
A]
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Another view of DIBL>10x increase in leakage
0
20
0 20 40 60 80 100 120
VDS[V]
0. 0. 0. 0. . .
Subthreshold Current
Subthreshold behavior can be modeled physically
qkTVds
qkTmThVgV
ds eeq
kT
L
WI 1
2
[Taur Ning]
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S
dsVThVgsV
ds W
WII
100
0
Or: [Taur, Ning]
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Leakage Components
23Courtesy of IEEE Press, New York. 2000
Leakage Components
1. pn junction reverse bias current
2. Weak inversion
3. Drain-induced barrier lowering (DIBL)
4. Gate-induced drain leakage (GIDL)
5. Punchthrough
6. Narrow width effect
7. Gate oxide tunneling
8. Hot carrier injection
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j
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Leakage Components
Drain-induced barrier lowering (DIBL)Voltage at the drain lowers the source potential barrier
Lowers VTh, no change on S
Gate-induced drain leakage (GIDL)High field between gate and drain increases injection of carriers into substrate -> leakage (band-to-band leakage)
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Transistor C-V
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MOS Transistor as a Switch
Discharging a capacitor• Can solve:
DS DS DSi i v
DSDS DS
dvi C v
dt
+
-
vDSiDS
vGS
C
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• Prefer using equivalent resistances• Find tpHL
• Find equivalent C, R ,
( )dDS DSpHL
DS GS DS
C v vt
i v v
MOS Capacitances
Gate Capacitance
CGSO = CGDO
= C xdW
p
Overlap Capacitance
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= CoxxdW
= CoW(often lump fringe capinto it)
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MOS Capacitances
Gate capacitanceNon-linear channel capacitance
Linear overlap, fringing capacitances
Miller effect on overlap, fringing capacitance
Non-linear drain diffusion capacitancePN junction
Wiring capacitances
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g pLinear
Gate-Channel Capacitance
G
CGC
G
CGC
G
CGC
S D S D S D
Cut-off Resistive Saturation
CGB CGS CGD
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+ overlap
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Gate and Drain CapacitancesGate capacitance
0.13um Cgs/um vs. Vgs
1 2E 15
1.4E-15
1.6E-15
1.8E-15
2.0E-15
0.13um Cdb/um vs . V ds
1 60E 15
1.80E-15
2.00E-15
db
(F
)
Drain capacitance
0.0E+00
2.0E-16
4.0E-16
6.0E-16
8.0E-16
1.0E-15
1.2E-15
0.0 0.4 0.8 1.2
Vgs [V]
Cgs
[F
]
NMOS VDS=VDD
PMOS VDS=VDD
NMOS VDS=0
PMOS VDS=0
310.00E+00
2.00E-16
4.00E-16
6.00E-16
8.00E-16
1.00E-15
1.20E-15
1.40E-15
1.60E-15
0.0 0.4 0.8 1.2
Vds (V)
Cd
NMOS VGS=0
PMOS VGS=0
Gate Capacitances
Gate capacitance is non-linearFirst order approximation with CoxWL (CoxL = 1.5fF/m)pp ox ( ox )
Need to find the actual equivalent capacitance by simulating it
Since this is a linear approximation of non-linear function, it is valid only over the certain range
Different capacitances for HL LH transitions and power
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Different capacitances for HL, LH transitions and power computation
Drain capacitance non-linearity compensatesBut this changes with fanout
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Gate Capacitance vs. VTh, VDD
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Nose, Sakurai, ISLPED’00
Gate Capacitance with Scaling
High-k allows for EOT scaling, increases Cgate
But some of it is masked by But some of it is masked by fringe/overlap caps
Scaling advantageTransconductance increases
If fringe cap can be controlled, win on power
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Next Lecture
Delay modeling
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