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EECS 151/251ASpring2019 DigitalDesignandIntegratedCircuits

Instructor:JohnWawrzynek

Lecture 16

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Memory Circuits

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General Latch Design

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Storage principles• Hardwired (Read-only-memory- ROM) • Programmable

• Volatile • Feedback to hold state while power is on

• Non-volatile • Persistent state without power supplied

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Volatile Storage Mechanisms

D

CLK

CLK

Q

Dynamic - chargeStatic - feedback

D D

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Basic Static Storage Element

D D

▪ If D is high, D_b will be driven low - Which makes D stay high

▪ Positive feedback ▪ Tolerant to noise and other small disturbances

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A Static Latch

D

Enable

Access transistor must be able to overpower the feedback.

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Addressing the write problem

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Implemented with a MUX.

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

clk’

clk

clk

clk’

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Memories

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Semiconductor Memory Classification

Read-Write MemoryNon-Volatile Read-Write

MemoryRead-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO

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Storage Mechanisms

D

CLK

CLK

Q

Dynamic (DRAM)Static (SRAM)

D D

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C

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Memory Architecture Overview

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❑ Word lines used to select a row for reading or writing

❑ Bit lines carry data to/from periphery

❑ Core aspect ratio keep close to 1 to help balance delay on word line versus bit line

❑ Address bits are divided between the two decoders

❑ Row decoder used to select word line

❑ Column decoder used to select one or more columns for input/output of data

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Memory - SRAM

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Memory CellsComplementary data values are written (read) from two sides

D

Enable

D

Enable

D

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WL2

WL0

WL3

BLBL_B

WL2

WL0

WL3

BLBL_B

Cells stacked in 2D to form memory core.

WL2

WL0

WL3

BLBL_B

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SRAM read/write operations

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WL

BL

VDD

M5 M6

M4

M1

M2

M3

BL

QQ

6-Transistor CMOS SRAM Cell

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SRAM Operation - Read

BL

WL

BL10

During read Q will get pulled up when WL first goes high, but …

• Reading the cell should not destroy the stored value

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1. Bit lines are “pre-charged” to VDD 2. Word line is driven high (pre-charger is turned off) 3. Cell pulls-down one bit line 4. Differential sensing circuit on periphery is activated to capture value on bit lines.

Q

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WL

BLVDD

M 5M 6

M 4

M1 VDDVDD VDD

BL

Q = 1Q = 0

Cbit Cbit

CMOS SRAM Analysis (Read)

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SRAM Operation - Write

BL

WL

BL1-0 0-1

For successful write the access transistor needs to overpower the cell pullup

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1. Column driver circuit on periphery differentially drives the bit lines

2. Word line is driven high (column driver stays on) 3. One side of cell is driven low, flips the other side

Q_b

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CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0Q = 1

M1

M4

M5M6

VDD

VDD

WL

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Size width ratio between PMOS pull-up and NMOS access

W4 /L4

W6 /L6

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6T-SRAM — Layout

VDD

GND

WL

BL BLB

VDD and GND: in M1 Bitlines: M2 Wordline: poly-silicon

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65nm SRAM

❑ ST/Philips/Motorola

Access Transistor

Pull down Pull up

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Memory Periphery

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Periphery

❑ Decoders ❑ Sense Amplifiers ❑ Input/Output Buffers ❑ Control / Timing Circuitry

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Row Decoder • Expands L-K address lines into 2L-K word lines

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❑ Example: decoder for 8Kx8 memory block ❑ core arranged as

256x256 cells ❑ Need 256 AND gates,

each driving one word line

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Row Decoders

Collection of 2K logic gates, but need to be dense and fast.

(N)AND Decoder

NOR Decoder

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Predecoders❑ Use a single gate for

each of the shared terms ▪ E.g., from

generate four signals: ▪

❑ In other words, we are decoding smaller groups of address bits first ▪ And using the

“predecoded” outputs to do the rest of the decoding

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a5 a4 a3 a2 a1 a0

a5 a4 a3 a2 a1 a0a5 a4 a3 a2 a1 a0a5 a4 a3 a2 a1 a0a5 a4 a3 a2 a1 a0a5 a4 a3 a2 a1 a0

a5 a4 a3 a2 a1 a0

a5 a4 a3 a2 a1 a0

a5 a4 a3 a2 a1 a0a5 a4 a3 a2 a1 a0a5 a4 a3 a2 a1 a0

a5 a4 a3 a2 a1 a0

a1, a1, a0, a0

a1 a0 , a1 a0 , a1 a0 , a1 a0

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Predecoder and DecoderA0 A1 A4 A5A2 A3

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Column “Decoder”

❑ Is basically a multiplexer ❑ Each row contains 2K

words each M bit wide. ❑ Bit of each of the 2K are

interleaved ❑ ex: K=2, M=8

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d7c7b7a7d6c6b6a6d5c5b5a5d4c4b4a4d3c3b3a3d2c2b2a2d1c1b1a1d0c0b0a0

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4-input pass-transistor based Column Decoder

Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path

2-input NOR decoder

A 0 S0

BL0 BL1 BL2 BL3

A 1

S1

S2

S3

D

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decoder shared across all 2K x M row bits

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SenseAmplifiers

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Sense Amplifiers

make as small as possible

small

large

Idea: Use Sense Amplifer

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τp =C ⋅ ΔV

Iav

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Differential Sense Amplifier

Directly applicable toSRAMs

M4

M1

M5

M3

M2

VDD

bitbit

SE

Outy

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Differential Sensing ― SRAM

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Memory - DRAM

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No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = V WWL -VTn

WWLBL 1

M1 X

M3

M2

CS

BL 2

RWL

VDDVDD - VT

DVVDD - VTBL 2

BL 1

X

RWL

WWL

3-Transistor DRAM Cell

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Can work with a normal logic IC process

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Write: C S is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

1-Transistor DRAM Cell

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VBL

CS << CBL

VBIT= 0 or (VDD – VT)

❑ To get sufficient Cs, special IC process is used ❑ Cell reading is destructive, therefore read operation always is followed by a

write-back ❑ Cell looses charge (leaks away in ms - highly temperature dependent),

therefore cells occasionally need to be “refreshed” - read/write cycle

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Latch-Based Sense Amplifier (DRAM)

• Initialized in its meta-stable point with EQ • Once adequate voltage gap created,

sense amp enabled with SE • Positive feedback quickly forces output to

a stable operating point.

EQ

VDD

BL BL

SE

SE

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Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layerCell plateWord lineInsulating Layer

IsolationTransfer gateStorage electrode

Advanced 1T DRAM Cells

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Multi-ported memory

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Multi-ported Memory❑ Motivation:

▪ Consider CPU core register file: – 1 read or write per cycle limits

processor performance. – Complicates pipelining. Difficult for

different instructions to simultaneously read or write regfile.

– Common arrangement in pipelined CPUs is 2 read ports and 1 write port.

data buffer

disk or network interface

CPU– I/O data buffering:

Aa Dina WEa

Ab Dinb

WEb

Dual-port Memory

Douta

Doutb

• dual-porting allows both sides to simultaneously access memory at full bandwidth.

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Dual-ported Memory Internals❑ Add decoder, another set of

read/write logic, bits lines, word lines:

deca decbcell

array

r/w logic

r/w logic

data portsaddress

ports

• Example cell: SRAM

• Repeat everything but cross-coupled inverters.

• This scheme extends up to a couple more ports, then need to add additional transistors.

b2 b2b1 b1

WL2

WL1