eecs 482 introduction to operating...
TRANSCRIPT
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EECS 482Introduction to Operating
Systems
Fall 2019
Baris Kasikci
Slides by: Harsha V. Madhyastha
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Base and bounds● Load each process into contiguous region of
physical memory• Prevent process from accessing data outside its region• Base register: starting physical address• Bound register: size of region
physicalmemory
base + bound
base
0
boundvirtual
memory
0
February 20, 2019 EECS 482 – Lecture 12 2
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Base and bounds● Pros?
• Fast• Simple hardware support
● Cons?• Virtual address space limited by physical memory• No controlled sharing• External fragmentation
February 20, 2019 EECS 482 – Lecture 12 3
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Base and bounds● Can’t share part of an address space between
processes
physicalmemory
data (P2)
data (P1)
code
virtualaddressspace 1
data
code
virtualaddressspace 2
data
code
February 20, 2019 EECS 482 – Lecture 12 4
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External fragmentation● Processes come and go, leaving a mishmash
of available memory regions• Wasted memory between allocated regions
P2
P3
P1
P4
February 20, 2019 EECS 482 – Lecture 12 5
P5
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Growing address space
How can stack and heap grow independently?
February 20, 2019 EECS 482 – Lecture 12 6
physicalmemory
base + bound
base
0
boundvirtual
memory
0
StackHeap
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Segmentation● Divide address space into segments
● Segment: region of memory contiguous in both physical memory and in virtual address space
• Multiple segments of memory with different base and bounds.
February 20, 2019 EECS 482 – Lecture 12 7
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Segmentationphysicalmemory
46ff
4000code
2fff
2000
stack
4ff0 data
virtualmemory
segment 3
fff
0
stack
virtualmemory
segment 1
4ff0 data
virtualmemory
segment 0
6ff
0code
EECS 482 – Lecture 12 8February 20, 2019
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Segmentation
● Virtual address is of the form: (segment #, offset)• Physical address = base for segment + offset
● Many ways to specify the segment #• High bits of address• Special register• Implicit to instruction opcode
February 20, 2019 EECS 482 – Lecture 12 9
Segment # Base Bounds Description0 4000 700 code segment1 0 500 data segment2 n/a n/a unused3 2000 1000 stack segment
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Segmentation
● Physical address for virtual address (3, 100)?• 2100
● Physical address for virtual address (0, ff)?• 40ff
● Physical address for virtual address (2, ff)?● Physical address for virtual address (1, 2000)?
February 20, 2019 EECS 482 – Lecture 12 10
Segment # Base Bounds Description0 4000 700 code segment1 0 500 data segment2 n/a n/a unused3 2000 1000 stack segment
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Segmentation● Not all virtual addresses are valid
• Valid à region is part of process’s address space• Invalid à virtual address is illegal to access
» Accessing an invalid virtual address causes a trap to OS (usually resulting in core dump)
● Reasons for virtual address being invalid?• Invalid segment number• Offset within valid segment beyond bound
February 20, 2019 EECS 482 – Lecture 12 11
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Segmentation● How to grow a segment?
● Different segments can have different protection• E.g., code is usually read only (allows fetch, load)• E.g., data is usually read/write (allows fetch, load, store)• Fine-grained protection in base and bounds?
● What must be changed on a context switch?
February 20, 2019 EECS 482 – Lecture 12 12
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Benefits of Segmentation● Multiple areas of address space can grow
separately● Easy to share part of address space
February 20, 2019 EECS 482 – Lecture 12 13
Segment # Base Bounds Description0 4000 700 code segment1 0 500 data segment3 2000 1000 stack segment
Segment # Base Bounds Description0 4000 700 code segment1 1000 300 data segment3 500 1000 stack segment
Process 1
Process 2
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Drawbacks of Segmentation● Have we eliminated external fragmentation?
● Can an address space be larger than physical memory?
● How can we:• Make memory allocation easy• Not have to worry about external fragmentation• Allow address space size to be > physical memory
February 20, 2019 EECS 482 – Lecture 12 14
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Project 2● Due on Monday
• Check calendar on web page for extra office hours
● For every thread, think about “where is the current context?”
● Think about memory leaks and how to test if they exist
● Think about why your thread library may cause a program to run for longer than correct library
February 20, 2019 EECS 482 – Lecture 12 15
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Project 2● Due on Monday
• Check calendar on web page for extra office hours
● I have office hours on Sunday
February 20, 2019 EECS 482 – Lecture 12 16
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Drawbacks of Segmentation● Have we eliminated external fragmentation?
● Can an address space be larger than physical memory?
● How can we:• Make memory allocation easy• Not have to worry about external fragmentation• Allow address space size to be > physical memory
February 20, 2019 EECS 482 – Lecture 12 17
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Drawbacks of Segmentation
February 20, 2019 EECS 482 – Lecture 12 18
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Paging● Allocate physical memory in fixed-size units
(pages)• Any free physical page can store any virtual page
February 20, 2019 EECS 482 – Lecture 12 19
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Paging● Virtual address is split into
• Virtual page # (high bits of address, e.g., bits 31-12)• Offset (low bits of address, e.g., bits 11-0, for 4 KB page
size)
February 20, 2019 EECS 482 – Lecture 12 20
Address Space
Page 1
Page 2
Page 3
Page N
Physical Memory
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Paging● Translation data is the page table
● Why no column for bound?● How do I check whether offset is within bound?● One entry per virtual page à Lots of entries!
February 20, 2019 EECS 482 – Lecture 12 21
Virtual page # Physical page #0 1051 152 2833 invalid... invalid1048575 invalid
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February 20, 2019 EECS 482 – Lecture 12 22
Page Lookups
Page frame
Page number OffsetVirtual Address
Page TablePage frame Offset
Physical Address
Physical Memory
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Paging● Translating virtual address to physical addressif (virtual page is invalid) {
trap to OS fault handler} else {
physical page # = pageTable[virtual page #].physPageNum}
● What must be changed on a context switch?• Page table (but can be large)• Use indirection: Page Table Base Register
» Points to physmem address of page table
February 20, 2019 EECS 482 – Lecture 12 23
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Paging out● Each virtual page can be in physical memory or
“paged out” to disk● How does processor know that a virtual page is not in
physical memory?
February 20, 2019 EECS 482 – Lecture 12 24
Virt. page # Phys. page # resident0 105 1
1 15 0
2 283 1
3 invalid
… invalidif (virtual page is invalid or non-resident) {
trap to OS fault handler; retry} else {
physical page # = pageTable[virtual page #].physPageNum}
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Paging● Like segments, pages can have different
protections (e.g., read, write, execute)
if (virtual page is invalid or non-resident or protected) {trap to OS fault handler; retry
} else {physical page # = pageTable[virtual page #].physPageNum
}
February 20, 2019 EECS 482 – Lecture 12 25
Virt. page # Phys. page # resident protected0 105 1 0
1 15 0 0
2 283 1 1
3 invalid
… invalid
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Valid versus resident● Valid à virtual page is legal for process to access● Resident à virtual page is in physical memory● Error to access invalid page, but not to access
non-resident page
● Who makes a virtual page resident/non-resident?● Who makes a virtual page valid/invalid?● Why would a process want one of its virtual
pages to be invalid?
February 20, 2019 EECS 482 – Lecture 12 26
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Picking Page Size● What happens if page size is really small?● What happens if page size is really big?
● Typically a compromise, e.g., 4 KB or 8 KB• Some architectures support multiple page sizes
February 20, 2019 EECS 482 – Lecture 12 27
What must be changed on a context switch?
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February 20, 2019 EECS 482 – Lecture 12 28
Growing Address Space
Stack
Code
Heap
Virtual page # Physical page #0 1051 152 2833 invalid... invalid1048572 invalid1048573 10781048574 481361048575 60
How is this better than base and bounds?
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Paging● Pros?
• Flexible memory allocation/growing address space• Virtual memory• No external fragmentation• Flexible sharing
● Cons?• Large page tables
● How to modify paging to reduce space needed for translation data?
February 20, 2019 EECS 482 – Lecture 12 29
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Multi-level Paging● Standard page table is a simple array● Multi-level paging generalizes this into a tree
● Example: Two-level page table with 4KB pages• Index into level 1 page table: virtual address bits 31-22• Index into level 2 page table: virtual address bits 21-12• Page offset: bits 11-0
February 20, 2019 EECS 482 – Lecture 12 30
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Multi-level Paging
How does this let translation data take less space?February 20, 2019 EECS 482 – Lecture 12 31
level 1page table 0 1 2 3
virtual addressbits 21-12
physical page #
0 101 152 203 2
level 2page tables
virtual addressbits 21-12
physical page #
0 301 42 83 3
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February 20, 2019 EECS 482 – Lecture 12 32
Sparse Address Space
Stack
Code
Heap
Virtual page # Physical page #0 1051 152 2833 invalid... invalid1048572 invalid1048573 10781048574 481361048575 60
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Sparse Address Space
February 20, 2019 EECS 482 – Lecture 12 33
Bits 21-12 Physical page #0 1051 152 2833 invalid... invalid
Bits 31-22 Physical page #0 3891 invalid2 invalid… invalid1021 invalid1022 invalid1023 7046
Bits 21-12 Physical page #... invalid1020 invalid1021 10781022 481361023 60
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Multi-level paging● How to share memory between address spaces?
● What must be changed on a context switch?
● Pros:• Easy memory allocation• Flexible sharing• Space efficient for sparse address spaces
● Cons?• Two extra lookups per memory reference
February 20, 2019 EECS 482 – Lecture 12 34
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Translation lookaside buffer● TLB caches virtual page # to PTE mapping
• Cache hit à Skip all the translation steps• Cache miss à Get PTE, store in TLB, restart
instruction
● Does this change what happens on a context switch?
February 20, 2019 EECS 482 – Lecture 12 35