eee-dsp qb-unit1-unit5 (2m and 16m qstn only)

7/26/2019 EEE-DSP QB-unit1-Unit5 (2m and 16m Qstn Only)

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UNIT IINTRODUCTION TO SIGNALS AND SYSTEMS

PART A (2 MARKS)

1. Defne even and odd signals.2. State the disadvantages o digital signal processing over analog process.3. Check whether the ollowing system is time-variant y(n!n"2(n.#. $hat are the di%erent types o signal representation&'. Defne D) pair.*. Defne the ollowing (a System (+ Discrete-time system,. ist the merits and demerits o DS/

0. $hen discrete time signals called as periodic signals&. $rite properties o convoltion.1. $hat is static and dynamic system&11. $hat are the classifcation o discrete-time systems&12. $hat is linear and non-linear system&13. State sampling theorem.1#. $hat is an anti-aliasing flter&1'. $hat is aliasing e%ect&1*. $hat is a Casal system&1,. $hat is S4S5 system and 6465 system&10. Defne a Sta+le System.

1. $hat is an )4 system&2. $hat is a Shit invariant (or )ime-invariant system&21. Defne 7anti8ation.

PART B

1. 9"plain in detail a+ot the classifcation o discrete time systems. (1*2. (a Descri+e the di%erent types o discrete time signal representation. (*(+ Defne energy and power signals. Determine whether a discrete time nitstepsignal "(n ! (n is an energy signal or a power signal. (13. (a :ive the varios representation o the given discrete time signal"(n ! ;-1


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(+ :ive the classifcation o signals and e"plain it. (*#. (a Draw and e"plain the ollowing se>ences/i ?nit sample se>enceii ?nit step se>enceiii ?nit ramp se>ence

iv Sinsoidal se>ence andv @eal e"ponential se>ence (1(+ Determine i the system descri+ed +y the ollowing e>ations are casalor noncasali y(n ! "(n A (1 B ("(n-1 ii y(n ! "(n2 (*'. Determine the vales o power and energy o the ollowing signals. indwhether thesignals are power< energy or neither energy nor power signals.i "(n ! (1B3n (n ii "(n ! e((B2n A (B#iii "(n ! sin (B#n iv "(n ! e2n (n (1**. (a Determine i the ollowing systems are time-invariant or time-variant

i y(n ! "(n A "(n-1 ii y(n ! "(-n (#(+ Determine i the system descri+ed +y the ollowing inpt-otpte>ations arelinear or non-linear.i y(n ! "(n A (1 B ("(n-1 ii y(n ! "2(n iii y(n ! n"(n (12

,. )est i the ollowing systems are sta+le or not.i y(n ! cos "(n ii y(n ! a"(n

iii y(n ! "(n en iv y(n ! a"(n (1*0. (a Determine the sta+ility o the system y(n E ('B2y(n-1 A y(n-2 ! "(nE "(n-1 (0(+ FrieGy e"plain a+ot >anti8ation. (0. (a 9"plain the principle o operation o analog to digital conversion with aneatdiagram. (0(+ 9"plain the signifcance o Hy>ist rate and aliasing dring the samplingocontinos time signals. (01. (a ist the merits and demerits o Digital signal processing. (0

(+ $rite short notes a+ot the applications o DS. (0

UNIT IIDISCRETE TIME SYSTEM ANALYSIS

PART A (2 MARKS)1. Defne I-transorm.


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2. $hat is meant +y @egion o convergence&3. $hat are the properties o @5C. ist the properties o 8-transorm.'. 9"plain the linear property o 8-transorm.*. 9"plain the time-shiting property o 8-transorm.

,. $hat are the di%erent methods o evalating inverse 8-transorm&0. $hat are the properties o re>ency response J(eiK o an )4 system&. $hat is the necessary and sLcient condition on the implse response osta+ility&1. Distingish +etween inear convoltion and circlar convoltion.11. Jow will yo o+tain linear convoltion rom circlar convoltion&12. $hat is meant +y sectioned convoltion&

13. $hat are the two methods sed or te sectional convoltion&1#. Distingish +etween 5verlap add and 5verlap save method.1'. Distingish +etween D) and D)).1*. Distingish +etween orier series and orier transorm.

PART B1. (a 5+tain the transer nction and implse response o the )4 systemdefned +yy(n-2A'y(n-1A*y(nA"(n (0(+ State and prove convoltion property o discrete time orier transorm.(0

2. (a State and prove any tow properties o 8-transorm. (0(+ ind the 8-transorm and @5C o the casal se>ence. (#M(n ! ;1


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(+ Compte the response o the system y(n ! .,y(n-1-.12y(n-2A"(n-1A"(n-2 toinpt "(n ! n(n.4s the system is sta+le (0

*. ind the inverse 8-transorm o "(8 ! (82A8 B (8-1(8-3< @5C/ 8 N 3. ?sing(i artialraction method< (ii @eside method and (iii Convoltion method. (1*,. (a Determine the nit step response o the system whose di%erencee>ation isy(n-.,y(n-1A.12y(n-2 ! "(n-1A"(n-2 i y(-1 ! y(-2 ! 1. (0(+ ind the inpt "(n o the system< i the implse response h(n and theotpt y(n

as shown +elow. (0h(n ! ;1


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12. (a Calclate the re>ency response or the )4 systems representationi h(n ! R1Bnn (n ii h(n ! O(n E O(n-1 (0(+ ind the re>ency response o the system having implse response

h(n ! R1B2 ; (1B2n A (-1B#n = (n (013. Determine the re>ency response (J(eK or the system and plotmagnitderesponse and phase response. y(nAR1B#y(n-1 ! "(n-"(n-1 (1*1#. (a T discrete E time system has a nit sample response h(n given +yh(n ! R1B2 O(n A O(n-1 A R1B2 O(n-2. ind the system re>ency responseJ(eKPlot magnitde and hase response. (12(+ 9"plain any two properties o Discrete orier Series. (#

UNIT III

DISCRETE FOURIER TRANSFORM AND COMPUTATION

PART A (2 MARKS)1. $hy ) is needed&2. $hat is the main advantage o )&3. $hat is )< $hat is meant +y @adi"-2 )&'. $hat is decimation-in-time algorithm&*. $hat is decimation in re>ency algorithm&,. $hat are the di%erences and similarities +etween D4 and D4) algorithm&

0. $hat is the +asic operation o D4) algorithm&. $hat is the +asic operation o D4 algorithm&1. $hat are the applications o ) algorithms&11. Draw the Gow graph o a two point D) or a decimation-in-timedecomposition.12. Draw the Gow graph o a two point radi"-2 D4 ).13. Draw the +asic +tterGy diagram or D4) algorithm.1#. Draw the +asic +tterGy diagram or D4 algorithm.

PART B1. Descri+e the decimation in time RD4) radi"-2 ) algorithm to determineH-pointD). (1*2. Tn 0-point discrete time se>ence is given +y "(n ! ;2


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3. (a Compte the #-point D) and )-D4) or the se>ence "(n !;1


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2. $rite the procedre or designing 4@ flters3. $rite the characteristics o 4@ flter.#. $hat are the design techni>es availa+le or the designing 4@ flter&'. $hat are the demerits o 4@ flter&*. $hat are the possi+le types o implse response or linear phase 4@

flters&,. $hat is :4FFS phenomenon&0. $rite the desira+le characteristics o re>ency response o windownctions.. $rite the characteristics eatres o rectanglar window.1. ist merits and demerits o rectanglar window.11. ist the eatres o Vaiser $indow.12. $hat do yo nderstand +y linear phase response&13. $hat are the two types o flter +ased on the implse response&1#. $hat are the advantages o Vaiser $indow&1'. $hat is the principle o designing 4@ flter sing re>ency sampling

method&1*. $hat are the properties o 4@ flter&1,. $hat is the need or employing window techni>e or 4@ flter design&(5r$hat is window and why it is necessary&10. $hat is the necessary and sLcient condition or linear phasecharacteristic in 4@flter&

1. Defne 44@ flter.2. $hat are the methods availa+le or designing analog 44@ flter&21. $hat are the methods availa+le or designing analog 44@ flter&22. 6ention the importance o 44@ flter/23. 6ention the two properties o Ftterworth low pass flter.2#. $rite the properties o che+yshev type-4 flter/2'. $hat is aliasing& $hy it is a+sent in +ilinear transormation &2*. Jow one can design digital flter rom analog flter &2,. $hat is +ilinear transormation&20. $hat is warping e%ect&2. $rite merits and demerits o +ilinear transormation.

3. $hat is the main advantage o direct-orm 44 reali8ation when comparedto directorm 4 reali8ation&31. $hat is the main disadvantage o direct-orm reali8ation&32. $hat is the advantage o cascade reali8ation&33. Distingish 44@ and [email protected]#. Compare analog and digital flter.3'. Compare Ftterworth and Che+yshev ilter/3*. Compare implse invariant and +ilinear techni>e


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3,. $hat are the di%erent types o strctres or reali8ation o 44@ systems&30. $rite a short note on prewarping.

PART B1. Descri+e the implse invariance and +ilinear transormation methods sed

ordesigning digital 44@ flters. (1*2. (a 5+tain the cascade and parallel reali8ation o the system descri+ed +yy(n ! -.1y(n-1A.2y(n-2A3"(nA3.*"(n-1A.*"(n-2 (1(+ Discss a+ot any three window nctions sed in the design o 4@flters. (*

3. Determine the direct orm 44 and parallel orm reali8ation or the ollowing

system.y(n ! -.1y(n-1A.,2y(n-2A.,"(n-.2'2"(n-2 (1*#. Tn analog flter has a transer nction J(s ! (1 B s2A,sA1. Design adigital fltere>ivalent to this implse invariant method. (1*'. or the given specifcations design an analog Ftterworth fltere design a lowpass flter with pass

+and gain onity< cto% re>ency o 1 J8 and working at a sampling re>ency o'kJI. )helength o the implse response shold +e ,. (1*12. Design an ideal Jil+ert transormer having re>ency responseJ(eK ! or - U K U ! - or U K U ?sing +lackman window or H!11.lot the re>ency response. (1*

UNIT VDIGITAL SIGNAL PROCESSOR

PART A (2 MARKS)

1. $hat are the classifcations o digital signal processors&2. $hat are the actors that inGence the selection o DSs&3. $hat are the applications o DSs. 6ention the di%erent addressing modes in )6S32C'#" processor.'. $hat is meant +y pipelining&*. :ive the digital signal processing application with the )6S 32 amily.,. $hat are the desira+le eatres o DS rocessors&

0. $hat are the di%erent types o DS Trchitectre&. State the eatres o )6S32'C'" series o DS processors.1. Defne arallel logic nit&11. Defne scaling shiter&12. Defne T@T? in )6S32C'M processor&13. $hat are the 4nterrpts availa+le in )6S32C'M processors&1#. $hat are the three >anti8ation errors de to fnite word length registersin digitalflters&

1'. $hat do yo nderstand +y inpt >anti8ation error&1*. $hat is co-eLcient >anti8ation error&1,. $hat is prodct >anti8ation error& (or $hat is prodct rond-o% error inDS&10. $hat are the di%erent methods o >anti8ation&1. Defne )rncation and @onding.


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2. $hat is the e%ect o >anti8ation on pole locations&21. $hich reali8ation is less sensitive to the process o >anti8ation&22. $hat is meant +y >anti8ation step si8e&23. $hat are the two kinds o limit cycle +ehavior in DS&2#. Defne XDead +andY o the flter.

2'. 9"plain +rieGy the need or scaling in the digital flter implementation.2*. $hy ronding is preerred to trncation in reali8ing digital flter&

PART B1. Descri+e in detail the architectral aspects o )6S32C'# digital signalprocessorsing an illstrative +lock diagram. (1*2. 9"plain the varios addressing modes and salient eatres o)6S32C'#M. (1*3. (a Descri+e the nction o on-chip peripherals o )6S32C'# processor.(12

(+ $hat are the di%erent +ses o )6S32C'# and their nctions& (##. Descri+e the errors introdced +y >anti8ation. 9"plain the impact o>anti8ationo flter coeLcients on the location o poles. (1*'. $rite a +rie note on/i 4npt >anti8ation (0ii imit cycles (0*. Discss in detail the varios >anti8ation e%ects in the design o digitalflters. (1*,. ind the e%ect o co-eLcient >anti8ation on pole locations o the givensecond

order 44@ system< when it is reali8ed in direct orm 4 and in cascade orm.Tssme aword length o # +its throgh trncation. (1*J(8 ! 1 B (1 E . 8-1 A .2 8-1

eee-dsp qb-unit1-unit5 (2m and 16m qstn only)

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