eee2243 digital system design chapter 3: elementary components by muhazam mustapha, february 2012
TRANSCRIPT
EEE2243Digital System Design
Chapter 3: Elementary Components
by Muhazam Mustapha, February 2012
Learning Outcome
• By the end of this chapter, students are expected to understand a few elementary components in digital system– Decoder– Multiplexer– Demultiplexer– T Flip-flop– JK Flip-flop
Chapter Content
• Decoder
• Multiplexer
• Demultiplxer
• T Flip-flop
• JK Flip-flop
Decoder
Decoder• A decoder is a combinational circuit that
activates its output according to the binary value of its input
• General block diagram of active high 3-bit decoder:
3-to-8 Decoder
I0
I1
I2
O0
O1
O2
O3
O4
O5
O6
O7
If I2I1I0 = 010, O2 will be set to HIGH, the rest will be LOW
Decoder• Most of the decoders available in the market are
inverted output (active low):
I0
I1
I2
O0
O1
O2
O3
O4
O5
O6
O7
If I2I1I0 = 010, O2 will be set to LOW, the rest will be HIGH
3-to-8 Decoder
Decoder• General truth table and circuit of 2-to-4 active
high decoder:
I1 I0 O0 O1 O2 O3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Decoder• General truth table and circuit of 2-to-4 active
high decoder:
I1 I0 O0 O1 O2 O3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
Decoder Verilog• From the definition of decoder it might be
obvious now that it easier to write its Verilog code in Boolean algebra rather than behavioral approach
• Active high decoder:
module Decoder2to4(codein, codeout); input [1:0] codein; output [3:0] codeout;
assign codeout[0] = ~codein[1] & ~codein[0]; assign codeout[1] = ~codein[1] & codein[0]; assign codeout[2] = codein[1] & ~codein[0]; assign codeout[3] = codein[1] & codein[0];endmodule
Decoder Verilog• Active low decoder:
module Decoder2to4(codein, codeout); input [1:0] codein; output [3:0] codeout;
assign codeout[0] = ~(~codein[1] & ~codein[0]); assign codeout[1] = ~(~codein[1] & codein[0]); assign codeout[2] = ~( codein[1] & ~codein[0]); assign codeout[3] = ~( codein[1] & codein[0]);endmodule
Multiplexer
Multiplexer• A multiplexer (mux) is a combinational circuit
that transfers its MULTI line inputs to a SINGLE line output according to the binary value of some selector lines
• General block diagram:
S0
I0
I1
I2
I3Output
I5
I6
I7
If S2S1S0 = 010, value at I2 will be sent to Output
8-to-1 Mux
I4
S1S2
Multiplexer• General truth table of 8-to-1 multiplexer:
S1 S0 Output
0 0 I0
0 1 I1
1 0 I2
1 1 I3
301201101001 ISSISSISSISSOutput
Multiplexer• Based on the previous truth table, multiplexer
can be built using decoder:S1 S0
I3
I2
I1
I0
Decoder
MultiplexerOutput
Multiplexer• The simplified circuit:
S1 S0
I3
I2
I1
I0
Output
Multiplexer Verilog• Multiplexer is better be defined in behavioral
approach
module Mux4to1(sel, lin, lout); input [3:0] lin; input [1:0] sel; output lout; reg lout;
always@(sel) begin case (sel) 0: lout = lin[0]; 1: lout = lin[1]; 2: lout = lin[2]; 3: lout = lin[3]; endcase endendmodule
Demultiplexer
Demultiplexer• A demultiplexer (demux) is a combinational
circuit that transfers its SINGLE line input to one of its MULTI line outputs according to the binary value of some selector lines
• General block diagram:
S0
O0
O1
O2
O3
Output
O5
O6
O7
If S2S1S0 = 010, value at Input goes O2
1-to-8 Demux
O4
S1S2
Input
Demultiplexer• Since a demux sends the input to only one
output, the rest (non-active outputs) will be all HIGH (active low) or all LOW (active high)
• In this sense demux behaves like a decoder• As a matter of fact we can build demux using
decoder with gates at the outputs
Demultiplexer• Active HIGH construct:
3-to-8 Decoder
S0
S1
S2
O0
O1
O2
O3
O4
O5
O6
O7
The corresponding Verilog is left as exercise or tutorial or quiz
Input
Demultiplexer• Active LOW construct:
3-to-8 Decoder
S0
S1
S2
O0
O1
O2
O3
O4
O5
O6
O7
The corresponding Verilog is left as exercise or tutorial or quiz
Input
T & JK Flip-flops
T Flip-flop• Toggles if T is high, otherwise stay
T Q
Q
T Q Q*
0 0 0
0 1 1
1 0 1
1 1 0
clk
Characteristic equation:
QT
QTQTQ*
T Flip-flop• Since in Verilog (any HDL) and FPGA design all
flip-flops are D, we need to add some surrounding circuit if we want T flip-flops:
D Q
Qclk
T
The corresponding Verilog is left as exercise or tutorial or quiz
JK Flip-Flop
J
K
Q
Q
J K Q Next Q (Q*)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
clk
Characteristic equation:
QKQJQ*
Stay
Reset
Set
Toggle
JK Flip-flop• Surrounding circuit for JK flip-flops:
D Q
QclkJ
K
The corresponding Verilog is left as exercise or tutorial or quiz