eeng 2710 chapter 4
DESCRIPTION
EENG 2710 Chapter 4. Modular Combinational Logic. Chapter 4 Homework. EENG 2710 Xilinx Project 1 And EENG 2710 VHDL Project 2 (Projects are on Instructor’s Website). Basic Decoder. Decoder: A digital circuit designed to detect the presence of a particular digital state. - PowerPoint PPT PresentationTRANSCRIPT
EENG 2710 Chapter 4
Modular Combinational Logic
1
Chapter 4 Homework
EENG 2710 Xilinx Project 1And
EENG 2710 VHDL Project 2(Projects are on Instructor’s Website)
2
3
Basic Decoder
• Decoder: A digital circuit designed to detect the presence of a particular digital state.
• Can have one output or multiple outputs.• Example: 2-Input NAND Gate detects the
presence of ‘11’ on the inputs to generate a ‘0’ output.
4
Single-Gate Decoders
• Uses single gates (AND/NAND) and some Inverters.
• Example: 4-Input AND detects ‘1111’ on the inputs to generate a ‘1’ output.
• Inputs are labeled D3, D2, D1, and D0, with D3 the MSB (most significant bit) and D0 the LSB (least significant bit).
5
Single-Gate Decoders
D3 D3
D0
D2 D2
D1 D1
D0 Y = (D3 D0)’D2 D1Y = D3 D0D2 D1
6
Single-Gate Examples
• If the inputs to a 4-Input NAND are given as , then the NAND detects the code
0001. The output is a 0 when the code 0001 is detected.
• This type of decoder is used in Address Decoding for a PC System Board.
4321 , DD, D, D
7
Multiple Output Decoders
• Decoder circuit with n inputs can activate m = 2n load circuits.
• Called a n-line-to-m-line decoder, such as a 2-to-4 or a 3-to-8 decoder.
• Usually has an active low enable that enables the decoder outputs.
G
8
2-to-4 Decoder
9
3-to-8 Decoder
10
Truth Table for a 3-to-8 Decoder
1 1 1 1 1 0 1 1 0 1 0 0
1 1 1 1 1 1 0 1 1 0 0 0
1 1 1 1 1 1 1 0 0 0 0 0
1 1 1 1 1 1 1 1 X X X 1
Y Y Y Y Y Y Y YD D D G 7 6543210012
11
74138 3-to-8 Decoder
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74138 3-to-8 Decoder
13
Simulation
• Simulation: The verification of a digital design using a timing diagram before programming the design in a Complex Programmable Logic Device (CPLD).
• Used to check the Output Response of a design to an Input Stimulus using a timing diagram.
14
Simulation
15
VHDL Binary Decoder
• Use select signal assignment statements constructs or conditional signal assignment statements constructs.
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2-to-4 Decoder VHDL Entity
• Using a select signal assignment statement:LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY decode3a ISPORT( d : IN STD_LOGIC_VECTOR (1 downto 0);
g : IN STD_LOGIC y : OUT STD_LOGIC_VECTOR (3 downto 0));END decode3;
17
Selected Signal Entity
• In the previous slide, the Entity used a STD LOGIC Array for Inputs and Outputs.
• The Y : OUT STD_LOGIC_VECTOR(3 downto 0) is equal to Y3, Y2, Y1, Y0.
• The STD_LOGIC Data Type is similar to BIT but has added state values such as Z, X, H, and L instead of just 0 and 1.
18
Selected Signal Assignments
• Uses a VHDL Architecture construct called WITH SELECT.
• Format is:– WITH (signal input(s)) SELECT.– Signal input states are used to define the output
state changes.
19
2-to-4 Decoder VHDL Architecture
ARCHITECTURE decoder OF decode2to4 ISSIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0);BEGIN
inputs(2) <= g;inputs (1 downto 0) <= d;WITH inputs SELECT
y <= "0001" WHEN "000","0010" WHEN "001","0100" WHEN "010","1000" WHEN "011","0000" WHEN others;
END decoder;
gd(1)
d(0)
Y(3) Y(0)
Default case
2-to-4 Decoder VHDL ArchitectureLIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY decode3a ISPORT( d : IN STD_LOGIC_VECTOR (1 downto 0);
g : IN STD_LOGIC y : OUT STD_LOGIC_VECTOR (3 downto 0));END decode3;
ARCHITECTURE decoder OF decode2to4 ISSIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0);BEGIN
inputs(2) <= g;inputs (1 downto 0) <= d;WITH inputs SELECT
y <= "0001" WHEN "000","0010" WHEN "001","0100" WHEN "010","1000" WHEN "011","0000" WHEN others;
END decoder; 20
21
Decoder Architecture
• The decoder Architecture used a SELECT to evaluate d to determine the Output y.
• Both d and y are defined as an Array (or bus or vector) Data Type.
• The last state for WHEN OTHERS is added for the other logic states (Z, X, H, L, etc.).
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Seven-Segment Displays
• Seven-Segment Display: An array of seven independently controlled LEDs shaped like an 8 that can be used to display decimal digits.
23
Seven-Segment Displays
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Seven-Segment Displays
25
Common Anode Display
• Common Anode Display (CA): A seven- segment display where the anodes of all the LEDs are connected together to VCC and a ‘0’ turns on a segment (a to g).
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Common Cathode Display
• Common Cathode Display (CC): A seven-segment display where all the cathodes are connected and tied to ground, and a ‘1’ turns on a segment.
27
Common Cathode/Anode Display
28
Common Anode Display
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Seven-Segment Decoder/Driver
• Receives a BCD (Binary Coded Decimal) 4-Bit input, outputs a BCD digit 0000 – 1001 (0 through 9).
• Generates Outputs (a–g) for each of the display LEDs.
• Requires a current limit series resistor for each segment.
30
Seven-Segment Decoder/Driver • Decoders for a CC-SS have active high outputs
while decoders for a CA-SS have active low outputs (a to g).
• The outputs generated for the binary input combinations of 1010 to 1111 are “don’t cares”.
• The decoder can be designed with VHDL Logic (7447, 7448).
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Digit D3 D2 D1 D0 a b c d e f g0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 1 1 0 0 1 1 1 12 0 0 1 0 0 0 1 0 0 1 03 0 0 1 1 0 0 0 0 1 1 04 0 1 0 0 1 0 0 1 1 0 05 0 1 0 1 0 1 0 0 1 0 06 0 1 1 0 1 1 0 0 0 0 07 0 1 1 1 0 0 0 1 1 1 18 1 0 0 0 0 0 0 0 0 0 09 1 0 0 1 0 0 0 1 1 0 0
SS Decoder/Driver Truth Table
32
Decoder/Driver Entity (CA)
ENTITY bcd_7seg IS PORT( d3, d2, d1, d0 : IN BIT; a, b, c, d, e, f, g : OUT BIT;END bcd_7seg;
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Decoder/Driver Architecture
ARCHITECTURE seven_segment OF bcd_7seg IS
SIGNAL input : BIT_VECTOR (3 downto 0);
SIGNAL output : BIT_VECTOR (6 downto 0);
BEGIN
input <= d3 & d2 & d1 & d0;
-- Uses two intermediate signals called input and output (internal no pins)
-- Creates an array by using the concatenate operator (&)
In this case input(3) <= d3, input(2) <= d2, etc.
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Decoder/Driver Architecture
WITH input SELECT
output <= “0000001” WHEN “0000”,
“1001111” WHEN “0001”,
“0010010” WHEN “0010”,
“0000110“ WHEN “0011”,
• • •
• • •
• • •
“1111111” WHEN others;
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Decoder/Driver Architecture
a <= output(6);
b <= output(5);
c <= output(4);
d <= output(3);
e <= output(2);
f <= output(1);
g <= output(0);
END seven_segment
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SS VHDL File Description
• In the preceding example file, a concurrent select signal assignment was used (WITH (signals) SELECT.
• The intermediate output signals were mapped to the segments (a to g).
• Example: when Input (D3 – D0) is 0001, the decoder sets a=d=e=f=g=1, b=c=0.
37
Encoders
• Encoder: A digital circuit that generates a specific code at its outputs in response to one or more active inputs.
• It is complementary in function to a decoder.• Output codes are usually Binary or BCD.
38
Priority Encoders
• Priority Encoder: An encoder that generates a code based on the highest- priority input.
• For example, if input D3 = input D5, then the output is 101, not 011. D5 has a higher priority than D3 and the output will respond accordingly.
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BCD Priority EncoderD9 – D0 = 0100001111
BCD # = ?
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BCD Priority EncoderD9 – D0 = 0101001011
Q3 – Q0 = 1000 (810)
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BCD Priority EncoderD9 – D0 = 1000000001
Q3 – Q0 = 1001 (910)
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BCD Priority EncoderD9 – D0 = 1101001011
Q3 – Q0 = 1001 (910)
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Put It All Together
A
DC
B
1
= 1= 0
= 0= 0
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Priority Encoder VHDL Entity
-- hi_pri8a.vhd
ENTITY hi_pri8a IS PORT( d : IN BIT_VECTOR (7 downto 0);
q : OUT BIT_VECTOR (2 downto 0));END hi_pri8a;
45
Priority Encoder VHDL Architecture
ARCHITECTURE a OF hi_pri8a ISBEGIN-- Concurrent Signal Assignments
q(2) <= d(7) or d(6) or d(5) or d(4); q(1) <= d(7) or d(6) or ((not d(5)) and (not d(4)) and d(3)) or ((not d(5)) and (not d(4)) and d(2));
q(0) <= -- in a similar fashionEND a;
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8 to 3 bit Encoder
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8-to-3 Encoder Truth Table
1 1 1 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 1 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
Q0 Q1 Q2 D0 D1 D2 D3 D4 D5 D6 D7
Inputs High Active
1
48
Basic Multiplexers (MUX)
• (MUX): A digital circuit that directs one of several inputs to a single output based on the state of several select inputs.
• A MUX is called a m-to-1 MUX. • A MUX with n select inputs will require m = 2n
data inputs (e.g., a 4-to-1 MUX requires 2 select inputs S1 and S0).
49
Basic Multiplexers (MUX)
50
Basic Multiplexers (MUX)
51
4-to-1 Multiplexers Truth Table
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
52
Multiplexer Logic
• Boolean expression for a 4-to-1 MUX is
• This expression can be expanded to any size
MUX so the VHDL architecture could use a very long concurrent Boolean statement.
013012011010 SS D S S D SS D S S DY
53
Double Subscript Notation
• Naming convention in which variables are bundled in numerically related groups, the elements of which are themselves numbered.
• The first subscript identifies the group that a variable belongs to (D01, D00).
• The second subscript indicates which element of the group a variable represents.
54
4-bit Bus MUX
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Truth Table for a 4-to-1 4-bit Bus MUX
S1 S0 Y3 Y2 Y1 Y0
0 0 D03 D02 D01 D00
0 1 D13 D12 D11 D10
1 0 D23 D22 D21 D20
1 1 D33 D32 D31 D30
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VHDL Constructs For MUXs
• The following three VHDL constructs can be used to describe the Multiplexer:– Concurrent Signal Assignment Statement– Select Signal Assignment Statement– CASE Statement
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PROCESS and Sensitivity List
• PROCESS: A VHDL construct that contains statements that are executed if a signal in its sensitivity list changes.
• Sensitivity list: A list of signals in a PROCESS statement that are monitored to determine whether the Process should be executed.
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Case Statement
• A case statement is a VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable.
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Case VHDL Template
CASE __expression ISWHEN __constant_value => __statement; __statement;WHEN __constant_value => __statement; __statement;WHEN OTHERS => __statement; __statement;
END CASE;
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MUX 4-to-1 VHDL – 1
• Basic Entity declaration for a 4-to-1 MUX: ENTITY mux4case IS
PORT(d0, d1, d2, d3 : IN BIT;
s : IN BIT_VECTOR (1 downto 0); y : OUT BIT); END mux4case;
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MUX 4-to-1 VHDL – 2
ARCHITECTURE mux4to1 OF mux4case ISBEGIN
-- Monitor select inputs and execute if they changePROCESS(s)BEGIN
CASE s IS
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MUX 4-to-1 VHDL – 3
WHEN "00" => y <= d0;WHEN "01" => y <= d1;WHEN "10" => y <= d2;WHEN "11" => y <= d3;WHEN others => y <= '0';
END CASE;END PROCESS;
END mux4to1;
63
Multiplexer Applications
• Used in directing multiple data sources to a single processing element such as multiple CD Player Streams to a DSP.
• Used in Time Division Multiplexing (TDM) by the Phone Service to multiplex multiple voice channels on a single coax line (or fiber).
64
Multiplexer ApplicationsUsed in directing multiple data sources to a single
processing element such as multiple CD Player Streams to a DSP.
65
Multiplexer ApplicationsUsed in Time Division Multiplexing (TDM) by the
Phone Service to multiplex multiple voice channels on a single coax line (or fiber).
66
Time Division Multiplexing (TDM)
• Each user has a specific time slot in a TDM data frame. Each frame has 24 users.
• TDM requires a time-dependent (counter) source to synchronize the select lines.
• Each user’s time slot repeats on the next frame for more data.
• The links are called T-Carriers (such as a T1 Line).
67
TDM Data Streams
• Two methods in which data is transmitted:– Bit Multiplexing: One bit is sent at a time from
the channel during the channel’s assigned time slot
– Word Multiplexing: One byte is sent at a time from the channel during the channel’s assigned time slot
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TDM Data Streams
69
TDM Data Streams
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Demultiplexer Basics
• Demultiplexer: A digital circuit that uses a decoder to direct a single input (from a MUX) to one of several outputs.
• A DEMUX performs the reverse operation of a MUX.
• The selected output is chosen by the Select Inputs (as in a MUX).
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Demultiplexer Basics
• Designated as a 1-to-n DEMUX that requires m select inputs such that n outputs = 2m select inputs.
• 1-to-4 DEMUX Equations:
• They are similar to a MUX and can be designed
using CASE Statements.
. S S D YS SDY
SS D YS S D Y
)()(
)()(
01030102
01010100
;
;;
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Demultiplexer Basics
73
Demultiplexer Basics
74
Demultiplexer Basics
75
Demultiplexer VHDL Entity
ENTITY dmux8 ISPORT(
s : IN STD_LOGIC_VECTOR (2 downto 0);d : IN STD_LOGIC;y : OUT STD_LOGIC_VECTOR (0 to 7));
END dmux8;
76
Demultiplexer VHDL Architecture
ARCHITECTURE a OF dmux8 IS SIGNAL inputs : STD_LOGIC_VECTOR (3 downto 0);BEGIN inputs <= d & s; WITH inputs select Y <= “01111111” WHEN “0000”, “10111111” WHEN “0001”,
• • • • • • “11111111” WHEN others;END a;
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Demultiplexer VHDL Architecture
78
Analog MUX/DEMUX
• Uses a CMOS Switch or Transmission Gate that will allow a signal to Pass in two directions for + and – Voltages.
• Some commercial types such as a CD4066 or 74HC4066.
• Multiplexes 4 CMOS Switches to a single output (Y) for analog multiplexing.
79
Analog MUX/DEMUX
80
Analog MUX/DEMUX
81
Magnitude Comparators
• Magnitude Comparator: A digital circuit that compares two n-Bit Binary Numbers and indicates if they are equal or which is greater.
• A very simple One-Bit Magnitude Comparator is the Two-Input XNOR Gate:– When both inputs are equal, the output is a 1; if
they are not, it is a 0.
82
2-Bit Comparator
A1
A0
B1
B0
AEQB
83
2-Bit Magnitude Comparator
A1
A0
B1
B0
AEQB
AGTB
ALTB
84
Magnitude Comparators
• Multiple Bit Comparisons
• Also adds A > B (AGTB) and A < B (ALTB) Outputs.• For A > B, start with the MSB:
– If An–1 > Bn–1, then AGTB = 1 • If not, then try the next most significant bit.
. ) B A) • ( B A (AEQB n-n-n-n- 2211
85
4-Bit Magnitude Comparator
AEQB
AGTB
ALTB
A3
A2
B3
B2
A1
A0
B1
B0
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VHDL 4-Bit Magnitude Comparator
ENTITY compare4 IS PORT( a, b : IN INTEGER RANGE 0 to
15; agtb, aeqb, altb : OUT STD_LOGIC);END compare4;
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VHDL 4-Bit Magnitude Comparator
ARCHITECTURE a OF compare4 IS SIGNAL compare :STD_LOGIC_VECTOR (2 downto 0);BEGIN PROCESS (a, b) BEGIN
IF a<b THEN compare <= “110”;
ELSIF a = b THEN compare <= “101”;
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VHDL 4-Bit Magnitude Comparator
ELSIF a > b THEN
compare <= “011”;
ELSE
compare <= “111”;
END IF;
agtb <= compare(2);
aeqb <= compare(1);
altb <= compare(0);
END PROCESS
END a;
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Temperature Comparator
90
Parity Basics
• Parity: A digital system that checks for errors in a n-Bit Binary Number or Code.
• Even Parity: A parity system that requires the binary number and the parity bit to have an even # of 1s.
• Odd Parity: A parity system that requires the binary number and the parity bit to have an Odd # of 1s.
91
Parity Basics
• Parity Bit: A bit appended on the end of a binary number or code to make the # of 1s odd or even depending on the type of parity in the system.
• Parity is used in transmitting and receiving data by devices in a PC called UARTs, that are on the COM Port.
• UART = Universal asynchronous Receiver/Transmitter
92
Parity Basics
93
Parity Calculation
• N1 = 0110110:– It has four 1s (an even number).– If Parity is ODD, the Parity Bit = 1 to make it an odd number (5).– If Parity is EVEN, the Parity Bit = 0 to keep it an even number
(4).
• N2 = 1000000:– One 1 in the data.– Podd = 0.– Peven = 1.
94
Parity Generation HW
• A basic two-bit parity generator can be constructed from a XOR Gate.
• When the two inputs are 01 or 10, the output is a 1 (so this is even parity).
• When the two inputs are 00 or 11, the output is a 0.• For a parity generator of n bits, add more gates.
95
Parity Generator HW
• Cascading a long chain of XOR gates could cause excessive propagation delays.
• To check for a Parity error, the receiver (RX) just generates a new Parity Bit (P1) based on the received parallel data and then compares it to the parity bit transmitted (P2).
96
Parity Generator HW
• If there is an error, the two bits (P1 and P2) will not be equal, and we can use a two-bit magnitude comparator to check this (an XOR gate).
• This check is called syndrome.– If there are no errors, the syndrome output (Perr) is 0.
• Parity is not a foolproof system.– If two bits are in error, the error is not detected.
97
4-Bit Parity Generator
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VHDL GENERATE Statement
__generate_label:FOR __index_variable IN __range GENERATE
__statement; __statement;END GENERATE;
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4-Bit Parity VHDL Code
LIBRARY ieee;USE ieee.std_logic1164.ALL;
ENTITY parity4_gen IS PORT( d : IN STD_LOGIC_VECTOR (0 to 3); pe ; OUT STD_LOGIC);END parity4_gen;
100
4-Bit Parity VHDL Code
ARCHITECTURE parity OF parity4_gen IS SIGNAL p : STD_LOGIC_VECTOR (1 to 3);BEGIN p(1) <= d(0) xor d(1); parity_generate: FOR i IN 2 to 3 GENERATE p(i) <= p(i-1) xor d(i);END GENERATE; pe <= p(3);END parity;
101
Binary Adders
• Half Adder (HA): A circuit that will add two bits and produce a sum bit and a carry bit.
• Full Adder (FA): A circuit that will add a carry bit from another HA or FA and two operand bits to produce a sum bit and a carry bit.
102
Basic HA Addition• Binary Two-Bit Addition Rules:
0 + 0 = 000 + 1 = 011 + 1 = 10
103
HA Circuit• Basic Equations: S = A XOR B, C = A and B where
S = Sum and C = Carry.• Truth Table for HA Block:
104
Full Adder Basics
• Adds a CIN input to the HA block.
• Equations are modified as follows:
• A FA can be made from two HA blocks and an OR Gate.
IN
INOUT
) (
) (
CBA
A BCBAC
105
Full Adder Basics
106
Full Adder Basics
107
Full Adder Basics
108
Parallel Adders
• A circuit, consisting of n full adders, that will add n-bit binary numbers.
• The output consists of n sum bits and a carry bit.
• COUT of one full adder is connected to CIN of the next full adder.
109
4-Bit Parallel Adder
110
4-Bit Parallel Adder
111
Ripple Carry
• In the n-Bit Parallel Adder (FA Stages) the Carryout is generated by the last stage (FAN).
• This is called a Ripple Carry Adder because the final carryout (Last Stage) is based on a ripple through each stage by CIN at the LSB Stage.
112
Ripple Carry
• Each Stage will have a propagation delay on the CIN to COUT of one AND Gate and one OR Gate.
• A 4-Bit Ripple Carry Adder will then have a propagation delay on the final COUT of 4 2 = 8 Gates.
• A 32-Bit adder such as in an MPU in a PC could have a delay of 64 Gates.
113
Ripple Carry
114
Look-Ahead Carry
• Fast Carry or Look-Ahead Carry:– A combinational network that generates the final
COUT directly from the operand bits (A1 to An, B1 to Bn).
– It is independent of the operations of each FA Stage (as the ripple carry is).
115
Look Ahead Carry
• Fast Carry has a small propagation delay compared to the ripple carry.
• The fast carry delay is 3 Gates for a 4-Bit Adder compared to 8 for the Ripple Carry.
116
4-Bit Fast Carry Circuit
117
Subtractor (2’s Complement)
• The concept of Subtraction using 2’s Complement addition allows a Parallel FA to be used.
• The subtract operation involves adding the inverse of the subtrahend to the minuend and then adding a 1.
118
Subtractor (2’s Complement)
• • This operation can be done in a parallel n-Bit FA by
inverting (B1 to Bn) and connecting CIN at the LSB Stage to +5 V.
• The circuit can be modified to allow either the ADD or SUBTRACT operation to be performed.
1Difference BABA
119
Subtractor (2’s Complement)
120
Parallel Binary Adder/Subtractor
• XOR gates are used as programmable inverters to pass binary numbers (e.g., B1B2B3B4) to the parallel adder in true or complemented form.
•
form. true its in is 0, /SUBADD When
ed.complement is 1,/SUBADD When
B
B
121
Parallel Binary Adder/Subtractor
1
0
X
B
Y
X=1 X=0
B B BB’
122
Overflow
• If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overflow has occurred.
• Overflow is not possible if the sign bits of the operands are different from each other.
123
Overflow Examples• Adding two 8-bit negative numbers:
• Adding two 8-bit positive numbers:
)1overflow;bit(Sign000010000
00001000
H100
H8000001000H80
V
)1overflow;bit(Sign00001000
00010000
H80
H0111110111FH7
V
124
Overflow 8-bit Parallel Adder
sum) of bit Sign ( S SS
) of bit Sign ( B B S
) of bit Sign ( A AS
1234567
B1234567B
A1234567A
S S S S SS
BS B B B BB
AS A AA AA
125
Overflow Detector Truth TableSA SB S V
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
SSSSSSV BABA
126
Overflow Detector
127
BCD Adder
• A Parallel Adder whose output sum is in groups of 4 bits, each representing a BCD (8421) Digit.
• Basic design is a 4-Bit Binary Parallel Adder to generate a 4-Bit Sum of A + B.
• Sum is input to the four-bit input of a Binary-to-BCD Code Converter.
128
BCD Adder