eesm516/10 lect1 1 elec 516 vlsi system design and design automation spring 2010 lecture 1...
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EESM516/10 Lect11
ELEC 516 VLSI System Design and Design AutomationSpring 2010
Lecture 1 Introduction,VLSI Design Methodology, Review on CMOS Design
Read Assignment:
Rabaey: Chapter1, 8
Weste: Chapter 6
Note: some of the slides in this lecture are adapted from the slide setof “ Digital Integrated Circuits, A design perspective” by Rabaey et.al, Copyright 2002Some are from the presentation slides of Prof Rabaey and Borderson of UCB
EESM516/10 Lect12
What is a VLSI Circuit and Why VLSI?
Very Large Scale Integrated Circuit– Technique where many circuit components and the
wiring that connects them are manufactured simultaneously into a compact, reliable and inexpensive chip.
Why VLSI?– Integration improves the design:
• lower parasitics = higher speed;• lower power;• physically smaller.• Higher reliability due to on-chip interconnect• Significant cost reduction
– Integration reduces manufacturing cost-(almost) no manual assembly.
EESM516/10 Lect13
Moore’s Law
Gorden Moore – Founder of Intel In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor
technology will double its effectiveness every 18 months
Reasons for Moore’s Law - – Process improvement - scaling
– Better circuit and architectural technique
EESM516/10 Lect14
Moore’s Law Plot
161514131211109876543210
195
91
960
196
11
962
196
31
964
196
51
966
196
71
968
196
91
970
197
11
972
197
31
974
197
5
LO
G2 O
F T
HE
NU
MB
ER
OF
CO
MP
ON
EN
TS
PE
R I
NT
EG
RA
TE
D F
UN
CT
ION
Electronics, April 19, 1965.
EESM516/10 Lect15
Moore’s law in Microprocessors
EESM516/10 Lect16
Trends of VLSI Technology
Feature size shrinks continuously # of Transistors increases Supply voltage decreases Low threshold voltage Higher clock frequency Small nodal capacitance
EESM516/10 Lect17
Technology Directions: SIA Roadmap
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 56 30 20
Mtrans/cm2 7 14-26 47 130 400 600
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183
Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4
For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years)
http://www.itrs.net/ntrs/publntrs.nsf
EESM516/10 Lect18
Die Size Growth
40048008
80808085
8086286
386486 Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
EESM516/10 Lect19
Frequency
P6Pentium ® proc
486386
28680868085
8080
80084004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Fre
qu
ency
(M
hz)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
Courtesy, Intel
EESM516/10 Lect110
Power Dissipation
P6Pentium ® proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Po
wer
(W
atts
)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Courtesy, Intel
EESM516/10 Lect111
Power will be a major problem
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Po
wer
(W
atts
)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
Courtesy, Intel
EESM516/10 Lect112
Power density
400480088080
8085
8086
286386
486Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Po
wer
Den
sity
(W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
Courtesy, Intel
EESM516/10 Lect113
Challenges in Digital Design
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.
…and There’s a Lot of Them!
DSM 1/DSM
Year Tech. Complexity Frequency 3 Yr. Design Staff Size
Staff Costs
2002 0.13 130 M Tr. 1,400 MHz 800 $360 M
2004 0.09 250 M Tr. 2,500 MHz 1200 $500 M
2006 65nm 500 M Tr. 4,000 MHz 1500 $800 M
2008 43nm 1BTr. 4500 MHz 2000 $1000 M
EESM516/10 Lect114
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
200
3
198
1
198
3
198
5
198
7
198
9
199
1
199
3
199
5
199
7
199
9
200
1
200
5
200
7
200
9
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./ChipTr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Lo
gic
Tra
nsi
sto
r p
er C
hip
(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
ctiv
ity
(K)
Tra
ns.
/Sta
ff -
Mo
.
Source: Sematech
Complexity outpaces design productivity
Co
mp
lexi
ty
Courtesy, ITRS Roadmap
EESM516/10 Lect115
Why Scaling?
Technology shrinks by 0.7/generation With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
Cost of a function decreases by 2x But …
– How to design chips with more and more functions?
– Design engineering population does not double every two years…
Hence, a need for more efficient design methods– Exploit different levels of abstraction
EESM516/10 Lect116
Disciplines contributed to the current states of the art in VLSI Design
Solid-state physics Material Science Lithography and fabrication device modeling circuit design and layout architecture algorithms CAD tools
EESM516/10 Lect117
Digital CMOS VLSI Design
• Objectiveinput: specification (e.g. a Pentium microprocessor in Englishor Hardware Descriptive Language with performance,cost,power constraints)
output: VLSI implementationmask layout that is verifiedfor the functional and performancespecificationhardware/software
Design Process
EESM516/10 Lect118
The Design Process• Top-down vs Bottom-up
• May be part of larger product design.
• Major levels of abstraction:
– specification;
– architecture;
– logic design;
– circuit design;
– layout.
microprocessor
memory ALU controlcircuit pads
Adder LogicUnit
Shifter
Inverter NAND NOR
p-transistor n-transistor
TOP-DOWNBOTTOM-UP
EESM516/10 Lect119
Implementation Style Factors affecting decision on implementation style
– Performance in terms of speed or power consumption– Cost
• Nonrecurring cost - design cost• production cost - function of process, design area, and
process yield• Testing cost
– Production Volume– Time to Market
Examples– microprocessor - high performance, low cost, high volume,
high development cost with high-performance design is amortized over many parts=> custom design
– Space applications - low volume, performance is critical, cost is insignificant compared with other parts => custom design
– consumer products - integration density is more important than performance, time to market is important => automatic design => semi-custom design
EESM516/10 Lect120
Implementation Choices
Custom
Standard CellsCompiled Cells Macro Cells
Cell-based
Pre-diffused(Gate Arrays)
Pre-wired(FPGA's)
Array-based
Semicustom
Digital Circuit Implementation Approaches
Platform-based design - SOC
EESM516/10 Lect121
Custom Design
Manual design, hand layout, manually-tuning of the transistor sizing, topology and placement
Use of Layout editor, circuit level simulation performance and design density is primary importance Labor-intensive => high cost and a long time-to-market Justified under the following conditions
– Cost amortized over a large volume– custom block can be reused for other design, e.g.
library cell– Cost is not the prime design criterion
Example - critical parts of microprocessors, such as integer and floating point execution units
EESM516/10 Lect122
Cell-based Design Methodology Standard Cells - reusing a limited
library cells e.g. inverter, AND/NAND, flip-flops
Steps– Input using HDL or schematic
capture– Generate gate netlist– automatic placement of the cells in
row– automatic routing of the cells
Can be intermixed with other custom-designed module such as memory/ALU
Require careful design of the library cells
EESM516/10 Lect123
Standard Cell - Example
3-input NAND cell(from Mississippi State Library)characterized for fanout of 4 andfor three different technologies
EESM516/10 Lect124
A chip using standard cells approach
[Brodersen92]
EESM516/10 Lect125
FPGA (Field Programmable Gate Arrays)
Completely programmable even after a product is shipped or in the field
Two basic versions:– Fuse/Antifuse based – permanently program
interconnect and personalize logic
• Program once– SRAM based – customerize routing and logic
functions Consists of array of configurable logic blocks
(CLBs) and programmable router Become more popular for re-configurable
computing systems
EESM516/10 Lect126
A typical FPGA floorplan
EESM516/10 Lect127
Platform-based design
Complex system design Use of pre-defined intellectual property (IP) blocks
– E.g. RISC processor core, memory, I/O, standard peripheral,( USB2.0, UART, etc.)
A platform can be used to implement a design by using common structures such as busses and common high-level language (such as C) to program the processors.
Design tasks:
– Put the blocks together, design application-specific blocks, place and route to form an operational chip,
develop software on the platform is an important task
– Hardware/software co-design is needed
EESM516/10 Lect128
Comparison of different implementation style
Implementation method
NRE Unit Cost
Power consump-tion
Comp-lexity
Time to market
Perform-ance
Flexibility
p/DSP Low med high Low Low Low high
FPGA Low high med med Low med high
Gate Array
med Low Low med med med med
Cell-based
high Low Low high high high Low
Full custom
high Low Low high high Very high
Low
Platform-based
high Low Low high high high med
EESM516/10 Lect129
Moore’s Law Impact
More transistors System-on-chip (SoC) design
– Embedded System Multiple-chips in the same package
– Multi-chip Module (MCM)– System-in-Package (SiP)
Multiple-core in the same chip– Network-on-chip (NoC)
Expand in the third dimension– 3-D chip
SiP
Mesh-based Network on chp
3-D chip
MCM
EESM516/10 Lect130
Design methodology
More details on the design style and design methodology will be discussed in the later lecture.
EESM516/10 Lect131
Design Phases• The four phases of creating a VLSI chip
EESM516/10 Lect132
Challenges in VLSI design
Multiple levels of abstraction: transistors to CPUs. Multiple and conflicting constraints: low cost and high
performance are often at odds. Short design time: Late products are often irrelevant. Dealing with high complexity (billion transistors in 2010)
– Divide-and-conquer: limit the number of components you deal with at any one time.
– Group several components into larger components, I.e.Hierarchical design:
• transistors form gates;• gates form functional units;• functional units form processing elements;• etc.
– Use of abstraction
EESM516/10 Lect133
Hierarchical name
Interior view of a component:– components and wires that make it up.
Exterior view of a component = type:– body;
– pinsFull
addera
bcin
sum
cout
EESM516/10 Lect134
Instantiating component types
Each instance has its own name:– add1 (type full adder)
– add2 (type full adder). Each instance is a separate copy of the type:
Add1(Fulladder)
a
bcin
sum
cout
Add2(Fulladder)
a
bcin
sumAdd1.a Add2.a
EESM516/10 Lect135
Abstraction
Levels of abstraction– Specification: function, cost, etc.– Architecture: large blocks.– Logic: gates + registers.– Circuits: transistor sizes for speed, power.– Layout: determines parasitics.
EESM516/10 Lect136
Layout and its abstractions
Layout for dynamic latch:
Abstraction: stick diagram
EESM516/10 Lect137
Circuit abstraction
Continuous voltages and time:
Digital abstraction: Discrete levels, discrete time:
EESM516/10 Lect138
Register-transfer abstraction
Abstract components, abstract data types:
+
+
0010
0001
0100
0011
EESM516/10 Lect139
Design abstractions
specification
behavior
register-transfer
logic
circuit
layout
English
Executableprogram
Sequentialmachines
Logic gates
transistors
rectangles
Throughput,design time
Function units,clock cycles
Literals, logic depth
nanoseconds
microns
function cost
EESM516/10 Lect140
Three major tasks in the design stage
conceptualization and modeling convey design information
– modeling used HDL– graphical models - flow diagram, schematic and geometric
layout– hierarchical and abstraction
synthesis and optimization– refining the model, from an abstract one to a detailed one
(layout) through a stepwise refinement process.– As synthesis proceeds in refining the model,more
information is need regarding the technology and the desire design style.
– optimization is carried out during the synthesis by selecting some design choices in a given model with the goal of raising some figure of merit of the design (such as area, performance and power consumption)
EESM516/10 Lect141
validation– acquiring a reasonable certainty level that a
circuit will function correctly, assuming there is no manufacturing fault
– remove design error before fabrication– performed by simulation tools and verification
tools– functional validation as well as timing validation– different level of simulation (behavior, logic and
circuit level)– simulation is costly for large circuits as the
number of input pattern is huge.– use of formal verification tools to verify the
circuits by comparing two circuit models and to detect the consistency.
EESM516/10 Lect142
Computer-Aided Design (Synthesis, Optimization)
In the design process, much of the work of transforming a design from one form to another is tedious and repetitive. These activities can be done computers which is referred to as Design Automation. Computer-Aided tools speed up the design cycle and reduce the human effort. Optimization techniques enhance the design quality
Synthesis - Synthesis subtasks are divided according to the different modeling levels:– architectural-level synthesis:
• generating a structural view of an architectural-level model.
• corresponds to determining an assignment of the circuit functions to operators
EESM516/10 Lect143
Different types of synthesis
EESM516/10 Lect144
– logic-level synthesis:• generating a structural view of a logic-level
model • logic synthesis is the manipulation of logic• specifications to create logic models and
interconnection of logic primitives.– geometrical-level synthesis: physical design
• generating the floorplan and layout of the chip• major tasks - placement and routing, • cell generation, hand-design of macro-blocks
Optimization - Circuit Optimization is often performed in conjunction with synthesis and is used to maximize the circuit quality to yield competitive circuits.
Parameters to optimize:– performance, area, power, testability– constrained optimization
EESM516/10 Lect145
Computer-Aided Design (Modeling,Analysis and simulation)
Modeling– High-level modeling using HDL– Logic level modeling using abstract data type
• Modeling timing– Low level modeling
• Modeling devices, parasitic cap. and resistance Analysis
– Functional analysis• Formal verification• LVS
– Timing analysis – static, dynamic Simulation
– Functional simulation – HDL simulation, logic simulation– Timing simulation – HSPICE, Spectra
EESM516/10 Lect146
Overall VLSI Design FlowSystem Spec.
Functional Spec.
Functional Verification
Logic Design
Logic Verification
Circuit Design
Circuit Verification
Physical Design
Layout Verification
BehavioralRepresentation
Logic (gate level)Representation
Circuit (transistor)Representation
LayoutRepresentation
BehavioralDomain
StructuralDomain
PhysicalDomain
Fab. and test
EESM516/10 Lect147
Design Quality and Metric
Achieve specification:– Functional– Timing (delay, operating frequency)
Die size – cost Power consumption
– Operating power– Standby power– Energy to perform a function
Testability– Generation of good test vectors– Availability of reliable test fixture at speed– Design of testable chip
EESM516/10 Lect148
Design Quality and Metric (cont.)
Yield and Manufacturability– Functional yield
– Parametric yield Reliability
– Premature aging
– ESD protection
– Latchup
– On-chip noise and crosstalk
– Power and ground bouncing Technology updatable and scalability
– Easily updated to new design rules
EESM516/10 Lect149
Design Space and Design Trade-off Optimization can be viewed as
finding an optimal design from a set of different feasible structural implementation of a circuit which is called the design space.Each dimension of the space is the design parameter
The design process is hence to generate designs from the design space (traverse the design space) and evaluate the design according to the objectives of interest until the objectives are reached. Usually the design has to trade-off one factor for another
EESM516/10 Lect150
Design Trade-off and constrained optimization
Constrained optimization problem instead:– minimize the circuit
area under delay constraints
– minimize the circuit delay under area constraints or
– minimize the circuit area under latency constraints
– minimize the circuit latency under area constraints
EESM516/10 Lect151
ASIC design flow (RTL synthesis)
EESM516/10 Lect152
An example of Automated ASIC flow
High-level Design
Identify files and paths [Insecta]
Resolve design hierarchy [Insecta]
Check hierarchy consistency
[Insecta]
Identify bad VHDL structures [Insecta]
Correct bad VHDL structures [Insecta]
Generate synthesis scripts [Insecta]
Virtual component generation [MC]
Generate backend scripts [Insecta]
Run physical synthesis [DC/PSYN]
Run signal integrity [First Encounter]
Run floorplanning [First Encounter]
Re-run physical synthesis [DC/PSYN]
Run route [NanoRoute]
Run extraction & checks [Calibre]
GDSII
Backannotate netlist [DC]
Run (first)logic synthesis
[DC]
PC Software1. Matlb R13 (6.5)2. Xilinx ISE3. Xilinx System
Generator 2.24. BEE ISE5. Xilinx ChipScope6. Xilinx Parallel Cable
UNIX SW Versions1. TCL/TK 8.32. Synopsys 2002.053. Cadence SoC
Encounter 2.2(Nanoroute)
4. Modelsim 5.6
Post process DFII [icfb]
View hierarchy [Insecta]
Optional design steps
View logic schematic [DA]
View floorplan [First Encounter]
Gate-level simulation [Modelsim]
View routed design
[NanoRoute] View log files
[Insecta]
View GDSII [pipo]
Generate GDSII [pipo]
EESM516/10 Lect153
NRE Cost is Increasing
EESM516/10 Lect154
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
EESM516/10 Lect155
Cost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢-per-¢-per-transistortransistor
Fabrication capital cost per transistor (Moore’s law)
EESM516/10 Lect156
Yield
%100per wafer chips ofnumber Total
per wafer chips good of No.Y
yield Dieper wafer Dies
costWafer cost Die
area die2
diameterwafer
area die
diameter/2wafer per wafer Dies
2
EESM516/10 Lect157
Defects
area dieareaunit per defects
1yield die
is approximately 3
4area) (die cost die f
EESM516/10 Lect158
Design in the late Silicon Era
System-on-a-chip design paradigm– More silicon available– Cheaper cost if more components on a system can be
integrated onto a chip– Time to market
• IP- resue• Software/Hardware co-design
– Sophisticated applications need more processors/processing element to put on the chip
– New design methodology – What is SOC?
• A chip designed for “complete” system functionality that incorporates a heterogeneous mix of processing and computation architectures
EESM516/10 Lect159
System-on-a-chip Design
Embedded applications where cost, performance, and energy are the real issues
DSP and control intensive, mixed-mode
– E.g. Sigmatel STMP35xx
Mixed-mode Combines programmable
and application-specific modules
Software plays crucial parts
Hardware accelerator
200k Gates FPGA+
512M DRAM
ADC/DAC+ other analog
2GFLOP4way superscaler
64bit DSP
32-bit RISCCore with
2GbitDRAM
EESM516/10 Lect160
Example of a typical SOC Design- A Wireless System
Analog Baseband
and RF Circuits
AD FSM
phone
bookRTOS
ARQ
MAC
Control
Coders
FFT Filters
Hardwired Algorithms
(word level)
analog digital
Logic (bit level)
Communication
AlgorithmsProtocols
HardwiredLogic
Analog
DSP Core P CoreA wide mix of components – how do we optimize this???
EESM516/10 Lect161
A Commercial Example
EESM516/10 Lect162
The Changing Metrics
Power/Energy have become dominant drivers for SOC design– Limiting factor performance and reliability in wall-
plugged applications
– Enabler for wide-spread use of distributed computing and data access
Energy reduction requires joint optimization process between applications and implementation
Cost of fabrication facilities and mask making has increased significantly– NRE cost of new design has increased significantly
EESM516/10 Lect163
The Changing Metrics
Physical effects (parasitics, reliability issues, power management) are increasingly significant in the design process– These must now be considered explicitly at the
circuit level Design complexity, and “context complexity are
sufficiently high that design verification is a major limitation on time-to-market
Towards fewer, but more flexible, reliable and reusable silicon platforms
Tradeoff between power, cost and flexbilibity
EESM516/10 Lect164
Design Platform for SOC
Application
Algorithm
Software Implementation
Compilation
Architecture
Microarchitecture
Component AssemblyAnd Synthesis
Final DesignEstimation andEvaluation
HW/SWPartitioning
EESM516/10 Lect165
Fast Design Space Exploration
Architect Designer
ArchitectureChoices
ArchitectureParameters
ParameterizedArchitecture
Model
Application(Generic C code)
RetargetableEstimator
Output: Estimate, Profile
Profile
EESM516/10 Lect166
SOC Design
Specification to architecture to implementation Behavior to structure
– System level: System specification to system architecture– RT/IS level: component behavior to component
microarchitecture
memory P1 P2
CustomHW memory
interface
interface interface
interface
chip
Specification+ constraints
System architecture+ estimates
RTL/IS implementation+ results
ProcessorsIPs
MemoryBuses
RegistersALU/FUsMemory
Gates
EESM516/10 Lect167
Reviews of CMOS Design CMOS Logic
– Using of pmos and nmos transistor to implement digital gates – Performance of a CMOS gate, inverter model analysis– Effect of transistor sizing, load capacitance, fanin and fanout
on the performance/delay of a CMOS gate CMOS circuit design style
– static CMOS circuit– dynamic CMOS circuit– pseudo CMOS circuit
Actual Design a CMOS digital circuit– Layout using layout tools (e.g. Cadence)– Circuit verification, layout vs. schematic– Timing verification, circuit level simulation
EESM516/10 Lect168
Review on CMOS Technology
Fully restored logic, output settled at Vdd or Vss
Similar Rise and Fall Transition Time Effective use of transmission gates No static power consumption => low power
consumption Precharging characteristics, both n and p
transistors can be used for precharging Layout density, need 2 n transistors for static
CMOS, n+1 for pseudo-NMOS, and n+2 for dynamic CMOS
encourages regular and easily automated layout styles
EESM516/10 Lect169
Review on CMOS Logic Gatesoutputinput
GND
VDD
outputinput
input output 0
110
outputAB
0
1
0 1
1 1
1 0
A
B
GND
VDD
output
AB
outputAB
0
1
0 1
1 0
0 0
A
B
GND
VDD
output
AB
EESM516/10 Lect170
Review on Dynamic CMOS Design Advantages of pseudo-NMOS :
– N+1 transistors instead of 2N for fan-in N.
– Disadvantage: static power consumption.
DYNAMIC LOGIC:– obtain similar result while
avoiding the static power consumption.
It uses a sequence of precharge and conditional evaluation phases, to realize complex logic functions
Mp
Me
VDD
PDN
In1In2
In3
OutMe
Mp
VDD
PUN
In1In2
In3
Out
CL
CL
p networkn network
2 phase operation:• Evaluation
• Precharge
EESM516/10 Lect171
Example of Dynamic Logic Gate
Mp
Me
VDD
Out
A
B
C
?N + 2 Transistors
?Ratioless
?No Static Power Consumption
?Noise Margins small (NML)
?Requires Clock
EESM516/10 Lect172
Review of CMOS gate performance
Factors affecting the delay– Width of the driving transistor– Fan-in of the gate– Load - Fanout,Gate capacitance and
wire capacitance
L
W
t
V
Ckt
V
Ckt
ox
ddp
Lpr
ddn
Lnf
2fr
avg
ttt
Factors affecting the delay– Width of the driving
transistor– Fan-in of the gate– Load - Fanout,Gate
capacitance and wire capacitance
EESM516/10 Lect173
A First-Order RC Network
vout
vin C
R
tp = ln (2) = 0.69 RC
Important model – matches delay of inverter
EESM516/10 Lect174
A First-Order RC NetworkVdd
Vout
isupply
CL
E0->1 = CLVdd2
PMOS
NETWORK
NMOS
A1
AN
NETWORK
E0 1 P t dt
0
T Vdd isupply t dt
0
T Vdd CLdVout
0
Vdd
CL Vdd 2= = = =
Ecap Pcap t dt
0
T Vouticap t dt
0
T CLVoutdVout
0
Vdd 1
2---C
LVdd
2= = = =
vout
vin CL
R
EESM516/10 Lect175
Measurement of Delay and Power
Delay Definition
tpHL
tpLH
t
t
Vin
Vout
50%
50%
tr
10%
90%
tf
Power Dissipation
dttIT
Vdttp
TP
tpVIP
T
ply
Tply
av
plypeakpeak
)()(1
))(max(
0sup
0
sup
sup
Power-Delay Product
avp PtPDP = Energy dissipated per operation
Energy-Delay Product (EDP) =
quality metric of gate = E tp
EESM516/10 Lect176
Reliability―Noise in Digital Integrated Circuits
i(t)
Inductive coupling Capacitive coupling Power and ground noise
v(t) VDD
EESM516/10 Lect177
DC OperationVoltage Transfer Characteristic
V(x)
V(y)
VOH
VOL
VM
VOH
VOL
fV(y)=V(x)
Switching Threshold
Nominal Voltage Levels
VOH = f(VOL)VOL = f(VOH)VM = f(VM)
EESM516/10 Lect178
Mapping between analog and digital signals
VIL
VIH
Vin
Slope = -1
Slope = -1
VOL
VOH
Vout
“ 0” VOL
VIL
VIH
VOH
UndefinedRegion
“ 1”
EESM516/10 Lect179
Definition of Noise Margins
Noise margin high
Noise margin low
VIH
VIL
UndefinedRegion
"1"
"0"
VOH
VOL
NMH
NML
Gate Output Gate Input
EESM516/10 Lect180
Noise Budget
Allocates gross noise margin to expected sources of noise
Sources: supply noise, cross talk, interference, offset
Differentiate between fixed and proportional noise sources
EESM516/10 Lect181
Key Reliability Properties
Absolute noise margin values are deceptive
– a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)
Noise immunity is the more important metric – the capability to suppress noise sources
Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;
EESM516/10 Lect182
Fan-in and Fan-out
N
Fan-out N Fan-in M
M
EESM516/10 Lect183
The Ideal Gate
Ri = Ro = 0Fanout = NMH = NML = VDD/2 g =
V in
V out
EESM516/10 Lect184
An Old-time Inverter
NMH
Vin (V)
Vout(V)
NM L
VM
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0
EESM516/10 Lect185
Ring Oscillator
T = 2 tp N