Efficient Designs of Reversible Majority Voters

Davar Kheirandish1& Majid Haghparast2 & Midia Reshadi1 & Mehdi Hosseinzadeh3,4

Received: 21 April 2020 /Accepted: 16 November 2020# Springer Science+Business Media, LLC, part of Springer Nature 2020

AbstractReversible Logic is one of the emerging technologies that has the capability of replacing traditional irreversible systems. Thepower consumption is low by the elimination of power dissipation caused by information loss in quantum computing. It ispredicted that a high failure rate for future technologies increases demand for fault-tolerant in reversible logic. Safety and criticalcircuits employ redundancy in their designs to overcome any faults of the circuit during the normal operation. One of the mostcommon forms to design fault-tolerant systems is to incorporate hardware redundancy to form N-Modular Redundancy (NMR),where N replicas of a module are connected to majority voters. In this paper, techniques for fault-masking have been proposed toprevent error propagation for reversible circuits by different implementations of the 3 and 5 input reversible majority voters. Boththese voters are able to provide fault location information by using the techniques of insertion directly and independent and bytaking advantage of available garbage outputs. The proposed reversible majority voters are efficient to deal with the single pointof failure. Moreover, a novel design for 5-input reversible majority voter (MV5) is also presented. The structure of the proposed5-input reversible majority voter is very simple and easy to implement in the reversible circuit. Evaluation results show that theproposed reversible MV5 can reduce the quantum cost up to 44% in the literature.

Keywords Reversible logic . Fault-tolerant . N-modular redundancy . Reversible majority voter

1 Introduction

Power dissipation and therewith heat generation is a seriousproblem for today’s computer chips. In [19], Landauer statedthat logic computation that is non-reversible essentially dissi-pates kTln2 of heat energy when a bit of information is lost,where again k is Boltzmann’s constant and T is the operatingtemperature in Kelvin. Bennett [6] showed that energy dissi-pation is impossible only if a design includes reversible gates.A solution is to develop new computational paradigms based

on quantum technologies. The reversible logic technique is aprimary part of the property of quantum computations [12,20].

High failure rates are expected to be one of the most im-portant challenges of any future technology. Therefore, faultdetection and correction and masking should be considered inthe design of reversible circuits [23]. The concept of faulttolerance is very important in the development process of asystem. Fault tolerance is a property that enables the system tocorrectly perform operations even in the presence of faults.Fault tolerance is achieved through redundancy. Safety-critical applications such as electricity transmission and distri-bution facilities, industrial control and automation, bankingand financial systems, and other sensitive industry applica-tions usually incorporate redundancy in their physical designsto obtain a specific degree of fault tolerance [8]. A commonapproach to fault tolerance is hardware redundancy by repli-cating one or more physical components of the system. In thiscontext, the n-modular redundancy (NMR) has been widelyused as one of the most common forms of hardware redun-dancy to design fault-tolerant systems. NMRmadeN identicalfunction modules and maximum faults of (N - 1)/2 functionmodules are tolerated. In other words, the NMR employs Nidentical function modules and requires the correct operation

Responsible Editor: V. D. Agrawal

* Majid Haghparasthaghparast@srbiau.ac.ir; mhaghparast@gmail.com

1 Department of Computer Engineering, Science and ResearchBranch, Islamic Azad University, Tehran, Iran

2 Department of Computer Engineering, Yadegar-e-Imam Khomeini(RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

3 Institute of Research and Development, Duy Tan University, DaNang 550000, Vietnam

4 Computer Science, University of Human Development,Sulaymaniyah, Iraq

https://doi.org/10.1007/s10836-020-05912-2

/ Published online: 4 December 2020

Journal of Electronic Testing (2020) 36:757–770

of at least (N + 1)/2 function units. Therefore, if (N-1)/2 of themodules are faulty modules, the majority voter will still gen-erate the correct output [8]. The 3MR, which is well-known asTMR, uses 3 identical function units and requires the correctoperation of at least 2 function units.

In this paper, the fault-masking techniques are used forreversible circuits and provide several 3 and 5 input reversiblemajority voters with different fault-masking capabilities.These reversible majority voters have fault diagnosis capabil-ities. Non-functional outputs of these reversible majorityvoters (garbage outputs) are used in providing informationfor fault diagnosis. Besides fault-masking for reliability, on-line repairs and reduced test complexity are other features ofthe proposed designs. A major advantage of these reversiblemajority voters is their robustness against a single point offailure. In the implementation, each copy of the voted valueis produced independently and directly from the inputs.Instead of using majority voter expansion, the proposed de-signs can be used.

The paper is structured as follows. In the next section, thebasic background is presented followed by Section 3 describ-ing the related works and explaining existing reversible ma-jority voters. The proposed approaches of reversible majorityvoters and the diagnosis schemes are discussed in Section 4.The results are shown in Section 5 and conclusions are pre-sented in Section 6.

2 Background

This section introduces the basic definitions related to quan-tum and reversible circuits and cost metrics that are used andrelevant to this research work. In this section, an attempt ismade to provide the required basic concepts to keep this paperself-contained.

2.1 Reversible Circuits

A reversible circuit can be generated with a cascade of revers-ible gates without fan-out branches and feedbacks. The twomost widely used categories of reversible logic gates are theNCT gate family and SF gate family [10, 28, 32]. The NCTgate family consists of NOT, CNOT, and Toffoli gates. Two

important reversible logic gates in the SF gate family areSWAP and Fredkin gates [24, 25]. Reversible gates in theNCT gate family are shown in Fig. 1. Figure 1(a) shows thesymbol of a NOT gate which performs inversion of input.Figure 1(b) shows a Controlled-NOT (CNOT). The input I2is the target input and the gate inverts the value of the targetinput if the control input is 1. Otherwise, its value remainsunchanged to the target output. Figure 1(c) shows the symbolof a 3 × 3 Toffoli gate. The input I3 is the target input and isconnected target output that its value is obtained by I3 =I1I2⊕ I3. A Toffoli gate with multiple controls is shown inFig. 1(d). A Toffoli gate with multiple controls inverts thetarget input if the values of all negative control inputs are 0,and the values of all positive control inputs are 1. Otherwise,its value remains unchanged to the target output [14, 17, 18,24]. Reversible gates in the SF gate family are shown in Fig. 2.Figure 2(a) shows the symbol of a SWAP gate which ex-changes the inputs. Figure 2(b) shows a 3 × 3 positive con-trolled Fredkin gate. The inputs I2 and I3 are the target inputs.The target inputs are swapped at the target outputs if the valueof control input (I1) is 1. Otherwise, their value remains un-changed to the target outputs. Figure 2(c) also shows the sym-bol of a 3 × 3 negative controlled Fredkin gate. The targetinputs (I2 and I3) are swapped at the target outputs if the valueof control input (I1) is 0. Otherwise, their value remains un-changed to the target outputs. The n × n multiple controlledFredkin gate is shown in Fig. 2(d). An n × n multiple con-trolled Fredkin gate swaps the target inputs (In-1 and In) atthe target outputs if the values of all negative control inputsare 0, and the values of all positive control inputs are 1.Otherwise, their values are passed unchanged to the targetoutputs [14, 17, 18, 24].

2.2 Quantum Circuits

The quantum circuit is constructed using quantum gates. AClifford+T circuit is a quantum circuit composed of gatesfrom the Clifford+T library. For quantum computation, differ-ent gates libraries exist, such as the Clifford+T library. TheClifford+T library consists of the gates NOT, CNOT, H(Hadamard), S, S†, T, and T†. Figure 3 shows the gates ofClifford+T libraries [9, 21].

Fig. 1 Reversible gates in NCT gates family. (a) NOT gate, (b) CNOT or Feynman gate, (c) 3 × 3 Toffoli gate, and (d) n × n Toffoli gate with multipleand negative control

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A real quantum computing platform is quantum computersavailable from IBM’s QX project, implement circuits withClifford+T gates. Available quantum computers in IBM’s Qproject works with the quantum gates from the Clifford+Tlibrary which consists of NOT, CNOT, H, S, S†, T, and T†

gates. Therefore, in order to implement well-known circuits insuch architectures, they need to be mapped to Clifford+Tgates.

2.3 Cost Metrics

There are five metrics to evaluate and compare different re-versible designs. These metrics are quantum cost, ancilla in-puts, garbage outputs, logical depth, and delay [4, 13].Definitions and a brief review of these metrics in the literatureare as follows:

2.3.1 Quantum Cost

The quantum cost is the most popular metric to compare dif-ferent reversible logic circuits. The quantum cost of a revers-ible circuit is the total number of quantum primitive gates,which are used to form an equivalent quantum circuit [11,21, 22, 24, 27].

The quantum cost of 1 × 1 and 2 × 2 reversible logic gatesare considered to be a unit cost. A 3 × 3 Toffoli gate and a 3 ×3 positive-controlled Fredkin gate can be implemented using 5quantum primitive gates. So the quantum cost for both is 5.The generalized Toffoli gate is implemented by 2n − 3 of 2 × 2quantum gates. The quantum cost of these implementations is

equal to 2n − 3 of 2 × 2 quantum gates [22]. The quantum costof NCT gates family and SF gates family in reversible logicgates is shown in Table 1.

2.3.2 Ancilla Input

AnAncilla Input (AI) or constant input is required to retain thefeature of a one-to-onemapping between vectors of inputs andoutputs in the reversible circuit [2, 3, 29, 30]. Adding constantinputs is a basic technique to convert an irreversible functioninto a reversible circuit. Additional constant inputs to the cir-cuit increase the cost and may reduce the quantum cost.

2.3.3 Garbage Output

In the synthesis of reversible functions, garbage outputs areneither the primary outputs nor required for future computa-tion [4, 13, 16]. So, all logic gates (except inverters) requiregarbage outputs and ancilla inputs to satisfy one to one map-ping between inputs and outputs. The garbage outputs in-crease the information loss of a reversible circuit. Therefore,it is desired to decrease the number of garbage outputs [22].

2.3.4 Logical Depth and Delay

In a reversible circuit, any number of primitive gates, whichcan be applied in parallel are considered as one logic level.The number of logical levels in a reversible circuit is calledlogical depth. The logical depth in a reversible circuit is lessthan or equal to the number of its primitive gates. Delay and

Fig. 2 Reversible gates in SFgates family. (a) SWAP gate, (b)3 × 3 positive controlled Fredkingate, (c) 3 × 3 negative controlledFredkin gate, and (d) n × n multi-ple controlled Fredkin gate

Fig. 3 Clifford+T quantumlibrary. (a) NOT, (b) CNOT, (c)T, (d) T†, (e) S, (f) S†, and (g) H

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logical depth are two interdependent parameters. The defini-tion of delay in [22] uses the quantum cost and logical depthconcepts to introduce a measure of the delay in reversiblelogic circuits. The main aspect of this definition is its comput-ability based on the quantum implementation of the gates. Thedelay of each 1 × 1 and 2 × 2 reversible gate is considered asunit delay called 1Δ. The delay is equal to the number ofprimitive quantum gates in the critical path [1, 17, 22, 31].The Critical Path Delay (CPD) is the path with maximumdelay [22]. Total delay from the input to output is:

Delay ¼ depth� Δ ð1Þ

A 3 × 3 Toffoli gate can be implemented using 5 quantumprimitive gates. But the critical path has 3 gates with a totaldelay 4Δ. So the delay for the 3 × 3 Toffoli gate is 4Δ. Thegeneralized Toffoli gate is implemented by 2n − 3 of 2 × 2quantum gates. The delay of these implementations is equalto 2n − 3 of quantum primitive gates of critical path delay inthe reversible circuit. According to the definition of the delayconcept in [22], the delay of well-known reversible gates isshown in Table 2.

Table 1 The quantum cost of well-known reversible logic gates

NCT gate family SF gate family

Size Gate QC Gate QC

1 NOT 1 × ×

2 CNOT/2 × 2 Toffoli 1 SWAP 3

3 3 × 3 Toffoli 5 3 × 3 Fredkin 5

4 4 × 4 Toffoli 13 4 × 4 Fredkin 13

5 5 × 5 Toffoli 29 5 × 5 Fredkin 29

n n × n Toffoli 2n-3 n × n Fredkin 2n-3

Table 2 The delay of well-known reversible logic gates

NCT gate family SF gate family

Size Gate Delay Gate Delay

1 NOT 1Δ × ×

2 CNOT/2 × 2 Toffoli 1Δ SWAP 3Δ3 3 × 3 Toffoli 4Δ 3 × 3 Fredkin 4Δ4 4 × 4 Toffoli 13Δ 4 × 4 Fredkin 13Δ5 5 × 5 Toffoli 29Δ 5 × 5 Fredkin 29Δn n × n Toffoli (2n-3)Δ n × n Fredkin (2n-3)Δ

Fig. 4 The 3-input reversible majority voter in [7]

Fig. 5 Reversible gates. (a) NOTgate (NOT), (b) Feynman gate(Fe), (c) Toffoli gate (To), and (d)Fredkin gate (Fr) [33]

Fig. 6 Minimal Triplicated Voter (MTV) in [33]

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3 Related Works

In the literature, only a few designs of reversible majorityvoter circuits have been proposed [7, 24, 33]. The simplest3-input reversible majority voter circuit is presented in [7].The authors used a reversible fault-tolerant scheme for classi-cal computing at the gate level based on Von-NeumannMultiplexing and to offer a reversible fault-tolerant

multiplexing scheme using a 3-bit repetition code. Themultiplexing scheme uses the reversible extension of majoritygate (MAJ) instead of the irreversible NAND gate or somederivatives. A proposed majority voter circuit in [7] is shownin Fig. 4. The quantum cost of 3-input reversible majorityvoter proposed in [7] is 7 and can be used in designing fault-tolerant reversible circuits base on triple modular redundancy.

In [33], two reversible majority voters with different fault-masking and fault detection capabilities for reversible circuitsare presented. Both proposed reversible majority voters cir-cuits consist of two garbage lines and two constant inputs.Garbage outputs are used in providing fault diagnosis whilemasking fault occurs. Therefore, fault-tolerant capability ofreversible majority voters increases the reliability of the cir-cuit. The advantage of the reversible majority voters is theirrobustness against a single point of failure. The reversiblemajority voter is producing all ‘0’ or all ‘1’ on outputs. Thegates used in the design of these two reversible majority votersas shown in Fig. 5. The symbols of a NOT, C-NOT, andToffoli gate are shown in Fig. 5(a), 5(b), and 5(c), respective-ly. Figure 5(d) show the symbols of a Fredkin gate that foreach i, Gi = Ci. If all Cis are 0, then F1 = T2 and F2 = T1, oth-erwise F1 = T1, and F2 = T2.

Minimal Triplicated Voter (MTV) is the first implementa-tion of the proposed voters in [33] that is shown in Fig. 6. InMTV voter, three copies of the output are generated, whichare calculated based on the value of inputs. The F2G gate isbasically designed by 2 Feynman gates. The fault is masked ifonly one fault occurs on inputs. In other words, it is not pos-sible to mask more than one fault. The second implementationof the proposed votes in [33] is Robust Triplicated Voter(RTV) that is shown in Fig. 7. In RTV voter each copy ofthe voted value is produced independently and directly fromthe inputs. The proposed voters provide three copies of thevoted output to the implementation of TMR architecture.

The authors in [24] present a simpler and low-cost ap-proach for designing a 3-input reversible majority voter inreversible logic. The quantum cost of this reversible majorityvoter is 6 that is shown in Fig. 8. Also, a 4-input reversiblemajority voter is presented in [24]. It consists of three CNOTgate and one four Toffoli gate that is shown in Fig. 9.Figure 10 shows the 5-input reversible majority voter, which

Fig. 7 Robust Triplicated Voter (RTV) in [33]

Fig. 8 The 3-input reversible majority voter in [24]

Fig. 9 The 4-input reversible majority voter in [24]

Fig. 10 The 5-input reversiblemajority voter in [24]

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is proposed in [24]. The quantum cost of this reversible ma-jority voter is 54.

4 Proposed Designs

This section presents a novel design of a 5-input reversiblemajority voter. Also, fault diagnosis schemes for 3 and 5 inputfault-tolerant reversible majority voters are presented. Thesemodules perform the fault-masking and fault diagnosis in pro-posed designs.

4.1 Proposed 5-Input Reversible Majority Voter

The proposed 5-input reversible majority voter (MV5) circuitconsists of six inputs and six outputs which includes fivegarbage lines and one constant input. The logic function ofreversible MV5 can be presented as Eq. (2), where the inputsare labeled as a, b, c, d, and e respectively [5, 15].

MV5 a; b; c; d; eð Þ ¼ abcþ abdþ abeþ acdþ ace

þ adeþ bcdþ bceþ bdeþ cde ð2Þ

A reversible full adder circuit is used in designing a 5-inputreversible majority voter. The Fig. 11 illustrates a reversiblefull adder where the S and C are the sum and carry out foroutputs of full adder respectively and g1 and g2 are garbageoutputs [26, 34]. This is used as a part of the 5-input and 6-input reversible majority voter design. That are indicated bydashed lines in Fig. 12 and Fig. 13.

The proposed design of reversible MV5 is shown inFig. 12. In this work, a, b, c, d and e are labeled as inputsand the output is labeled as a0. A reversible full addercircuit can be used in designing a 5-input reversible major-ity voter. The dashed box on the left side of a 5-bit voter inFig. 12 shows a reversible full adder circuit. The structureof the proposed reversible MV5 is very simple and easy toimplement in the reversible circuit. The quantum cost ofour proposed 5-input reversible majority voter is 32.Evaluation results show that the proposed reversibleMV5 generates lower quantum cost compared to previousworks. The 5-input reversible majority voter can be used indesigning a 6-input reversible majority voter. The pro-posed 6-input reversible majority voter is shown in Fig. 13.

4.2 Proposed Fault-Tolerant Reversible MajorityVoters

In this section, different designs for 3 and 5 input fault-tolerantreversible majority voters are presented. These modules per-form fault-masking and fault diagnosis in the scope of n-modular redundancy. The block diagram and inner design ofthe 3-input fault-tolerant reversible majority voter is shown inFig. 14 and it consists of three inputs (a, b, and c) and twocontrol inputs (Pin1, Pin2). Three outputs are m1, m2, and m3and two garbage outputs are g1 and g2. The voting is per-formed on the input values of a, b, and c and the results aregenerated on the outputs. In this reversible voter, each threecopy of the voted value is produced independently and direct-ly from the inputs. The inner design contains 4 steps that areindicated by dashed lines in Fig. 14. The objective of fault-tolerant reversible majority voter’s implementation are pro-ducing all ‘0’ or all ‘1’ on three data outputs. In other words,two permutations out of eight possible permutations of theseoutputs are used in the implementation. In order to maintainreversible, at least two garbage outputs are required. Twogarbage outputs are exploited to perform fault diagnosis andfault location. In reversible circuit, fan-out is not possible. Theproposed fault-tolerant reversible majority voters offer three

Fig. 11 A reversible full adder circuit [26, 34]

Fig. 12 Proposed design of 5-input reversible majority voter

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copies of the given output values for efficient implementationof the triple modular redundancy. In addition, Triple outputscan be implemented to eliminate the single point of failureproblem in the reversible majority voter. The behavior of 3-input fault-tolerant reversible majority voter is characterizedby the truth table in Table 3.

In the following, three designs of the 5-input fault-tolerantreversible majority voter circuit are presented. All three of 5-input fault-tolerant reversible majority voter contains five in-puts a, b, c, d, and e. Similar to 3-input fault-tolerant reversiblemajority voters, the objective of all three voters implementa-tion are producing all ‘0’ or all ‘1’ on data outputs. In otherwords, two permutations out of 32 possible permutations ofthese outputs are used in the implementation. It uses garbageoutputs to perform fault diagnosis. The first design of theproposed 5-input fault-tolerant reversible majority voter in-cludes 5 control inputs and 7 garbage outputs and three out-puts that is shown in Fig. 15. The second design of the pro-posed 5-input fault-tolerant reversible majority voter includes

4 control inputs and 6 garbage outputs and three outputs that isshown in Fig. 16. Both of the proposed voters can providethree independent and direct copies of the voted output. Thethird design of proposed 5-input fault-tolerant reversible ma-jority voter includes 6 control inputs and 6 garbage outputsand 5 outputs that is shown in Fig. 17. It can also provide fiveindependent and direct copies of the voted output. All threevoters’ implementation design can mask two faults in theinputs.

4.3 Realizations with Clifford+T

In order to implement reversible circuits on a real quantumcomputing platform like IBM’s QX architecture, they shouldbe mapped to Clifford+T gates and then implement on IBM’sQX architecture. An implementation of the proposed 5-inputmajority voter and 3 input fault-tolerant reversible majorityvoters are demonstrated with Clifford+T gates in Fig. 18 andFig. 19, respectively.

Fig. 13 Proposed design of 6-input reversible majority voter

Fig. 14 The proposed design of 3-input fault-tolerant reversible majority voters

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4.4 Proposed Fault Diagnosis Schemes

The fault of inputs can occur in two cases:

& Recoverable Faults: If only one fault occurs on inputs andone or two faults in the control inputs, it can be masked anddoes not affect circuit performance and it can be recoveredby the 3-input fault-tolerant reversible majority voter.

& Unrecoverable Faults: Any fault that changes more thanone copy of the outputs on a 3-input fault-tolerant revers-ible majority voter is not recoverable.

The block diagram of 3-input fault diagnosis reversiblemajority voter is shown in Fig. 20. In the proposed design of3-input fault diagnosis reversible majority voter, the outputvalue is calculated based on the input values. The outputvalues are produced directly and independent of each other

Table 3 Inputs and outputs relation of 3-input fault-tolerant reversiblemajority voter

Inputs Outputs

Pin1 Pin2 a b c m1 m2 m3 g1 g2

0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1

0 0 0 1 1 1 1 1 1 1

0 0 1 0 0 0 0 0 1 1

0 0 1 0 1 1 1 1 0 1

0 0 1 1 0 1 1 1 1 0

0 0 1 1 1 1 1 1 0 0

m1,m2 and m3 =MV3(a, b, c), g1 = a⊕ b, g2 = a⊕ c

Fig. 15 The first design of the proposed 5-input fault-tolerant reversible majority voter

Fig. 16 The second design of the proposed 5-input fault-tolerant reversible majority voter

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Fig. 17 The third design of the proposed 5-input fault-tolerant reversible majority voter

Fig. 18 Proposed design of 5-input reversible majority voter realized with Clifford+T library

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Fig. 19 Proposed design of 3-input fault-tolerant reversible majority voter realized with Clifford+T library

Fig. 20 Block diagram of 3-inputfault diagnosis reversible majorityvoter

Table 4 Diagnosis table for the 3-input fault diagnosis reversiblemajority voter

Outputs Fault location Fault in truth table

g1 g2 m1 m2 m3 a, b, c Pin1, Pin2 Pin2Pin1cba→m3g2g1m2m1

0 0 m1 =m2 =m3 a→NF, b→NF,c→NF

Pin1→NF,Pin2→NF

0 0 m1 ≠m2 =m3 a→NF, b→ F,c→NF

Pin1→ F,Pin2→ F

11,101→ 00001,11,010→ 10,010

0 0 m1 =m2 ≠m3 a→NF, b→NF,c→NF

Pin1→NF,Pin2→ F

0 0 m1 ≠m2 ≠m3 a→NF, b→ F,c→NF

Pin1→ F,Pin2→NF

0 1 m1 =m2 =m3 a→NF, b→ F,c→NF

Pin1→NF,Pin2→NF

0 1 m1 ≠m2 =m3 a→NF, b→NF,c→NF

Pin1→ F,Pin2→ F

11,111→ 01001,11,000→ 11,010

0 1 m1 =m2 ≠m3 a→NF, b→ F,c→NF

Pin1→NF,Pin2→ F

0 1 m1 ≠m2 ≠m3 a→NF, b→NF,c→NF

Pin1→ F,Pin2→NF

1 0 m1 =m2 =m3 a→NF, b→NF,c→ F

Pin1→NF,Pin2→NF

1 0 m1 ≠m2 =m3 a→ F, b→NF,c→NF

Pin1→ F,Pin2→NF

01001→ 10,110,01110→ 00101

1 0 m1 =m2 ≠m3 a→NF, b→NF,c→ F

Pin1→NF,Pin2→ F

1 0 m1 ≠m2 ≠m3 a→ F, b→NF,c→NF

Pin1→ F,Pin2→ F

1 1 m1 =m2 =m3 a→ F, b→NF,c→NF

Pin1→NF,Pin2→NF

1 1 m1 ≠m2 =m3 a→NF, b→NF,c→ F

Pin1→ F,Pin2→NF

01011→ 01101,01100→ 11,110

1 1 m1 =m2 ≠m3 a→ F, b→NF,c→NF

Pin1→NF,Pin2→ F

1 1 m1 ≠m2 ≠m3 a→NF, b→NF,c→ F

Pin1→ F,Pin2→ F

F: fault, NF: no-fault.

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by input values in three copy. This module provides a diag-nosis of faults on the reversible majority voter of the previousTMR stage. For the status of triple outputs and two garbageoutputs, one can detect the presence of identical triple inputvalues from the previous stage reversible circuits. Eight per-mutations out of 32 possible permutations of these outputs areincorrect in the implementation. In other words, permutationsobtained from m1 ≠m2 =m3 row are incorrect (see Table 4for details). To correct the output of the 8 permutations mustbe reversed. The diagnosis method on all possible faults of theinputs is stated in Algorithm 1.

The block diagram of the proposed 5-input fault

diagnosis reversible majority voter is shown in Fig. 21.In the proposed design of 5-input fault diagnosis revers-ible majority voter, the output value is calculated based onthe input values. Then, three or five copies of the outputvalues are produced directly and independent of each oth-er by input values. This module provides a diagnosis offaults on the reversible majority voter of the previous5MR stage. Table 5 shows the diagnosis of all possiblefaults of the inputs.

Fig. 21 Block diagram of 5-inputfault diagnosis reversible majorityvoter

Table 5 Truth table for 5-input fault diagnosis reversible majority voter

Outputs Fault location

g1 g2 g3 g4 g5 g6 a, b, c, d, e

× 0 1 1 0 × a→NF, b→NF, c→NF, d→NF, e→NF

× 1 1 1 0 × a→ F, b→NF, c→NF, d→NF, e→NF

× 0 1 1 1 × a→NF, b→ F, c→NF, d→NF, e→NF

× 1 1 1 1 × a→ F, b→ F, c→NF, d→NF, e→NF

× 0 0 1 1 0 a→NF, b→NF, c→ F, d→NF, e→NF

× 1 0 1 1 1 a→ F, b→NF, c→ F, d→NF, e→NF

× 0 0 1 0 0 a→NF, b→ F, c→ F, d→NF, e→NF

× 1 0 1 0 0 a→NF, b→NF, c→NF, d→ F, e→ F

× 0 1 0 1 × a→NF, b→NF, c→NF, d→ F, e→NF

× 1 1 0 1 × a→ F b→NF, c→NF, d→ F, e→NF

× 0 1 0 0 × a→NF, b→ F, c→NF, d→ F, e→NF

× 1 1 0 0 × a→NF, b→NF, c→ F, d→NF, e→ F

× 1 0 1 0 1 a→NF, b→NF, c→ F, d→ F, e→NF

× 0 0 1 0 1 a→NF, b→ F, c→NF, d→NF, e→ F

× 1 0 1 1 0 a→ F, b→NF, c→NF, d→NF, e→ F

× 0 0 1 1 1 a→NF, b→NF, c→NF, d→NF, e→ F

F:fault, NF: no-fault, ×: don’t care.

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5 Evaluation

In this Section, some comparisons between proposed designsand existing designs in the literature are presented. Some ofthe optimal metrics like Depth, Critical Path Delay (CPD),Quantum Cost (QC), and Total Logic Calculation (TLC) areused in the evaluation. It is assumed that: α = the count ofCNOT gate, β = count of Toffoli gate, γ = count of Fredkingate, and T = Total logical calculation. The CPD is the delayof the longest path between any input and any output. For amore detailed comparison of the designs in literature and theone presented in this paper, they should be mapped to Clifford+ T gate. In Table 6, the results of the proposed design of the5-input reversible majority voter, in terms ofDepth, CPD, QC,and TLC in comparison to related work in [24] are reported.The proposed design of the 5-input reversible majority voter issimple in design and offers lower cost in terms of CPD andQC than the existing 5-input reversible majority voter in [24].Both designs are realized in terms of Clifford+T gates. Theproposed reversible majority voter resulted in circuits with upto 50% fewer QC compared to the circuit in [24]. Results arereported in Table 7.

In order to evaluate the proposed design of the 3-inputfault-tolerant reversible majority voter, a comparison withboth works in [33] are performed. Results are reported inTable 8. Similarly, a comparison of these voters, which arerealized with the Clifford+T library is shown in Table 9. Thistable indicates a 20% reduction compared to RTV Design anda 29% reduction compared to MTV Design in the QC metric.

Finally, Table 10 shows the comparison between the threedesigns of the 5-input fault-tolerant reversible majority voters.Then, proposed voters mapped to Clifford+T circuit to comparetogether in the QCmetric that is shown in Table 11. Overall, theevaluation confirms the effectiveness of proposed designs incomparison with the existing designs in the literature.

6 Conclusion

This paper presents a design of a 5-input reversible majorityvoter. The proposed design is simplest and of lower cost thanexisting designs in the literature. The proposed design hasbeen provided for extending the reversible majority voter ton-input reversible majority voter. The proposed reversibleMV5 has considerable improvement in comparison to the pre-vious reversible majority voters in terms of quantum cost. Acomparative analysis of proposed reversible MV5 with previ-ous works is performed that validates the correctness and ef-fectiveness of the proposed designs. The proposed reversiblemajority voter designs can be used to achieve fault-tolerant in

reversible circuits and can be used to generate a correctedoutput in the presence of a fault. Also, this paper presents

Table 6 Comparison of proposed 5-input reversible majority voter with[24]

Depth CPD QC TLC

Existing [24] 8 51Δ 58 7α + 1β + 2γ

Proposed [Fig. 12] 8 28Δ 32 4α + 2β + 2γ

Table 7 Comparison of proposed 5-input reversible majority voter with[24] realized with Clifford+T library

No. of 2-qubit gates No. of 1-qubit gates QC

Existing [24] 101 150 101

Proposed [Fig. 12] 50 70 50

Table 8 Comparison of proposed 3-input fault diagnosis reversible ma-jority voter with [33]

Depth CPD QC TLC

RTV Design [33] 7 16Δ 19 6α + 3β

MTV Design [33] 6 15Δ 20 3α + 3γ

Proposed [Fig. 14] 3 7Δ 17 5α + 1β + 1γ

Table 9 Comparison of proposed 3-input fault diagnosis reversible ma-jority voter with [33] realized with Clifford+T library

No. of 2-qubit gates No. of 1-qubit gates QC

RTV Design [33] 24 30 24

MTV Design [33] 22 35 27

Proposed [Fig. 14] 19 20 19

Table 10 Comparison between three designs of the 5-input fault-toler-ant reversible majority voter circuits

Depth CPD QC AI GO TLC

Proposed [Fig. 15] 11 54Δ 80 5 7 9α + 6β + 3γ

Proposed [Fig. 16] 11 55Δ 79 4 6 8α + 6β + 3γ

Proposed [Fig. 17] 15 60Δ 95 6 6 17α + 6β + 4γ

Table 11 Comparison between three designs of the 5-input fault-toler-ant reversible majority voter circuits realized with Clifford+T library

No. of 2-qubit gates No. of 1-qubit gates QC

Proposed [Fig. 15] 123 180 123

Proposed [Fig. 16] 122 184 126

Proposed [Fig. 17] 138 191 139

768 J Electron Test (2020) 36:757–770

different implementations of the 3-input and 5-input fault-tol-erant reversible majority voters. Proposed fault-tolerant re-versible majority voters provide information for online andoffline fault diagnosis. They can also provide diagnostic in-formation to a masked fault in the reversible majority votercircuits. Such diagnostic information can be used in offlineand online tests.

To implement proposed designs on a real quantum com-puting platform like IBM QX architecture, they need to bemapped to Clifford+T circuits. For a more detailed evaluationof the proposed designs, they should be mapped to Clifford +T gate. The result has lower cost to implement on a real quan-tum computing platform like IBMQX architecture. In order tomake the reversible majority voter robust by providing a guardagainst this potential single point failure is an area for furtherresearch. One potential approach is to add an online test fea-ture to the reversible majority voter, so the test of the revers-ible majority voter can indicate whether the reversible major-ity voter circuit is faulty or fault-free.

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Davar Kheirandish received his M.Sc. degree in computer architecturefrom Faculty of Technical & Engineering, Department of ComputerEngineering, Tabriz Branch, IAU University, Tabriz, Iran. He is currentlyworking toward the Ph.D. degree in Computer Hardware Engineering atDepartment of Computer Engineering in Islamic Azad UniversityScience and Research Branch, Tehran. His Research interests includereversible logic, fault tolerance and quantum reversible circuit design.

Majid Haghparast received his B.Sc. degree in computer hardware en-gineering in 2003. He received his M.Sc. and Ph.D. degrees in computerarchitecture in 2006 and 2009, respectively. Since 2007, he has beenaffiliated with the Computer Engineering Faculty, Yadegar-e-ImamKhomeini (RAH) Branch, IAU University, Tehran, Iran. He is currentlyan Associate professor and the head of computer engineering departmentat IAUSR. He has also been selected as his university’s best researcher in

2017. Majid has published more than 50 research papers in various inter-national journals and conferences. His research interests include CloudComputing, WSNs, reversible logic and computer arithmetic. Since April2017 he is on sabbatical at the Johannes Kepler University Linz, Austria,where he also is a Research Fellow. He served in more than 40 interna-tional conference advisory and technical program committees. Dr.Haghparast is on the panel of reviewers for various international journals.

Midia Reshadi is currently an Assistant Professor in ComputerEngineering Department at Science and Research Branch of AzadUniversity since 2010. His research interest is Network-on-chip includingperformance and cost improvement in topology, routing and applicationmapping design levels of various types of NoCs such as 3D, photonic andwireless. Recently, he has started carrying out research in NoC based deepneural network accelerators and Silicon interposer based NoC with histeam of MSc and PhD students.

Mehdi HosseinZadeh received his B.S. degree in computer hardwareengineering from Islamic Azad University, Dezfol branch, Iran in 2003.He also received his M.Sc. and the Ph.D. degrees in computer systemarchitecture from the Science and Research Branch, Islamic AzadUniversity, Tehran, Iran in 2005 and 2008, respectively. He is currentlyan Associate professor in Iran University of Medical Sciences (IUMS),Tehran, Iran, and his research interests include SDN, InformationTechnology, Data Mining, Big data analytics, E-Commerce, E-Marketing, and Social Networks.

770 J Electron Test (2020) 36:757–770