efm8ub1 universal bee stk - silicon labs universal bee stk revision history " # $ % %% &...

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Board Function Page

Title Page

1

2

3

4

5

User Interfaces

Signal Assignments

EFM8 I/O

STK Common Platform

Rev. Description

Revision HistoryEFM8UB1 Universal Bee STK

9

8

7

6

10

A00 Initial prototype version.

Advanced Energy Monitor

Board Controller

Clock & Filter

Power & Misc

Debug Interface

Initial version released for series

production.

A01

Changed ESD protection diode for

the EFM8's USB.

A02

Updated PCB revision.

A03

Size

Designed:

Revision

Sheetof

Approved:

Sheet Created Date Sheet Modified Date

Document number

Schematic Title

Design Created Date:

BOM Doc No:

Page Title

A03BRD5000A

Monday, March 23, 2015 1 10

A3

MRW JNO

EFM8UB1 Universal Bee Starter Kit

Thursday, May 15, 2014Wednesday, December 03, 2008

STK

Title Page

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO



STK

Title Page

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO



STK

Title Page

PCB1

PCB5000

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

��

User pushbuttons

EXP port

RGB LEDBreakout Connections Analog Joystick

P0.6P1.1P2.1P2.2

2 VMCU

1 GNDCMP0.0/ADC0.0

5V

SPI0_SCKSPI0_NSS

SPI0_MOSISPI0_MISO

P1.0P0.7

P1.2

20 3V3

46

108

12141618

I2C0_SDA

UART1_TXUART1_RX

P1.3

P0.0

19

35

97

11131517

I2C0_SCL

EXP-Header Functionality

Reserved for EXP Board IdentificationReserved for EXP Board Identification

CMP1.3/ADC0.11

CMP1.0/ADC0.8CMP0.7/ADC0.7CMP0.6/ADC0.6CMP1.1/ADC0.9CMP1.10/ADC0.21CMP1.11/ADC0.22CMP1.2/ADC0.10

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

RESET Pushbutton

P1.4P1.5P1.6P2.3P3.1

CMP1.4/ADC0.12CMP1.5/ADC0.13CMP1.6/ADC0.14

** STK LED0

CMP1.12/ADC0.23

** STK LED1** STK LED2

** Indicates potential STK hardware conflicts

U.FL ADC Connection

DISP_CTRL VDISP

1

0

EFM

BC

VMCU

BC_DISP_PWR_EN

The EFM8 always controls ownership of the displayusing the EFM_DISP_ENABLE signal.

EFM_DISP_ENABLE

Memory LCD-TFT Display & Multiplexer

��

EXP_HEADER3 P0.0 P1.0 EXP_HEADER4P0.7 EXP_HEADER6P0.6 EXP_HEADER8P1.1 EXP_HEADER10P2.1 EXP_HEADER12P2.2 EXP_HEADER14P1.2 EXP_HEADER16EXP_HEADER15 P1.3

MCU_P0.0MCU_P0.1MCU_P0.2MCU_P0.3

MCU_P3.0MCU_P3.1

JS_COMM

JS_C

EXP_HEADER5 P1.4EXP_HEADER7 P1.5EXP_HEADER9 P1.6EXP_HEADER11 P2.3EXP_HEADER13 P3.1

MCU_P0.4MCU_P0.5MCU_P0.6MCU_P0.7MCU_P1.0MCU_P1.1MCU_P1.2MCU_P1.3

DISP_SCLKDISP_MOSIDISP_CSDISP_COM

MCU_P2.1MCU_P2.0

MCU_P2.2MCU_P2.3

MCU_P1.7MCU_P1.6MCU_P1.5MCU_P1.4

GND

GND

VMCU

GND GND

3V3VMCU

GND

5V

VMCU

VMCU

3V3

GND

VMCU

GND

5V

GND

GND

GND GNDGND GND GND GND

VMCU

GND

GND

3V3

GND GND

GNDGND

V_SW

VDISP

GNDGND

VMCU

GND GND

VDISP

3V3

UIF_PB0UIF_PB1

EXP_HEADER[16..3]

UIF_JOYSTICKMCU_P0.[7..0]

MCU_P1.[7..0]

MCU_P3.[1..0]

BC_EXP_I2C_SCLBC_EXP_I2C_SDA

UIF_PBRESET

UIF_LED2

UIF_LED1

UIF_LED0

UFL_ADC_IN

EFM_DISP_ENABLE

BC_DISP_PWR_ENBC_DISP_SCLKBC_DISP_MOSIBC_DISP_CS

EFM_DISP_MOSIEFM_DISP_CS

EFM_DISP_SCLK

MCU_P2.[3..0]

MCU_P1.[7..0]

BC_DISP_AVAILABLE

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A

Thursday, February 12, 2015 2 10

A3

MRW JNO


Wednesday, August 28, 2013Wednesday, December 03, 2008

STK

User Interfaces

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO



STK

User Interfaces

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO



STK

User Interfaces

R12633K

R1021M

R1011MU106A

TS3A44159

COM112

COM216

IN1-214

NC113

NO111

NC21

NO215

NC49

NO47 NO33

NC35

COM34

COM48

IN3-46

TP

151

R137

2320

R1310RNM

DISP1

LS013B7DH03

J102

NM

12345678910111213141516

SW101

1

3

2

4

TP

150

C101

1N

R135

698

C104

100N

R1078100K

R1281K

RBG

LED2RGB

1

234

TP154

R1320R

P101

XF2L-1025-1A_MEMLCD

SCLK10

SI9

SCS8

EXTCOMIN7

DISP6

VDDA5

VDD4

EXTMODE3

VSS2

VSSA1

R82050RNM

R12415K

C103

100N

TP

152

SW103

1

3

2

4

R100100R

M4

25x4mm

R136

910

SW100

1

3

2

4

U106B

TS3A44159

V+10

GND2

C107

100N

J101

NM

123456789

10111213141516

R11110K

R113100R

R12510K

R1049100R

R12760.4K

C102

100N

TP

153

R103100R

J104U.FL

NM

3

21

R110100K

M5

25x4mm

Q100DMN5L06WK

1

32

C100

1N

C106

1N

R10510M

SW102

1

2

3

4

5

6

P100

HEADER_2X10_2.54MM_HOR_SMD

1 24

86

10

35

97

1213 1411

15 161719

1820

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

P2 Connections

P0 Connections

P3 & DEBUG Connections

P1 Connections

MCU_P1.1 SPI0_CS

MCU_P1.0 SPI0_MOSI

MCU_P1.3 I2C0_SCL

MCU_P1.4 PCA0_CEX0

MCU_P1.5 PCA0_CEX1

MCU_P1.6 PCA0_CEX2

MCU_P1.7

MCU_P1.2 I2C0_SDA

MCU_P3.0

MCU_P2.0

MCU_P2.1 UART1_TX

MCU_P2.2 UART1_RX

MCU_P2.3

MCU_P0.2

MCU_P0.1

MCU_P0.3

MCU_P0.4 UART0_TX

MCU_P0.5 UART0_RX

MCU_P0.6 SPI0_SCK

MCU_P0.7 SPI0_MISO

MCU_P3.1

MCU_P0.0 GND

EFM_USB_VBUS

MCU_P1.[7..0]

MCU_P2.[3..0]

MCU_P0.[7..0]

UIF_PB1

EFM_DISP_SCLK

UIF_PB0

MCU_P3.[1..0]

EFM_DISP_CS

EFM_BC_EN

MCUDBG_TMS_SWDIO_C2D

EFM_BC_RX

EFM_BC_TX

MCUDBG_TCK_SWCLK_C2CKEFM_C2CK_RESET

UIF_PBRESET

UIF_JOYSTICK

UIF_LED2

UIF_LED1

UIF_LED0

EFM_DISP_MOSI

EXP_HEADER6

EXP_HEADER8

EXP_HEADER3

EXP_HEADER9

EXP_HEADER7

EXP_HEADER5

EXP_HEADER15

EXP_HEADER16

EXP_HEADER10

EXP_HEADER4

EXP_HEADER11

EXP_HEADER14

EXP_HEADER12

EXP_HEADER13

EFM_C2D

MCUDBG_C2CK_PS

MCUDBG_C2D_PS

BC_1KHZ_SINE

BC_REFCLK

EFM_DISP_ENABLE

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A

Thursday, December 18, 2014 3 10

A3

MRW JNO


<Cage Code>


Signal Assignments

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


Signal Assignments

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


Signal Assignments

R1059

0R

R1057

0R

R1055

1K

R1054

1K

R1056

1K

R138

0R NM

R1053

0R

R139

0R

R1095

100R

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB Connection and ESD protection

VBUSD-D+

Layout note:Rotate such thatthe battery is usedwhen switch is inthe left position

Power Switch

SWITCH

POS

AEM

MODE DESCRIPTION

USB

AEM Enabled, VMCU sourced from external 3.3V LDO

powered by BC USB 5V supply

AEM Disabled, VMCU sourced from internal 3.3V LDO

powered by EFM8 USB 5V

BAT

AEM Disabled, VMCU sourced from external

coin-cell battery or external power supply

C2 Debug Header

��

�

��

��

* PopulateR134 fornon-USBdevices.

��

�� MCU_P0.1

MCU_P0.0

MCU_P0.2

MCU_P0.3

MCU_P0.4

MCU_P0.5

MCU_P0.6

MCU_P0.7

MCU_P1.1

MCU_P1.0

MCU_P1.2

MCU_P1.3

MCU_P1.4

MCU_P1.5

MCU_P1.6

MCU_P1.7

MCU_P2.0

MCU_P2.1

MCU_P2.2

MCU_P2.3

MCU_P3.1

GND

VMCU

GND

GND

GND

EFM_USB_VBUS

GND

VMCU

GND

GNDGND

VMCU

EFM_USB_VBUS

VMCU

GND

GND GNDGND

GND

5V

EFM_USB_DP

EFM_USB_DM

MCU_P0.[7..0]

MCU_P1.[7..0]

MCU_P2.[3..0]

EFM_USB_DPEFM_USB_DM

EFM_VREGIN

EFM_VREGIN

EFM_C2CK_RESET

AEM_VMCU_OUT

MCUDBG_TMS_SWDIO_C2DMCUDBG_TCK_SWCLK_C2CK

EFM_C2D

MCU_P3.1

UFL_ADC_IN

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


EFM8 I/O

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


EFM8 I/O

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


EFM8 I/O

TP155

TP

J403

R140

0R

53 41 2

P103USB MICRO-B

1 2 3 4 5

678

91011

C112

100N

ST1NM

12

C111

10U

D1SP0505BAHT

1 2 3

456

TP

J404

L1

CBF221HC

1 2

R119 0R

R1171K

TP

J405

U103

EFM8UB10F16G-B-QFN28

P2.

113

P2.

014

D+4

VIO/VDD6

GND3

D-5

P0.0/VREF2

P0.1/AGND1

P1.715

P1.616

P1.517

P1.418

P2.

212

P2.

311

P0.

5/U

AR

T0_

RX

25

P3.

0/C

2D10

P0.

2/X

TA

L128

VREGIN7

P3.

1/V

BU

S8

RS

T/C

2CK

9

P1.319

P0.

6/C

NV

ST

R24

P1.220

P0.

3/X

TA

L227

P0.

4/U

AR

T0_

TX

26

P0.

723

P1.

022

P1.121

EP

AD

29

TP157

+

P700COIN_CELL

12

R134

0R NMQ1

NTS21012 3

C109

10U

TP156

R118 0R

C108

100N

TP704

SW104

SW_DP3T

12

34

56

78

J103

1X3 2.54MM

NM

123

C110

100N

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BC_IO5 BC_1KHZ_CLK

BC_IO[9..0]

BC_IO9

BC_IO0BC_IO2BC_IO3

BC_IO6

BC_IO8 BC_CLK_SWITCH_EN

BC_DAC1_OUT

BC_I2S_MCK

BC_I2S_WS

BC_I2S_CKBC_I2S_DATA

BC_DISP_AVAILABLE


MCUDBG_C2D_PS

UIF_PB0UIF_PB1

BC_EXP_I2C_SCLBC_EXP_I2C_SDA

MCUDBG_C2CK_PS

EFM_BC_EN

AEM_VMCU_OUT

BC_DISP_MOSIBC_DISP_SCLKBC_DISP_CS

BC_DISP_PWR_EN

EFM_BC_TXEFM_BC_RX

BC_1KHZ_SINE

BC_REFCLK

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


STK Common Platform

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


STK Common Platform

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


STK Common Platform

DEBUG

AEM

Board Controller GPIO

EXP Board Identification

VCOM

User Interface to BC

DAC Output

I2S

HB1

MCU STK Platform

UIF_PB0UIF_PB1 MCUDBG_TRACECLK

MCUDBG_TRACED[3..0]


MCUDBG_TDO_SWO

AEM_VMCU_OUT

MCUDBG_RESET_C2CKPS

VCOM_ENABLE

EXP_ID_SCL

VCOM_RXD

VCOM_#RTSVCOM_TXD

VCOM_#CTS

EXP_ID_SDA

MCUDBG_TDI_C2DPS

BC_DAC_OUT

BC_IO[9..0]

CTRLMCU_I2S_MCK

CTRLMCU_SPI_#CSCTRLMCU_SPI_MOSICTRLMCU_SPI_SCK

CONTROL & INPUTS OUTPUTS

HB2

CLK CIRCUITRY

BC_REFCLK

BC_DAC1_OUT

BC_I2S_DATABC_I2S_WS

BC_I2S_CKBC_I2S_MCK

BC_CLK_SWITCH_EN

BC_1KHZ_CLK

BC_1KHZ_SINE

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MCU Voltage Sense

MCU current sense

MCU power regulator

Sense Resistor

BleederResistor

3.30 uA100 uA220 uA320 uA3.30 mA

AEM_CTRL

0x10x20x40x60x8

CalibrationCurrent

AEM Calibration

AEM_CTRL0AEM_CTRL1AEM_CTRL2AEM_CTRL3

AEM_VMCU_OUT

3V3

GND GND

VMCU_BUF

GNDGND

5V

GND

GND

VMCU_R VMCU_S

GND GND

GND

GND GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

VMCU_R VMCU_S

GND

VCS

5V

GND GNDGND

3V6_SW

GND

AEM_SENSE_CURRENT_RANGE2

AEM_SENSE_CURRENT_RANGE1

AEM_CTRL[3..0]

AEM_SENSE_VOLTAGE

AEM_VMCU_ENABLE

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A

Thursday, November 13, 2014 6 10

A3

DDB JNO


<Cage Code>

Tuesday, May 13, 2014Monday, May 12, 2014

MCU STK Platform/HB1


Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

DDB JNO


<Cage Code>




Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

DDB JNO


<Cage Code>




R731

1R

R70615K

-

+

2

U1000B

AD8656

6

5

7

C724100N

C700

10U

C707

100N

C1001

1N

C70533N

TP708

TP707

U703 LTC6102CDD

-INF2

V-5

-INS1

VREG6

OUT4V-

3

V+7

IN+8

V- (HEAT)9

R7051K

C731

10U

C710100N

C1004

10P

R703110K

R7091K8

TP712

C718

1N

R70010K

R1003

62R

C704

100N

TP701

C729

10NNM

C714

10U

TP711

R1008

62R

R729100K

R71812K

C703

10U

TP706

R7081M

R760330K

L700CBF102WB

12

U1000C

AD8656

V+8

V-4

U700A

NX3V1G66

E4

n.c.5

Y1

Z2

U701

LP3982ILD-ADJ

IN2

OUT11

GND3

OUT24

FAULT8

CC6

SHDN7 SET

5

GND_HEAT9

C728

100N

R727

47K

R1009

51K

R1005160R

R702180K

TP705

R70733K

C920100N

R1004

51K

L1001CBF102WB

1 2

C1002

10P

R701

4R7

L702

CBF102WB

1 2

TP713

R7101K8

R101051K

C702

100N

U700B

NX3V1G66

VCC6

GND3

R1007

6K2

C730

100N

-

+

1

U1000A

AD8656

2

3

1

TP714

R71710R

C701

100N

U702B

TS3A4751

V+14

GND7

C1003

1N

R1002

6K2

TP700

U702A TS3A4751

COM12

COM24

NO23

COM39

NO38

COM410

NO411

NO11

IN113

IN25

IN36

IN412

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Debug out J-LinkStatus

Indicators:

BootloaderHalt pin

J-Link USB Port

Place these TPsclose to USBheader

BC_DAC_OUT

CTRLMCU_I2S_MCK

CTRLMCU_SPI_MOSICTRLMCU_SPI_SCK

CTRLMCU_SPI_#CS

EXP_ID_SDAEXP_ID_SCL

UIF_PB0UIF_PB1

BC_IO[9..0]

3V33V33V3

5V

GND GND

GND

GND

DEBUG_RESET_OUTDEBUG_TDI_OUTDEBUG_TMS_SWDIO_OUTDEBUG_TCK_SWCLK_OUT

DEBUG_TDI_INDEBUG_TMS_SWDIO_INDEBUG_TCK_SWCLK_INDEBUG_#RESET_INDEBUG_TDO_SWO_IN

DEBUG_EXT_VDD_TARGETDEBUG_EXT_CABLE_ATTACH

DEBUG_TCK_SWCLK_#OEDEBUG_TMS_SWDIO_#OE

DEBUG_MCU_ISOLATE_#ENDEBUG_RESET_#OE

AEM_SENSE_VOLTAGEAEM_SENSE_CURRENT_RANGE1AEM_SENSE_CURRENT_RANGE2

DEBUG_TDI_#OE

DEBUG_MCU_SW_ENABLEREF_BOARD_ID_SCLREF_BOARD_ID_SDA

BC_UART_TXDBC_UART_#RTS

BC_UART_RXD

BC_UART_#CTS

AEM_VMCU_ENABLE

AEM_CTRL[3..0]

DEBUG_DH_SW_ENABLE

BC_EXT_HEADER_ENABLE

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>

Wednesday, May 14, 2014Monday, May 12, 2014


Board Controller

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>



Board Controller

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>



Board Controller

D600

IP4220CZ6

1 2 3

456

R9032K

LED900

YELLOW

21

TPJ613

R9201K

R9003K

L600CBF221HC

1 2

TPJ612TPJ611

R G LED904LED_G_R

13

24

TPH999

R9191K

1 2 3 4 5

P601WR_COM_USB_MINI_B

8 6

1 2 3 5

79

4

CMCU1

Control MCU

BC_IO[9..0]

BC_DAC_OUT

CTRLMCU_I2S_MCK


DEBUG_TDI_#OEDEBUG_TCK_SWCLK_#OEDEBUG_TMS_SWDIO_#OEDEBUG_MCU_ISOLATE_#ENDEBUG_RESET_#OE

DEBUG_MCU_SW_ENABLE

LED_STATUS_RLED_STATUS_G

DEBUG_DH_SW_ENABLE

AEM_VMCU_ENABLE

AEM_CTRL[3..0]

LED_JLINK

LED_DEBUG_OUT

BC_UART_#RTSBC_UART_TXD


BOOTLOADER_HALT

USBDP

USBDM

DEBUG_TDI_INDEBUG_TMS_SWDIO_INDEBUG_TCK_SWCLK_INDEBUG_#RESET_INDEBUG_TDO_SWO_IN

DEBUG_EXT_VDD_TARGETDEBUG_EXT_CABLE_ATTACH


CTRLMCU_SPI_MOSICTRLMCU_SPI_SCK

CTRLMCU_SPI_#CS

BC_UART_#CTS

BC_UART_RXD


UIF_PB0UIF_PB1

LED901BLUE

21

TPJ614

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AMode DEBUG_MCU_SW_ENABLE DEBUG_DH_SW_ENABLE DEBUG_BUF_#OE DH_VTARGET VTARGET

MCU Debug 1 0 0 Disconnected VMCU

Debug In 1 1 1 VMCU VMCU

Debug Out 0 1 0 External voltage External voltage

ISOLATE_#EN

- -Debug Off 1 1 1

0

1

0

1

Power & Decoupling

MCUDBG_TRACED3MCUDBG_TRACED2MCUDBG_TRACED1MCUDBG_TRACED0

MCUDBG_TRACECLK

TMS_SWDIOTCK_SWCLKTDO_SWOTDI

DEBUG_HEADER_EN

#RESET

DH_TDO_SWO

DH_#RESET

DH_TCK_SWCLK_C2CKDH_TMS_SWDIO_C2D

DH_TDI

DH_VTARGET

MCU_SW_EN

MCUDBG_TRACECLKMCUDBG_TRACED[3..0]

MCUDBG_RESET_C2CKPS

MCUDBG_TMS_SWDIO_C2DMCUDBG_TCK_SWCLK_C2CKMCUDBG_TDO_SWOMCUDBG_TDI_C2DPS

GND

VTARGET

GND

VMCU_BUF

GND

GND

DH_VTARGET

DH_VTARGET DH_VTARGET

5V

3V3

GND

5V

GND

GND

VTARGET

VTARGET

VTARGET

VTARGET

GND

GNDGND GNDGND GND

VTARGET

GND

VTARGET

GND

3V3

5V

GND

V_SW

GND

GND

GND

GND

GND

GND GND

3V3

DEBUG_TDI_OUT

DEBUG_TCK_SWCLK_OUT

DEBUG_TDI_IN

DEBUG_TMS_SWDIO_INDEBUG_TCK_SWCLK_INDEBUG_TDO_SWO_IN

DEBUG_#RESET_IN

DEBUG_TDI_#OE

DEBUG_TMS_SWDIO_#OE

DEBUG_TMS_SWDIO_OUT

DEBUG_DH_SW_ENABLE

DEBUG_MCU_SW_ENABLE

DEBUG_RESET_#OE

DEBUG_MCU_ISOLATE_#EN

DEBUG_EXT_VDD_TARGET

DEBUG_TCK_SWCLK_#OE

DEBUG_RESET_OUT

DEBUG_EXT_CABLE_ATTACH

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A

Wednesday, October 22, 2014 8 10

A3

DDB JNO


<Cage Code>

Monday, May 12, 2014Monday, May 12, 2014


Debug Interface

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

DDB JNO


<Cage Code>



Debug Interface

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

DDB JNO


<Cage Code>



Debug Interface

C800

100N

R81410M

C807

100N

R815

1M

C890

10N

P800

1 23 45 6

89 10

11 1213 1415 1617 1819 20

TP

J811

L800CBF102WB

1 2

U804C

74LVC2G125

VCCA2

GNDD1

R811

100R

TP

J814

U802A74LVC4066

1Y1

1Z2

1E13

2Y4

3Y8

4Y11

2Z3

3Z9

4Z10

2E5

3E6

4E12

R8084K7

D800VESD05A8A-HNH

1 2 3 4 5 6 7 8

9

Q800DMN5L06WK1

3 2

U808B

74LVC8T245

VCCA1

GND12GND11

VCCB24 VCCB23

GND13

PAD25

R805

33R

R8074K7

C803

100N

C804

100N

U809A74LVC2G125

B1C2

A1

U809B74LVC2G125

D2

B2

C1

L801

CBF102WB

12

D801PESD5V0F5UF

1 3 4 5

2

6

U808A

74LVC8T245

A13

A24

A35

A46

A57

A68

A79

A810

B121

B220

B319

B418

B517

B616

B715

B814

OE22

DIR2

U806B

74LVC4066

VCC14

GND7

RP801

33R

1234 5

678

U800B

74LVC4066

VCC14

GND7

TPJ813

U806A74LVC4066

1Y1

1Z2

1E13

2Y4

3Y8

4Y11

2Z3

3Z9

4Z10

2E5

3E6

4E12

R809100KNM

U800A74LVC4066

1Y1

1Z2

1E13

2Y4

3Y8

4Y11

2Z3

3Z9

4Z10

2E5

3E6

4E12

U805B

TS3A4751

V+14

GND7

TP

J812

RP800

33R

1234 5

678

R80147K

R800100K

C810

100N

TP

J818

U804B74LVC2G125

D2

B2

C1

U803A74LVC2G125

B1C2

A1

C806

100N

C808

100N

TP

J817

R891100K

C805

100N

TP

J820

R816100K

R890

100K

U803C

74LVC2G125

VCCA2

GNDD1

U805A TS3A4751

COM12

COM24

NO23

COM39

NO38

COM410

NO411

NO11

IN113

IN25

IN36

IN412

U804A74LVC2G125

B1C2

A1

C891

100N

U803B74LVC2G125

D2

B2

C1

R810

100R

U802B

74LVC4066

VCC14

GND7

U809C

74LVC2G125

VCCA2

GNDD1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Isolation Voltage Buffering

3V3 Regulator

Virtual COM Port Interface

Isolation

VMCU Voltage Mirror

Power Supply for Analog Switches

J-Link USB Cable

ConnectedDisconnected

PMOS State

OffON

NMOS State

OFFON

V_SW

3.6VVMCU

VMCU_SENSE

VMCUIsolated

The USB VBUS voltage is used to bias these transistors, turning theP-Channel MOSFETs (Q700) off, and the N-Channel MOSFETs (Q701) on.

Level Shift

EXTERNAL BOARD

Connector for externalreference designs boards

VCOM_ENABLE

VCOM_RXDVCOM_TXDVCOM_#RTSVCOM_#CTS

3V3

VMCU_BUF

GND GND

VMCU

GND

3V6_SW

3V6_SW

5V

GND

GNDGND GND

GND

3V3

GND

V_SW

GND

GNDGND

GND

VMCU_BUF

GND

GND

GND

5V

GND

5V

GNDGNDGND

GND

5V

3V6_SW

VMCU V_SW

3V3

VMCU V_SW

GND

VMCU_BUF

GND

3V3

GND

GNDGND

5V

GND

GND

GND

VMCU_EXT3V3

GND

5V

VMCU_EXTVMCU

5V

GND

5V_SW

5V_SW

5V_SW 5V_SW

BC_UART_TXD

BC_UART_RXD

BC_UART_#RTS

BC_UART_#CTS

REF_VCOM_RXDREF_VCOM_TXD

REF_VCOM_#CTSREF_VCOM_#RTS

REF_VCOM_TXDREF_VCOM_#RTS

REF_VCOM_RXD

REF_VCOM_#CTS


REF_BOARD_ID_SCLREF_BOARD_ID_SDA

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A

Tuesday, September 16, 2014 9 10

A3

DDB JNO


<Cage Code>



Power & Misc

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

DDB JNO


<Cage Code>



Power & Misc

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

DDB JNO


<Cage Code>



Power & Misc

R7744K7

C601

10U

U602A TS3A4751

COM12

COM24

NO23

COM39

NO38

COM410

NO411

NO11

IN113

IN25

IN36

IN412 R783

1K

R781

33R

TPJ607

R786

0R

U603

TLV70536

INB2

ENA2

OUTB1

GNDA1

Q701ADMN5L06

2

6 1

C608

1U

R6821K

C606

100N

L780CBF102WB

1 2

M3

C721

100N

U706B

MCP6001T

VDD5

GND2

U661C

74LVC2G125

VCCA2

GNDD1

M2

C609

1U

R62310K

C660

100NC727

100N

C720

10U

R627

0R NM

Q700BBSS84

3

5

4

-

+

U706A

MCP6001T

4

3

1

U600

LP3982ILD-ADJ

IN2

OUT11

GND3

OUT24

FAULT8

CC6

SHDN7 SET

5

GND_HEAT9

U604B

74LVC4066

VCC14

GND7

R78510K

C726

100N

TPJ608

C610

1N

R61010M

C600

100N

U660C

74LVC2G125

VCCA2

GNDD1

R782 10K

C60233N

R60010K

Q700ABSS84

6

2

1

R62247R

R602110K

C725

10U

U602B

TS3A4751

V+14

GND7

U604A74LVC4066

1Y1

1Z2

1E13

2Y4

3Y8

4Y11

2Z3

3Z9

4Z10

2E5

3E6

4E12

D705VESD05A8A-HNH

1 2 3 4 5 6 7 8

9

U660A74LVC2G125

B1C2

A1

R601180K

Q702

BC846BWT1G

1

23

U661A74LVC2G125

B1C2

A1

TPJ606

R621

0R NM

P701

HEADER_2X10_1.27MM_SMD

1 24

86

10

35

97

1213 1411

15 161719

1820

R779 0R

C607

10U

Q701BDMN5L06

5

3 4 R772

1K

TPJ600

M1

U661B74LVC2G125

D2

B2

C1

U660B74LVC2G125

D2

B2

C1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Analog Switch

LPF

I2S DAC

Layout note: Place All components here + C1025on secondary sice

BC_REFCLK

BC_DAC1_OUT

BC_I2S_DATABC_I2S_WSBC_I2S_CKBC_I2S_MCK

BC_CLK_SWITCH_EN

BC_1KHZ_CLKBC_1KHZ_SINE

GND

V_SW

GND

GND GND

5V

GND

GND

GND

V_FILT

V_I2SDAC5V

GND

GND

GND

V_FILT

GND

GND

3V3

1KHZ_SINE_DACI2S_DAC1_OUT

1KHZ_SINE_DAC

I2S_DAC1_OUT

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A

Friday, November 21, 2014 10 10

A3

MRW JNO


<Cage Code>

Monday, June 16, 2014Wednesday, December 03, 2008

Clock & Filter

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


Clock & Filter

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

MRW JNO


<Cage Code>


Clock & Filter

C1026

10UNM

R1094

33R

NM

C1025

10UNM

R103910K

U732A

PCM1781NM

DATA6

SCK5 BCK7

DEMP13 DEMP02 FMT1

TEST9

VOUTR14VOUTL15

ZEROA16

MUTE4

LRCK8

VCOM13

NC10

R1032

9.09K

R1027

11K

R1033

33R

U731B

TS3A4751

V+14

GND7

C1022100N

R1036

0R

U730E

OPA4322

VDD4

GND11

R109210.52K

R1026

11K

R1085100KNM

C1027

10U

NM

C1024

100N

C1028

100N

NM

C10201UNM

C1014

15N

-

+

1

U730A

OPA4322

2

3

1

C101110N

R1093

4.99K

C101210N

C1018

10U

R1081100KNM

R1048100K

U732B

PCM1781 NM

VCC11

AGND12

L1002

CBF102WB1 2

TP930

C1019

100N

C100722N

R1044

0R

R1012100K

C1010

10U

R1079100KNM

C100522N

-

+

2

U730B

OPA43226

5

7

L1004

CBF102WB

NM

1 2

U731A TS3A4751

COM12

COM24

NO23

COM39

NO38

COM410

NO411

NO11

IN113

IN25

IN36

IN412

R1020100K

-

+

3

U730C

OPA4322

9

10

8

R1025

11K

TP935

-

+

4

U730D

OPA4322

13

12

14

R1083100KNM

R1024

11K

R103810K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Control MCU Power & Bypass

Production test:10MHz referenceclock input

TEST_MODE

CTRL_MCU_TXDCTRL_MCU_RXD

USB_ADDR0

USB_ADDR1BOOTLOADER_HALT

PCB_REV0PCB_REV1CLK_SEL

USB_ADDR2CTRL_MCU_TCK_SWCLKCTRL_MCU_TMS_SWDIOCTRL_MCU_TDICTRL_MCU_#TRST

CTRL_MCU_TDO_SWD

AEM_CTRL0AEM_CTRL1AEM_CTRL2AEM_CTRL3

BC_IO2

BC_IO0BC_IO3

BC_IO1

BC_IO4

BC_IO5BC_IO9

BC_IO7BC_IO6

BC_IO8

BC_I2C_EXP_EN

BOARD_REV1

BOARD_REV0

BOARD_REV0BOARD_REV1

CTRLMCU_DEBUG_#RESET

BC_IO[9..0]

BC_DAC_OUT

CTRLMCU_I2S_MCK


DEBUG_TDI_#OEDEBUG_TCK_SWCLK_#OEDEBUG_TMS_SWDIO_#OEDEBUG_MCU_ISOLATE_#ENDEBUG_RESET_#OE

DEBUG_MCU_SW_ENABLE

LED_STATUS_RLED_STATUS_G

DEBUG_DH_SW_ENABLE

AEM_VMCU_ENABLE

AEM_CTRL[3..0]

LED_JLINK

LED_DEBUG_OUT

BC_UART_#RTSBC_UART_TXD


BOOTLOADER_HALT

USBDPUSBDM

DEBUG_TDI_INDEBUG_TMS_SWDIO_INDEBUG_TCK_SWCLK_INDEBUG_#RESET_INDEBUG_TDO_SWO_INDEBUG_EXT_VDD_TARGETDEBUG_EXT_CABLE_ATTACH


CTRLMCU_SPI_MOSI

CTRLMCU_SPI_SCKCTRLMCU_SPI_#CS

BC_UART_#CTS

BC_UART_RXD

GND

GND

GNDGND

GNDADC_VREF

GND

3V3

3V3

3V3

GND GND

3V3

GND GND

3V3

GND

3V3

GND

3V3_SENSE5V_SENSE

3V6_SENSE

EEPROM_WP

CTRLMCU_SPI_MISO

BC_UIF_PB0BC_UIF_PB1

BC_UIF_PB_CON

BC_I2C_EXP_EN

CTRLMCU_I2C_SCLCTRLMCU_I2C_SDA

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A

Wednesday, February 11, 2015 11 10

A3

ANB JNO


<Cage Code>

Wednesday, February 11, 2015Monday, May 12, 2014

Control MCU/HB1/CMCU1

Control MCU

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>



Control MCU

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>



Control MCUC917

100N

TPJ950TPJ951

R901 1K5

PORT A

PORT B

PORT C

U900A Control MCU

PA0 / WKUP / USART2_CTS / ADC123_IN0 / TIM2_CH1_ETR / TIM5_CH1 / TIM8_ETRG2

PA1 / USART2_RTS / ADC123_IN1 / TIM5_CH2 / TIM2_CH2H2

PA2 / USART2_TX / ADC123_IN2 / TIM5_CH3 / TIM2_CH3J2

PA3 / USART2_RX / ADC123_IN3 / TIM5_CH4 / TIM2_CH4K2

PA4 / SPI1_NSS / DAC_OUT1 / USART2_CK / ADC12_IN4G3

PA5 / SPI1_SCK / DAC_OUT2 / ADC12_IN5H3

PA6 / SPI1_MISO / TIM8_BKIN / ADC12_IN6 / TIM3_CH1 [TIM1_BKIN]J3

PA7 / SPI1_MOSI / TIM8_CH1N / ADC12_IN7 / TIM3_CH2 [TIM1_CH1N]K3

PA8 / USART1_CK / TIM1_CH1 / MCOD9

PA9 / USART1_TX / TIM1_CH2C9

PA10 / USART1_RX / TIM1_CH3D10

PA11 / USART1_CTS / CANRX / TIM1_CH4 / USBDMC10

PA12 / USART1_RTS / CANTX / TIM1_ETR / USBDPB10

PA13 / JTMS-SWDIOA10

PA14 / JTCK-SWCLKA9

PA15 / JTDIA8

PB0 / ADC12_IN8 / TIM3_CH3 / TIM8_CH2NJ4

PB1 / ADC12_IN9 / TIM3_CH4 / TIM8_CH3NK4

PB2 / BOOT1G5

PB3 / JTDO / TRACESWO / SPI3_SCK / I2S3_CK [TIM2_CH2 / SPI1_SCK]A7

PB4 / JNTRST / SPI3_MISO [TIM3_CH2 / SPI1_MISO]A6

PB5 / I2C1_SMBAI / SPI3_MOSI / I2S3_SD [TIM3_CH2 / SPI1_MOSI]C5

PB6 / I2C1_SCL / TIM4_CH1 [USART1_TX]B5

PB7 / I2C1_SDA / FSMC_NADV / TIM4_CH2 [USART1_RX]A5

PB8 / TIM4_CH3 / SDIO_D4 [I2C1_SCL / CANRX]B4

PB9 / TIM4_CH4 / SDIO_D5 [I2C1_SDA / CANTX ]A4

PB10 / I2C2_SCL / USART3_TX [TIM2_CH3]J7

PB11 / I2C2_SDA / USART3_RX [TIM2_CH4]K7

PB12 / SPI2_NSS / I2S2_WS / I2C2_SMBAI / USART3_CK / TIM1_BKINK8

PB13 / SPI2_SCK / I2S2_CK / USART3_CTS / TIM1_CH1NJ8

PB14 / SPI2_MISO / TIM1_CH2N / USART3_RTSH8

PB15 / SPI2_MOSI / I2S2_SD / TIM1_CH3NG8

PC0 / ADC123_IN10F1

PC1 / ADC123_IN11F2

PC2 / ADC123_IN12E2

PC3 / ADC123_IN13F3

PC4 / ADC12_IN14G4

PC5 / ADC12_IN15H4

PC6 / I2S2_MCK / TIM8_CH1 / SDIO_D6 [TIM3_CH1]F10

PC7 / I2S3_MCK / TIM8_CH2 / SDIO_D7 [TIM3_CH2]E10

PC8 / TIM8_CH3 / SDIO_D0 [TIM3_CH3]F9

PC9 / TIM8_CH4 / SDIO_D1 [TIM3_CH4]E9

PC10 / UART4_TX / SDIO_D2 [USART3_TX]B9

PC11 / UART4_RX / SDIO_D3 [USART3_RX]B8

PC12 / UART5_TX / SDIO_CK [USART3_CK]C8

PC13 / TAMPER-RTCA2

PC14 / OSC32_INA1

PC15 / OSC32_OUTB1

C912

100N

C904100N

TPJ952TPJ911

R9101R

TPJ954

C916

100N

C90710U

TPJ955

TPJ900

R902 22R

LED903

RED

21

R918 4K7 NM

C910

100N

TPJ901

C914

100N

TPJ902

U900B

Control MCU

PD0 / OSC_IN / FSMC_D2 [CANRX]D8

PD1 / OSC_OUT / FSMC_D3 [CANTX]E8

PD2 / TIM3_ETR / UART5_RX / SDIO_CMDB7

PD3 / FSMC_CLK [USART2_CTS]C7

PD4 / FSMC_NOE [USART2_RTS]D7

PD5 / FSMC_NWE [USART2_TX]B6

PD6 / FSMC_NWAIT [USART2_RX]C6

PD7 / FSMC_NE1 / FSMC_NCE2 [USART2_CK]D6

PD8 / FSMC_D13 [USART3_TX]K9

PD9 / FSMC_D14 [USART3_RX]J9

PD10 / FSMC_D15 [USART3_CK]H9

PD11 / FSMC_A16 [USART3_CTS]G9

PD12 / FSMC_A17 [USART3_RTS / TIM4_CH1]K10

PD13 / FSMC_A18 [TIM4_CH2]J10

PD14 / FSMC_D0 [TIM4_CH3]H10

PD15 / FSMC_D1 [TIM4_CH4]G10

PE0 / TIM4_ETR / FSMC_NBL0D4

PE1 / FSMC_NBL1C4

PE2 / TRACECK / FSMC_A23A3

PE3 / TRACED0 / FSMC_A19B3

PE4 / TRACED1 / FSMC_A20C3

PE5 / TRACED2 / FSMC_A21D3

PE6 / TRACED3 / FSMC_A22E3

PE7 / FSMC_D4 [TIM1_ETR]H5

PE8 / FSMC_D5 [TIM1_CH1N]J5

PE9 / FSMC_D6 [TIM1_CH1]K5

PE10 / FSMC_D7 [TIM1_CH2N]G6

PE11 / FSMC_D8 [TIM1_CH2]H6

PE12 / FSMC_D9 [TIM1_CH3N]J6

PE13 / FSMC_D10 [TIM1_CH3]K6

PE14 / FSMC_D11 [TIM1_CH4]G7

PE15 / FSMC_D12 [TIM1_BKIN]H7

R9122K

R917 4K7 NM

C913

100N

TPJ913

R9150R

C900

18P

R91410K

X900

16MHz

3 1

U900C

Control MCU

NRSTE1

BOOT0D5

OSC_INC1

OSC_OUTD1 VBAT

B2

VREF-H1 VREF+J1

VSSAG1 VDDAK1

VDD_1F7

VDD_2F6

VDD_3F5

VDD_4F4

VDD_5D2

VSS_1E7

VSS_2E6

VSS_3E5

VSS_4E4

VSS_5C2

NCF8

TPJ912

C90910N

TPJ956

C911

100N

TPJ953TPJ910

C915

10U

TP903

C908

10N

R904 22R

C90312P

TPJ909

C90212P

L900CBF102WB

1 2

R9160R

TPJ908

C901

18P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CTRLMCU EEPROM

CTRLMCU SERIAL FLASH

POWER SENSE

ADC referencevoltage


UIF_PB0UIF_PB1

GND

5V

GND

3V3

3V3

GND

3V3

3V33V3

GND

GND

3V3

3V3

3V3

GNDGND

ADC_VREF

GND

3V6_SW

GND

V_SW

GNDGND

GND

3V3 3V3

GND

5V_SENSE

3V3_SENSE

EEPROM_WP

CTRLMCU_I2C_SDACTRLMCU_I2C_SCL

CTRLMCU_SPI_SCK

CTRLMCU_SPI_MOSICTRLMCU_SPI_#CS

CTRLMCU_SPI_MISO

3V6_SENSE

BC_I2C_EXP_EN

BC_UIF_PB0BC_UIF_PB1

BC_UIF_PB_CON

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>



Control MCU Misc

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>



Control MCU Misc

Size

Designed:

Revision

Sheetof

Approved:


Document number

Schematic Title


BOM Doc No:

Page Title

A03BRD5000A


A3

ANB JNO


<Cage Code>



Control MCU Misc

R681100K

C603

100N

C605

100N

R60910K

U902B

M25PX16

VCC8

VSS4

U650A

TS3A4751

COM12

COM24

NO23

COM39

NO38

COM410

NO411

NO11

IN113

IN25

IN36

IN412

D703

LM4040CIM3-3.021

U902A

M25PX16

D5

C6 HOLD

7

Q2

W3

S1

TPJ650

U650B

TS3A4751

V+14

GND7

TPJ651

R6074K7

TPJ905

C611

100N

C90510N

R603100K

R604100K

TPJ652

R651100K

R652100K

C719

10U

R612100K

TPJ653

R650100K

R611100K

C604

100N

R6084K7

C650

10N

R728100R

U601B

24AA024

VCC8

VSS4

TP923

R606100K

U601A

24AA024

SDA5

SCL6

WP7

A01

A12

A23

R605100K

efm8ub1 universal bee stk - silicon labs universal bee stk revision history " # $ % %% &...

Documents