ehsan&totoni& babak&behzad&...

Ehsan Totoni Babak Behzad Swapnil Ghike Josep Torrellas

Illinois-Intel Parallelism Center �2

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•  Increasing number of transistors on chip – Power and energy limited – Single-‐thread performance limited – => parallelism

•  Many opEons: heavy mulEcore, manycore, “SIMD-‐like” GPUs, low-‐power designs –  Intel’s SCC presents manycore


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•  Various trade-‐offs – Performance, power and energy – Programmability – Different for each applicaEon

•  Each architecture has advantages – No single best soluEon –  (But manycore is a good opEon)


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•  Benchmark different parallel applicaEons – On all architectures

•  Analyze results, learn about architecture •  Where does each architecture stand? –  In various tradeoffs

•  What could be probably beZer for future? – Reasonable in all metrics: power, performance… – For most applicaEons


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•  Jacobi: nearest neighbor communicaEon – Standard floaEng-‐point benchmark

•  NAMD: Molecular dynamics – Dynamic scienEfic applicaEon

•  Nqueens: state space search –  Integer intensive


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•  CG: Conjugate Gradient, from NAS Parallel Benchmarks (NPB) – A lot of fine-‐grain communicaEon

•  Integer Sort: represents commercial workloads –  Integer intensive, heavy communicaEon


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•  All codes reasonably opEmized, not extensively! – Programmer producEvity

•  MPI and Charm++ •  CUDA and OpenCL codes for GPU – Reasonably opEmized, same complexity as CPU ones

– Fair apple-‐to-‐apple comparison


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•  MulE-‐core: Intel Core i7 – 4 cores, 8 threads, 2.8 GHz

•  Low-‐power: Intel Atom D – 2 cores, 4 threads, 1.8 GHz

•  “SIMD-‐like” GPU: Nvidia ION2 – 16 CUDA cores, low power, 475 MHz

•  Manycore: Intel’s SCC – 48 cores, 800 MHz


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•  “Single-‐Chip Cloud Computer” (SCC) –  Just a name, not only for cloud –  Experimental chip, for research on manycore

•  Slower than producEon chips, but we can analyze –  48 PenEum cores, Mesh interconnect

•  Not cache coherent, message-‐passing programs


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•  We ported Charm infrastructure to SCC – To run Charm++ and MPI parallel codes – Charm++ is message-‐passing parallel objects

•  No conceptual difficulty – SCC is similar to a small cluster

•  Just headaches of experimental chip – Old compiler, OS and libraries…


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Apps can use parallelism in architecture

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Speedup offsets Power increase

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Speedup and near constant

power

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Jacobi NAMD NQueens Sort 0

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Except CG (fine-‐grain collec5ves)

No change in source code!

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Different power

(Communica5on bound so processors stall)

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not for CG

Apps scalability needed to offset power increase!

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Atom (4 Threads)

Core i7 (8 Threads)

SCC (48 Threads)

ION2 (16 Threads)GPU good for some apps

Regular, highly parallel

Mul5core good for most apps

Even dynamic, irregular, less parallel

SCC beats mul5core on Nqueens

experimental chip!

Low-‐power is really slow!


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GPU and have low

consump5on

Mul5core has high consump5on

SCC has moderate power

More parallelism, less

frequency

High frequency, fancy features

Power nearly same for different apps


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Mul5core is energy efficient!

High speed offsets power

Low-‐power design is not

energy efficient!

Low speed offsets power

savings

SCC is OK

Despite low speed


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•  MulEcore sEll effecEve for many apps – Dynamic, irregular, heavy communicaEon

•  GPU is excepEonal for some apps – Not for all apps – Programmability, portability issues

•  Low-‐power design just low power – Slow! So not energy efficient


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•  SCC: a good opEon – Low power and can run legacy code fast

•  Balanced design point – Lower power than mulEcore, faster than low-‐power design

– No programmability and portability issues of GPU

•  Experimental, slow but can be improved


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•  SequenEal performance, floaEng point – Apps show good scaling on more cores of SCC – Easy with more CMOS transistors –  Interconnect also has to improve with it (sEll easy)

•  Global collecEves network – Like BlueGene supercomputers, low cost – To support fine-‐grain global communicaEons

•  As in CG

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