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Eindhoven University of Technology

MASTER

Hardware development of the Area Segmentation Processor for ESPRIT project *2017 :TRIOS

Smeets, F.G.M.

Award date:1992

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EINDHOVEN UNIVERSITY OF TECHNOLOGY

DEPARTMENT OF ELECTRICAL ENGINEERING

Measurement and Control Section

Hardware development of the

AREA SEGMENTATION PROCESSORfor Esprit Project #2017: TRIOS

by F.G.M. Smeets

M.Sc. Thesis on practical training period

carried out from october 1991 to august 1992

commisioned by prof. dr. ir. A.C.P.M. Backx

under supervision of ir. N.G.M. Kouwenberg

date: 19 august 1992

The Department of Electrical Engineering of the Eindhoven University of Technology

accepts no responsibility for the contents of M.Sc. Theses or reports on

practical training periods.

Hardware development of the

Area Segmentation Processor

forEsprit Project #2017: TRIOS

author: F.G.M. Smeets tvid.nr. : 248996

institute: Technical University Eindhoven

department : Electrotechnical Engineering

professor: prof. dr. ir. A.C.P.M. Backx

coach: ir. N.G.M. Kouwenberg

company: Nederlandse Philips Bedrijven BV edepartment : CFT - ISP - IMI

coach: ing. A.J.M. van Lier

period: october 1991 - june 1992

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Preface

On this place I would like to thank all my colleague students and employees who were of great helpduring my graduate period at Philips CPr. Some of these people I would like to call by name.

First of all a special word of thank to ir. RG. van Vliet, who arranged the graduate work at Philips

CPr. Of course also thanks to ir. N.G.M. Kouwenberg, who toke over the support from mr. van Vliet.

Working under ing. AJ.M. van Lier at Philips was a new experience. Within the required demands,

he gave me complete freedom in my design. If problems occurred, he was always willing to help.

Thanks to this approach I learned a lot about my future profession.

F.G.M. Smeetsaugust 1992

Preface 2


Summary

To graduate at the Technical University Eindhoven, Department of Electrical Engineering a final

assignment has to be fulfIlled. This report describes the graduate work done at Philips Centre for

manufacturing Technology (CFf). The assignment was done at the group Industrial Signal Processing,

Industrial Measurement and Inspection (ISP-IMI).

As part of the ESPRIT project #2017, an in-line PCB inspection system is under development at

Philips CFf. It concerns PCBs with Surface Mounted Technology. In this high-speed 3-D inspection

system a hardware module, called Area Segmentation Processor (ASP) takes care of image data

reduction and distribution. The graduate assignment concerns the hardware design of this ASP.

First the global function of the ASP was looked at. On base of this function the hardware was divided

into blocks. Stepwise these blocks were designed and some of them were already built.

At the moment this report was written, the design of the ASP was almost ready. Only a buffer between

the ASP and the HOST of inspection system has to be added. With this buffer the realised design will

satisfy the requirements.

Summary 3

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Contents

List of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6

List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7

1 Introduction 8

2 ESPRIT project #2017: TRIOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 92.1 Data Processing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 112.2 Area Segmentation 12

3 Area Segmentation Processor 133.1 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 133.2 Global description .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153.2.1 Controller............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153.2.2 Circular buffer 163.2.3 Image handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 163.2.4 Screen handler 183.3 Demands and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19

4 Hardware description of ASP 204.1 Controller 214.1.1 Processor................................................. 214.1.2 Reset.................................................... 214.1.3 Clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 224.1.4 Interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 234.1.5 Chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 254.1.6 Memory.................................................. 264.1.7 Serial communication 274.2 VME-BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 284.2.1 Slave decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 294.2.2 Controller................................................. 304.2.3 Address counter & Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 304.2.4 Memory 314.3 Picture-BUS interface 324.4 Circular buffer 334.4.1 Memory.................................................. 344.4.2 Cross Bar Switch 34

Contents 4


4.4.3 Write/Read block selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35

4.5 Image handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36

4.5.1 Counters ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 364.5.2 Line buffers 38

4.5.3 Multiplexers 41

4.6 Screen handler 424.6.1 Look Up Table 42

4.6.2 Counters.................................................. 43

4.6.3 Multiplexers............................................... 43

4.6.4 Oock generation , 44

5 Software description of ASP 47

5.1 ERM 47

5.2 ASP , , , 47

6 Project status and Conclusions 50

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 51

Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52

Appendix A 531 Hardware design controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 542 EPLD design interrupt handler 55

3 Hardware design image handler 56

4 Hardware design screen handler 575 EPLD design clock generator 58

6 EPLD design divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 59

7 Hardware design circular buffer 60

8 Hardware design PI-bus interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 619 Hardware design VME slave decoder 62

10 Hardware design VME-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 63

Appendix B 641 Timing diagram starting transmission of a screen 65

2 Timing diagram end of line of a screen . . . . . . . . . . . . . . . . . . . . . . . . . . .. 66

3 Timing diagram holding screen for programming XBAR . . . . . . . . . . . . . . .. 67

4 Timing diagram enabling screen after programming XBAR 685 Timing diagram end of burst of a screen 69

Contents 5


List of figures

Figure 2.1

Figure 2.2

Figure 3.1Figure 3.2

Figure 3.3

Figure 3.4Figure 3.5Figure 3.6Figure 3.7

Figure 3.8

Figure 3.9Figure 3.10Figure 4.1Figure 4.2

Figure 4.3Figure 4.4Figure 4.5






Figure 4.18


Figure 4.22


Figure 4.25

Figure 5.1

List offigures

Block diagram of the TRIOS TBI system 9

Block diagram of the DPS 11The ASP 13The relation between pixel, unit and AOI . . . . . . . . . . . . . . . . . . . . . . . . . .. 13Overlapping Areas Of Interest 14Illustration of image to screen unit reduction . . . . . . . . . . . . . . . . . . . . . . .. 14Block diagram of the ASP 15

Principle of the circular buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16

Unique identifier pixel and unit 17

Address generation for writing units 17

Example of line buffer filling 18Address generation for reading units . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19Block diagram of the ASP controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20

Block diagram of the ASP main clock generator . . . . . . . . . . . . . . . . . . . . .. 22

Example of clock stretching 22

Example timing interrupt handler 24CPU address composition 25

Block diagram of the ASP VME-BUS interface 28

Block diagram of the VME-BUS slave decoder and controller 29

Address dip switch 29

Flow diagram of the VME-BUS interface instructions 31Synchronisation of the PI-BUS 32Block diagram of the ASP Picture-BUS interface 33Block diagram of the ASP circular buffer. . . . . . . . . . . . . . . . . . . . . . . . . .. 33

XBAR address composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35

Block diagram of the ASP image handler . . . . . . . . . . . . . . . . . . . . . . . . . .. 36

Control signals of the incoming image. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37Illustration of the image control signals . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37Illustration new write block interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40

Line buffer: address composition 41Illustration of the line buffer switch bit 41Block diagram of the ASP screen handler 42Look Up Table: address composition 44

Screen control signals 44Block diagram of the screen clock generator 45

Clock usage in the screen handler 46

Clock timing in the screen handler 46Flow chart of the ASP software 48

6

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List of tables

Table 3.1

Table 4.1Table 4.2

Table 4.3Table 4.4

Table 4.5Table 4.6

Table 4.7Table 4.8

List of tables

Demands and specifications of the ASP . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19

Interrupt request levels 23

Interrupt handler: external signal description , 24Interrupt handler: possible interrupts 25

Overview of the possible chip selects 26VME-BUS interface: Possible control functions 30

Data bus composition XBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35

Description unit size register 39

LUT address bus control 43

7


1 Introduction

To graduate at the Technical University Eindhoven, department of Electrotechnical Engineering a final

assignment has to be fulfilled. This report describes the graduate work done at Philips Centre for

manufacturing Technology (CFT). The assignment was done at the group Industrial Signal Processing,

Industrial Measurement and Inspection (ISP-IMI).

In electronics industry severe inspection problems are generated by the combination of the increasing

miniaturisation of electronic components and assemblies, the increasing speed of their production, and

ever-increasing demands for high quality. For that reason the aim for inspection with high accuracy

raised. The key objective of the ESPRIT project #2017, called TRIOS is the development of such

inspection systems.

As part of the TRIOS project, an in-line PCB inspection system is under development at Philips CFT.

In this high-speed 3-D inspection system a hardware module, called Area Segmentation Processor

(ASP) takes care of image data reduction. The graduate assignment concerns this ASP and reads as

follows:

Design the (real-time operating) Area Segmentation Processor, which uses prepared

CAD files for selecting the desired image parts (Areas Of Interest) of a PCB and

passes them in an ordered way (screens) to other processing functions.

This report describes the development of the ASP. First a description of the TRIOS project is given.

Then a global description followed by a more specific hardware description of the ASP is given.

Finally the project status is considered.

Introduction 8


2 ESPRIT project #2017: TRIOS

The fulfilled assignment is done within the frame of the Esprit project #2017, called TRIOS. This

project stands for Automated Process and Assembly Inspection by 3-D Vision. Its objective is to

develop a high-speed 3-D inspection system for the electronics industry.

Severe inspection problems are generated by the combination of the increasing miniaturisation of

electronic components and assemblies, the increasing speed of their production, and ever-increasing

demands for high quality. The aim of this project is to provide a solution based on high speed, high

resolution 3-D sensing and data processing.

As TestBed 1 (TB1) of the TRIOS project the Philips department CFf-ISP is working at an inspection

system. The key objective of this project is to develop a 3-D data processing system for in-line testing

of Surface Mounted Technology (SMT) Printed Circuit Boards (PCBs), directly after solder paste

placement, using CAD data to guide the measurement. Inspection is done before soldering, because

it's easier to correct any errors by just removing the paste and applying new paste. Inspection after

soldering would lead to more difficult and expensive corrections. Inspection involves mainly:

o checking solder paste position to be between certain bounds

o checking solder paste volume to be between certain bounds

The layout of the system under development is given in figure 2.1

DATA PROCESSINGSYSTEM

LASER SCANNER

USER INTERFACE

FILE SYSTEM

TRANSPORT SYSTEMPCB

Figure 2.1 Block diagram of the TRIOS TBl system

ESPRIT project #2017: TRIOS 9


First a short overview of the shown blocks will be given.

Laser Scanner:

The laser scanner is a 3-D scanner and provides two parallel datastreams: an intensity and a

height datastream. Height infonnation will be used for volume measurements and intensity

infonnation will be used for position measurements.

TransportSystent:

The transport system moves the PCB under inspection.

User interface:

The User Interface is an interactive program by which the operator communicates with the

machine. It can be used for maintenance purposes, inspection and CAD-file preparation. The

CAD data belonging to the inspected PCB are stored in mass-storage in a compressed fonnat

Here expansion and preparation take place. These latter functions result in a file which

contains the control infonnation (File Systent) needed by the Data Processing System (DPS).

Data Processing Systent:

Here the actual inspection takes place. The DPS processes the height and intensity infonnation

coming from the Laser Scanner, which results in an error listing.

Host:

The Host has the overall control of the system. It provides initialisation data, controls the User

Interface and the Transport System. Moreover it receives the error reports from the DPS and

decides upon these reports what to do with the PCB.

The time-constraints for the system are rather strong (real-time processing of laser images at a pixelrate

up to 5 MHz and with a total image size of over 200 Mpixels), therefore a considerable part of the

system has to be implemented in hardware. Since the graduate work concerned the development of

one of the hardware modules of the DPS, a more detailed description of this part of the system will

be presented in the next paragraph.



2.1 Data Processing System

The development of the DPS is divided into several functional parts. These are shown in figure 2.2.

ii

AREA SBIPBUFFERi

SBIP=:: SEGMENTATION ~l..i.....

~OUTPUT(l-N) r-r" (l-N)

PROCESSOR iIMAGE i

LASER~

AQUISITION~ I IISCANNER &

i FILTERING REAL-TIME Ii ii MODEL DRIVEN

~ SBIPi SHAPEi RECOGNISERiii PRE-PROCESSING SEGMENTATION AND HARDWARE SOFTWARE PROCESSINGI MEASUREMENT FUNCTIONS FUNCTIONSi

Figure 2.2 Block diagram of the DPS

The function of the blocks will be shortly explained:

Image Acquisition & Filtering:

The signals from the laser scanner have to be modified before they can be transported through

a picturebus to the processing functions. Besides electrical preparation of the signals

(buffering, synchronisation, etc.), this also involves a logical conversion. The synchronisation

signals of the laser scanner differ from the signals from the picture busses. The data signals

of the laser scanner are send through a Look Up Table (LUT) for correction purposes. The

resulting signals are called an image.

Area Segmentation Processor:

Since only the pads on the PCBs contain solder paste, only these parts have to be inspected.

Consequently a large part of the image (about 90%) is superfluous. For that reason a number

of rectangular areas (Areas Of Interest, AOIs) is defined off-line. The Area Segmentation

Processor (ASP) will cut (segment) these AOIs out of the image.

In order to have a uniform datastream between the ASP and the buffer, a number of AOIs is

combined into one 512x512 picture, called a screen. When a screen is completed it is

transmitted, together with some additional information (about the composition of the screen).


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SBJP Buffer:

The previous mentioned screens are sent to a buffer of a Single Board Image Processor(SBIP). Here they will remain until the SBIP is ready for processing the screen.

Real-Time Model Driven Shape Recogniser + SBJP:

There are two problems concerning the location of a PCB under the laser scanner:

o PCBs are not always in exactly the same position. A displacement of a fraction of amillimetre can lead to a deviation of several pixels (resolution 25 micron per pixel). This

is a problem because the image data must be related to the CAD data.o PCBs are not always completely flat. A warpage of several millimetres is not uncommon,

but in order to be able to compute the solder paste volumes accurately the copper level (Le.

the height value of the surface of the copper tracks) must be known exactly.

Calculation of the position displacement vector is done by the combination of the Real-TimeModel Driven Shape Recogniser (RTMDSR) and the SBIP, together called Fiducial

Measurement Unit (FMU). First the RTMDSR locates a fiducial, then the SBIP calculates the

difference between the found location and the CAD location. In this way for each AOI avector is calculated.

SBJP (/-N):

The inspection algorithms run on a SBIP, a VME-card for vision purposes developed at eFT

some years ago. Several SBIPs will work in parallel, because the algorithms are fairly slow.Calculation of the actual copper level and other calculations like volume calculation take place

on these SBIPs. When all AOIs are processed an error report, containing all the detected errors

is sent to the systems host computer.

2.2 Area Segmentation

Introduction of the area segmentation has three main reasons:

o limitation of the number of data that has to be stored and processed

o introduction of the possibility to manipulate specific data per area

o distribution of the data over several processing functions

Since the segmentation is done for both height and intensity image (max. 5 MHz pixelrate), it is

obvious that this process has to be implemented in hardware. In the next chapter the Area

Segmentation Processor will be looked at in more detail.


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3 Area Segmentation Processor

In the previous chapter the function of the ASP was exposed. In figure 3.1 the block diagram for the

ASP is given. The ASP segments parts of an image (using CAD data) and sends these parts (combined

in a screen) to other processing functions of the system. Of course the figure gives a far to simple

impression of the ASP. To understand the several parts of the ASP first some defmitions will beexplained.

CAD DATA

IMAGE ASP SCREEN

Figure 3.1 The ASP

3.1 Definitions

An image is divided into units (figure 3.2 A). A unit consists of a square of pixels (e.g. 4x4). If a part

of the image has to be segmented (because it has to be inspected), this part is marked as an Area Of

Interest (AOI). An AOI is a rectangular combination of units and can be described by four parameters:

(X,Y) position, length and width (figure 3.2 B). All parameters are expressed in #Units.

UNIT SIZE<J----------i>

I I

-UNIT

I

II

~::'

\

(A)

Figure 3.2

PIXEL

(8)

The relation between pixel, unit and AO!

Area Segmentation Processor 13


If other shapes than rectangles have to be segmented, this can be done by use of overlapping

(rectangular) AOIs. This is illustrated in figure 3.3. Another possibility would be an Area Of Interest

which overlaps the desired shape completely. In the shown example this would lead to a AOI of 5x5

units.

TO BE SEGMENTED AREA:

2 3

4 5 6

7 8 :::::,:::: 10 11

12 13 :hit::: 15 16:.:.;.;.:.:.:.

17 18 19

AREAS OF INTEREST:

2 3 ::]~:::: 10 11

4 5 6 :::~:1:: 15 16

7 8 iit 17 18 19

12 13 :::1:1::

Figure 3.3 Overlapping Areas Of Interest

A screen is a picture of 5l2x5l2 pixels. This is the maximum size supported by the SBIP. It is also

divided into units, e.g. if a unit is 4x4 pixels then the screen is l28x128 units. A screen will be filled

with the segmented AOIs. An example of an image to screen reduction is given in figure 3.4.

IMAGE

r:,t:,:,:,t::ttttt::=]

I:::::::::::,:,,::\:t:::::\\d

SCREEN

Figure 3.4 Illustration of image to screen unit reduction

Combining AOIs to a screen is done in software. The decision for a fitting algorithm depends on the

available processing time on the ASP. If there is a lot of time available for calculating the composition

of a screen, the filling grade of a screen will be high. If on the contrary a very poor fitting algorithm

is used, a lot of overhead time can be saved. The filling grade of a screen however will be low and

the number of to be transmitted screens will increase.



3.2 Global description

Taking a closer look to the functions represented by figure 3.1 leads to a more detailed representation

of the ASP. First, the incoming image has to be dealt with, so an image handler is necessary. Secondly

the outgoing screen has to be created, which results in the need for a screen handler. A buffer is

required to store the parts of the image until they are sent as a screen. With this in mind the block

diagram is extended to the one in figure 3.5. The blocks will be explained in the next paragraphs.

~VME-BUS

CONTROLLERINTERFACE

1LIMAGE SCREENHANDLER HANDLER

:::::::> PI-BUS :=- ~ CIRCULAR :=- --==:: PI·BUSINTERFACE BUFFER INTERFACE ---......................

Figure 3.5

3.2.1 Controller

Block diagram of the ASP

Besides the image handler, screen handler and circular buffer we can see a controller. The controller

is the main block of the ASP. It consists of a CPU and two memory banks. The first memory bank

contains the program run at the CPU. The second bank contains the CAD data with (X,Y) position,

length and width of the AOIs. At initialisation of the TB I inspection system both memories will be

filled via the VME-bus interface. Tasks of the controller are:

o controlling the image handler

o controlling the circular buffer

o calculating the composition of a screen

o controlling the screen handler

o communication with the master of the system (via VME-bus interface)



3.2.2 Circular buffer

Because units of the incoming image have to be held until they will be sent as a screen, a buffer is

needed. This buffer is chosen to be circular, with eight blocks. The advantages of a circular buffer are:

o read and write side may differ in access frequency

o small amount of memory required

o possibility to access the memory blocks in random order (in contrast to for example a FIFO

memory)

The circular buffer is shown in figure 3.6.

CURRENTWRITE BLOCK

CURRENTREAD BLOCK

Figure 3.6 Principle of the

circular buffer

One of the blocks is used as write block, at the same time the other seven blocks can be used as read

blocks. Because of the sequential incoming image, the units are written in sequential order, until the

write block is full. Then the next block is chosen. A switch controlled by the controller directs the read

and the write address busses. Software has to take care of write and read block separation. When a

screen is sent the units are read in a random order to the correct SBIP buffer block.

3.2.3 Image handler

The image handler is the part of the ASP where the segmentation takes place. On basis of the CAD

data the image handler has to decide whether or not to store a unit in the buffer. For this decision it

has to be known which pixel currently is received from the picture bus. Therefore two counters are

used, a line and a column counter. The counters use the control signals of the incoming image. The

line counter is incremented every new line. The column counter is set to zero at the start of every new

line. Combination of the line and column counter values gives a unique identifier for a pixel.



Dividing the values of the line and column counter by the unit size, gives again a unique combination,

but now for a unit. This is illustrated in figure 3.7.

o 1 2 3 0

o 0 0 0 1o 1 2 3 4

1 2 3 0YMOD unit size

1 1 1 2 DIV unit size

5 6 7 8

0001-+--+--+-I-+--+--+----1I-+_

1 0 1I-+--+--+---t-I-+--+--+---t

2021-+--+--+-I-+--+--+----1h:",,""~,,::~.,f-::~-PIXEL 3,0 IN UNIT 0,2

3 0 3 '!'!'!'i:!;014

Figure 3.7 Unique identifier pixel and unit

From the CAD data the position of the AOIs is known. The processor has to interpret this information

to the current scan line. This is done by coupling an address to each unit in a line buffer. This address

denotes the start address of a unit in the circular buffer (Most Significant address part of the circular

buffer). If a unit doesn't have to be stored the start address will be set to the dummy value zero. The

Least Significant (LS) part of the line and column counter gives the pixel position within the unit. So

they form the LS part of the address of the circular buffer. In figure 3.8 the store address is illustrated.

LINE MODCOUNTER unit size

r==:: MODunit size

~ ~

~COLUMN L..--- L..... DIV I : ~+-

COUNTER unit size =-""""

LINE CIRCULARBUFFER BUFFER

r----Figure 3.8 Address generation for writing units



The line buffer contains also infonnation about selecting a new write block in the circular buffer. This

is handled by the controller with the highest priority, because the incoming image can't be stopped

until the new block is selected.

current--£>scan line

line buffer:

Figure 3.9

i'4--+-+-+--+-+- )

-++-+-+-++"'R'''+''¥4'''+'~I-+-+-~1-+- ) refresh line buffer

~J 42 L~I 0 I=-Example of line buffer filling

In figure 3.9 an AOI is marked. For the current scan line the MS part of the address is zero during

the first shown unit to denote that the four pixels of this unit off this line will be written to the dummy

address. Entering the next unit results in the next line buffer value, 42. The next four pixels will be

stored at address 42-1-0 till 42-1-3, where 1-0 till 1-3 come from respectively the line counter and the

column counter. After (in this example) 4 lines the contents of the line buffer have to be refreshed,

because new units are entered.

3.2.4 Screen handler

The units stored in the circular buffer will be sent to a SBIP. Reading the units in the buffer is donein a similar way as writing. Here also two counters give a unique identifier for a pixel and in

consequence for a unit. Instead off using a one-dimensional line buffer, a two-dimensional Look Up

Table (LUT) will be filled by the controller with the start addresses of the units in the circular buffer.

Because the LUT is a two dimensional buffer, the MS part of both the counters is necessary to address

it. This in the contrary to the line buffer were the MS part of the column counter was sufficient.

Together with the LS part of the counters again a unique buffer address is available. In figure 3.10

the address generation is illustrated.



LUT

Figure 3.10 Address generation for reading units

CIRCULARBUFFER

On the contrary to the image handler here the control signals are not available but have to be created.

For that reason a clock generator is implemented. After the Ltrr is filled by the controller the clock

generator is started. It stops automatically when a new read block in the circular buffer has to be

chosen. When the controller has taken care of this, the generator is enabled again.

3.3 Demands and Specifications

After this introduction a set of demands and specifications can be set. Because the system is aprototype it has to be kept as flexible as possible. For that reason higher demands than necessary are

made. In table 3.1 the demands and specifications are given.

Table 3.1 Demands and specifications of the ASP

IParameter IMIN IMAX IPCB width 30cmPCB length 50 cmpixel size 25 pm

pixel rate image 10 MHz

pixel rate screen 10 MHz 15 MHz

unit size 4x4, 8x8, 16x16, 32x32 pixels

screen size 512x512 pixels



4 Hardware description of ASP

Now the function of the several blocks and the belonging demands are known, hardware can be looked

at in more detail. In this chapter the separate hardware blocks of the system will be described. For

every block at least three aspects will be described:

o functionality

o implementation in hardware

o relation to other blocks

Hardware realisation is done using three kinds of devices. The main part of the hardware is realised

in FAST-TfL. Parts that are not too time critical but very space consuming were programmed in

Erasable Programmable Logic Devices (EPLDs). These devices have been designed, simulated and

programmed with the MAX+plus integrated development package (version 2.71). All other designs

were created with OrCAD Schematic Design Tools (version 3.11). Finally CMOS devices were used

for memories. All designs are included in Appendix A. In the text references to devices in these

designs are made by device number, e.g. U401

First the systems main block, the controller will be looked at. Then the other blocks will be examined

in an order related to the flow of the image data.

A 0 LA LO

.11 II

INT I..!!!b..,.,~INTERRUPT ,---v

HANDLERLATCH

PROCESSOR

~~

.........----_...

I! ~: CLOCK RAM

~ ~;GENERATOR BLOCK DUART

i;i

I [ RESET I ;::::::::: ~RAM CHIPBLOCK

IISELECT 1;

1

!

~. .L __•..•.••................•.......................•.•......•..............•.....•....__ __•..........~

Figure 4.1 Block diagram of the ASP controller

Hardware description ofASP 20


4.1 Controller

In the global description of the controller the CPU and two memory banks were already mentioned.

In figure 4.1 also other functional blocks are shown. In the next paragraphs these blocks will be

discussed. The hardware designs of the controller can be found in appendix A, sheet 1.

4.1.1 Processor

The Cypress RISC CY7C611 Integer Unit for Embedded Control (25 MHz) is chosen as CPU of the

ASP (UI01). This CPU is software compatible with the SPARC standard, for which there is a

development system at the CFf department.

The CPU is not a "full processor", for example an interface to a co-processor is missing. However,

for the control purposes the CPU is used for, all these extra options are not necessary. Also address

(0..23) and data (0..31) busses are sufficient. A data bus of 32 bit introduces the following datatypes:word (32 bit), half word (16 bit) and byte (8 bit).

Most outputs of the CPU must be latched externally, before they can be used. For that reason the

address and data bus are latched on the rising edge of the system clock (UI13 - UI17, 74F574). Also

some processor control signals are latched on this edge (U106, U107).

4.1.2 Reset

To reset the ASP (and the controller itself), a reset button is implemented. The reset signal should be

kept valid for at least 8 processor clock cycles (8 x 40 ns =320 ns) to reset the CPU. Other blocks

also will be reset by this signal. A monostable multivibrator (UI08, 74121) is used to hold the signal

for a relative to big time. The reset pulse width is set to:

= C1 0 Ru " ln2=22 J,LF Q 47 to 0 ln2= 0.72 s

(4.1)

The 74121 monostable multivibrator is only available in standard TTL. To achieve the better

propagation delays of FAST-TTL (factor 10 lower), two fast inverters are placed at the outputs of the

multivibrator, to create the RESET and RESET* signal.

Hardware description of ASP 21


4.1.3 Clock generator

This block provides the ASP with all clock signals. The clock used in the ASP is set to 25 MHz. This

frequency is the maximum frequency supported by the CPU. The base to all clock signals is a 50 MHz

oscillator. The clock is created by dividing the output of a the oscillator by toggling a flip flop.

When using a fast CPU to access relative slow devices, it is necessary to insert wait states. Nonnally

this is done by sending a Memory HOLD (MHOLD) signal to the CY7C611 CPU. This will freeze

the processor pipeline. However, there is an easier way to insert wait states. By delaying the rising

edge of the CPU clock, it is possible to let the CPU run slower, in order to match the CPU cycle time

with the devices access time. For that purpose a clock stretcher is introduced (figure 4.2).

50 MhzOSCILATOR

STRETCHCONTROLLER

HClK

DCLK

SClJ(

Figure 4.2 Block diagram of the ASP main clock

generator

Like said before the 50 MHz oscillator is divided. This results in the free running clock (FCLK). After

division only a delay correction is made. This to compensate the delay of the gate that controls the

stretched clock (SCLK). This is the same clock as the free running clock, but now with the possibility

to stretch it for several clock pulses. In figure 4.3 an example is given.

FCLK

SCLK

LA23

2 stretches

Figure 4.3 Example of clock stretching



Stretching is achieved by setting the latched address lines LA[20..22] of the CPU to 7 minus the

required number of wait states. This value will be loaded into the counter of the stretcher. The counter

will count upwards to 8 before the next rising edge of SCLK. Because this principle does not work

for zero wait states the latched address line LA23 is used to enable the wait state generator. In this

way the address lines 20 to 23 (the first digit of the hexadecimal address of the CPU) determine the

number of wait states as follows:

{

[0,,7] - no clock. stretchlng

LA[20•.23] € [B,,£] - clock. stretching (15 - #stretches)

[FJ - not allowed

(4.2)

Besides FCLK and SCLK two other clocks are generated. The data clock (DCLK) is the delayed

SCLK. The purpose of this delay is to achieve an already steady address at the moment data arrives

at a block. The half frequency clock (HCLK) is used by the screen handler. This is a 12.5 MHz clock,

realised by again dividing the already divided 50 MHz (toggling another flip flop).

4.1.4 Interrupt handler

The use of interrupts increases the efficiency of the system. Without interrupts the processor must poll

each peripheral to determine when it is ready for service. The time spent polling cuts down available

processing time and polling is unnecessary when the peripheral devices are not ready for service. With

interrupts, the peripheral device informs the processor when it's ready; thus no time is wasted.

Interrupts also provide a faster response to service requests from a peripheral.

The CY7C611 CPU provides vectored interrupt handling. The state of the Interrupt Request Level

(IRL) inputs defines the external interrupt level. The indication of these inputs is given in table 4.1.

Table 4.1 Interrupt request levels

IRL[3..0] status

0000 no external interrupts pending

1111 non maskable interrupt pending

others maskable interrupt pending



External hardware should ensure that (asynchronous) interrupts are latched and prioritised, before they

are passed to the CY7C611. Logic should also keep the IRL inputs stable until an interrupt is taken

and acknowledged. Otherwise there could be some question as to which interrupt the INTerrupt

ACKnowledge (lNTACK) is responding to.

An Erasable Programmable Logic Device (EPLD) was used for implementation of the interrupt handler

which satisfies the previous demands (latching, giving priority and holding). The implemented

schematic of this EPLD can be found in appendix A, sheet 2. In table 4.2 the external signals of the

handler are summarised.

Table 4.2 Interrupt handler: external signal description

IPin Name IDescription I~:l IActive

ICLK Processor Clock Input rINT[1..5] Peripheral Interrupt Input r

INTACK Interrupt Acknowledge Input HIGH

IRL[O..3] Interrupt Request Level Output

To each input called INT, a peripheral can be assigned. The higher the number of INT the higher the

priority of the generated interrupt. An example of the timing is illustrated in figure 4.4.

CLK

INT5

INT4

INT3

INT2

INT1

INTACK

IRL[O..3)

---+---...;.---+---+----.JrL--...;.------:---+----

--;-__--+-__-+---__+----'11'-+1__-;-__-+-__+--__

-+---...;........Jnl.----+-__-+-__i---_-+__-+-__+-__

-+_--"--0--i:__--+-----.JX'---+-__--+-_-"----+--__+--_---<---'G

Figure 4.4 Example timing interrupt handler



Initially there is no interrupt request pending, so IRL indicates zero. At a given moment INTI is

asserted by the peripheral assigned to this interrupt level. After a rising edge of CLK this interrupt

request is taken and put through to the processor (IRL indicates request level I). From then on this

request level is held until INTACK resets the hold status of the interrupt handler. So the requests

placed by peripheral 3 and 4 don't influence the IRL during this time. After the rising edge of CLK

the next interrupt request will be put through to the processor. Although the peripheral assigned to

level 3 interrupted earlier, this will be request level 4, because of the higher priority of this interrupt.

After servicing the peripheral assigned to level 4, the peripheral assigned to level 3 will be serviced

(if no other higher prioritised requests were placed).

In table 4.3 the possible interrupts are given. The meaning of these interrupts will be explained later.

Table 4.3 Interrupt handler: possible interrupts

I Input I IRL IName IDescription IINT5 5 NEXT_SCR next screen can be sent

INT4 4 LBll reprogram circular buffer write address

INT3 3 LLUTII reprogram circular buffer read address

INTI 2 EOB screen burst is sentINTI I NEXT_LB line buffer switched, fill next

4.1.5 Chip select

Address lines 20 to 23 of the CPU always denote the number of wait cycles. Address lines 16 to 19

determine the selected chip (the second digit of the hexadecimal address). The chip select signals are

created with two l-of-8 decoders (U120 and UI21). LAI9 enables one of the two devices. LAI6 to

LAI8 determine the desired output. In this way 16 chip select signals are possible. In table 4.4 the

possible chip selects are given, the meaning of these selections will be explained later.

123222120119181716115141312111098765432 1 o~

l L ~AVAILABLECHIP ADDRESS

CLOCK STRETCHING

Figure 4.5 CPU address composition



Table 4.4 Overview of the possible chip selects

IStart Address IDescription IWmt

IStates

00 0000 RAM (program) 001 0000 RAM (CAD) 082 0000 DUART 7D3 00 00 Crossbar 1 2D4 00 00 Crossbar 2 2E5 0000 LUT 1

06 0000 toLUT 0

07 00 00 send screen 008 0000 enable screen 0

E9 0000 line buffer 1

OA 00 00 unit size register 0

The composition of the CPU address is always the same for the lines 16 to 23. This is again illustrated

in figure 4.5. Address lines 0 to 15 differ per chip and will be looked at later. After a reset the

processor will start to execute instructions fetched from memory location O. Here the RAM with the

program is located.

4.1.6 Memory

As memory belonging to the CPU use is made of four cache data RAMs CY7C157. These are

16Kxl6-bit CMOS static RAMs specifically designed as cache memory for the used CPU. They

contain a self timed write mechanism, which simplifies the design. Two of the RAMs (32KxI6-bit)

are used as program memory and two (32KxI6-bit) as CAD memory. The infonnation which has to

be kept in this CAD memory is sorted per AOI. For every AOI the following values have to be stored:

X-position of the upper left corner of the AOI in units

Y-position of the upper left corner of the AOI in units

Length of the AOI in units

Width of the AOI in units

Hardware description ofASP

2 byte

2 byte

1 byte

1 byte

--+6 byte

26


These six bytes can be stored as three half words, where the last half word contains length and width.

Two CY7Cl57 RAMs have 32K half words available. This puts a maximum to the number of AOIs

that can be segmented, during an inspection:

MAX IAOJ =r3~1 = 10922

For a 30x50 cm PCB this might not be sufficient. Two possible solutions can be used:

(4.3)

o placing extra memory

o placing a communication buffer between ASP and HOST (as part of VME-bus interface)

The first option would still put a limit to the number of to be segmented AOIs. The second option

however, would make the system more flexible. During operation of the ASP, new CAD data could

be fetched and placed in the already existing CAD memory. The choice is made for the last option

(not implemented yet). If this memory is made dual ported, another advantage appears. Because

information about screen compilation has to be send to the HOST, this can be done via the same

memory.

Storing the CAD data as half words, requires a memory that is half-word accessible. This is

accomplished by several logic gates. The memory is not byte accessible, because then the required

logic would introduce to big a delay, for correct access to the memory. The CPU signals LSIZE[O.. I]

and LA[O.. I] indicate which part of the data bus is currently used.

The program memory is only word accessible. Because all RISC instructions are 32-bit instructions

this will not lead to any problem.

4.1.7 Serial communication

For development (debugging) purposes, a serial communication controller is provided at the ASP. The

main device in this controller is the SCN68681 Dual Asynchronous Receiver/fransminer (DUART,

UI25). RS232 protocol is used to communicate with a terminal. On the RISC CPU then a debug

monitor can be used, to find bugs in hard- or software.

The serial communication controller is optional, which means that it is not necessary for correct

functionality of the ASP. After the prototype is found to be correctly working, the controller does not

have to be implemented any more.



4.2 VME-BUS interface

The task of the VME-BUS interface is to provide communication between the ASP controller and the

HOST of the system, via a VME-BUS. Tasks of the interface are:

o downloading program data to the program RAM

o downloading CAD data to the CAD RAM

o handling interrupts between ASP and HOST

o transferring CAD data from HOST to ASP during operation

o transferring screen composition information from ASP to HOST

In figure 4.6 the block diagram of the VME-BUS interface is given. In the next paragraphs these

blocks will be looked at. Hardware realisation of the interface is given in appendix A, sheet 9 and 10.

LATCH

LATCH

MEMORY

ADDRESSCOUNTER

---- .., L..__

!BAMrO.51

~SLAVE DECODER

HiBAI1..151 ~ CONTROLLER

i··· D • D •••••••••••••••••••••• __ ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• •••••••••• __ ··································1: ::SOO.15 i

Ai

t __ __ .__ :

Figure 4.6 Block diagram of the ASP VME-BUS interface

The TB 1 inspection system finally will consist of a VME rack with the several functional cards. The

ASP is built on a VME prototyping board, PG2750. This board is a high performance general purpose

VME-BUS interface module. Using this board means that the knowledge about the sophisticated details

of VME-BUS arbitration and interrupt handling can be reduced to a minimum. Because the ASP is

a complete slave compared to the HOST, a lot of the utilities provided on this prototyping board are

not used. In a final design this prototyping board should be minimised to the necessary devices.



4.2.1 Slave decoder

Every card in the inspection system must have a unique address, to avoid bus conflicts. The mentioned

prototyping board has no address decoder of its own. For that reason a decoder is added. This decoder

checks if the address set on the bus is the address assigned to the ASP. In figure 4.7 the block diagram

of the realised decoder is given.

AM[O..5] BA[11 ••15] BA[1 .•3] BAS sRiW

II

f··aa _- --- -- ----- --- ----.

SHORT I/O ADDRESSADDRESS SELECTOR

1tCONTROLLERCOMPARATOR COMPARATOR

~CONTROL'T" SIGNALS

'----_......L••••••••••••••••••• __ ••••••••••••••••••• •••••••••• ••••••_••••••••••• •• __ ._•••••••••••• •••• _••••••••••••• •••••••••••••:

Figure 4.7 Block diagram ofthe VME-BUS slave decoder and controller

To check if the ASP is addressed, two comparisons have to be done. First the Buffered Address

Modifier (BAM[0..5]) is compared with the a fixed value. This value stands for short I/O access. With

a jumper (11) the decision can be made between supelVisory (2D hex) or non-privileged (29 hex) I/O.

If the address modifier satisfies the short I/O criterium, a second comparator is enabled. This one

(U902) compares the Buffered Address (BA[l1..15]) with the value set on dip switches. If this

comparison indicates equal, the controller is enabled. In figure 4.8 the dip switch is shown. Switch

number six is not used. Switch I to 5 are compared with respectively BAI5 to BAIL For example

if the switches would be set as indicated, the software address to select the ASP would be 03 60 00.

The first two digits (03) denote the address space of short I/O access. The next two digits are set by

the switches and the last two digits are free for indication of the desired function.

123456O!lli6100nIIJOOElem--OFF--

Figure 4.8 Address dip switch



4.2.2 Controller

The controller takes care of creating the correct signals for proper operation of the counter, latches,

memory and CPU. When the controller is enabled, it uses the three LS bits of the address bus

(BA[1..3]) to determine the function to be executed. This is done with two 1-to-8 decoders (U904,

U905), one enabled during read cycles, the other during write cycles. The possible functions are given

in table 4.5.

Table 4.5 VME-BUS interface: Possible control functions

IBA[3..l] IRead IWrite I000 read counter write counter001 write LS half word program

010 write MS half word program

011 write LS half word CAD data

100 write MS half word CAD data

101 disable CPU

110 enable CPU

It would lead to far to take a closer look at the hardware of the controller. All the desired control

signals where created only using logic gates, flip flops and digital delay lines.

4.2.3 Address counter & Latches

During initialisation of the TB1 inspection system, the ASP has to be loaded with the program for the

CPU. Also CAD data has to be loaded. Because the VME address bus does only indicate card address

and desired function, before every data write cycle, a write cycle would be necessary to set the store

address. Besides that the VME data bus is 16 bit wide on the contrary to the ASP program RAM

which is 32 bit orientated. For writing one 32 bit word this would lead to another extra write cycle,

which makes three together.

To reduce the number of write cycles from HOST to ASP, an address counter is implemented in the

VME-BUS interface (U1011 - U1014). During the first write cycle the start address of the data to be

written into the RAM is preloaded into this counter. Then the LS 16 databit are written. These will

be latched in the interface. Next step is writing the MS 16 databit to the ASP. These also will be



latched. The contents of both latches (Ul007 - UI01O) thus fOlm the data, which has to be stored at

the address indicated by the address counter. After writing the MS part, first the data is automatically

written into the RAM and then the counter is automatically incremented. Using this principle brings

the number of write cycles back from 3 to 2 per 32 bit data.

To avoid bus conflicts, during RAM access the CPU must be taken of the bus. This also should beestablished by the HOST. Initialisation of the ASP will then look as indicated in figure 4.9.

.,DISABLE CPU

IWRITE START ADDRESS TO COUNTER

WRITE LS PROGRAM DATA.,WRITE MS PROGRAM DATA

WRITE START ADDRESS TO COUNTER

WRITE LS CAD DATA.,WRITE MS CAD DATA

ENABLE CPU.,

Figure 4.9

4.2.4 Memory

Flow diagram of the VME-BUS interface instructions

The memory in the VME-BUS interface has a twofold function. In both situations the memory is only

used as temporary storage between ASP and HOST. The functions are transferring CAD data from

HOST to ASP and screen composition information from ASP to HOST. At the moment of writing this

report the memory was not implemented yet. Use of the memory will be interrupt driven.

When during operation, the processor goes out of CAD data this is reported to the HOST by means

of an interrupt called SEND_CAD. The HOST will write a fixed number of CAD data to the memory.

From here it is placed to the CAD RAM by the CPU.

When the processor has to send a screen, screen composition is written to the memory and the LUT

is filled. Then an interrupt called NEXT_SCR signals to the HOST that a screen can be send. The

HOST will then read the memory and pass the information to the selected SBIP.



Introduction of this memory will lead to some changes in the hardware of the controller of the

VME-BUS interface. All other blocks however remain the same.

4.3 Picture-BUS interface

The Picture-BUS interface consists of two parts. The first part is used to receive the incoming image.

the second part to send the outgoing screen. Its function is synchronisation of the signals respectively

between the Image Acquisition Card and ASP and between ASP and a SBIP. Synchronisation is

illustrated in figure 4.10.

CLKB

DATAB

BUS

DATA A

~CL,"",OC"",K'-- ~"I DRIVER ~-····r"·

I_.....1

CLKA=CLKB

DATA A (LATCHED)

DATAB -+-_-+-_--:->1,---1-+--I------h!l-

Figure 4.10 Synchronisation of the PI-BUS

In the figure three parts can be distinguished. At the left the transmitting part, in the middle the

picture-BUS and at the right the receiving part are shown. At the transmitting part a clock signal is

set onto the bus using a driver. This signal is received again by both transmitting and receiving part.

This leads to both parts having the disposal of the same clock, because for both parts the delay from

CLOCK to CLK is the delay of a driver, the bus and a receiver. If the delay of driver, bus and

receiver stays within the clock period, data clocked at the transmitting part, will be clocked at the

receiving part, one clock cycle later.

The hardware design of the Picture-BUS interface is given in appendix A, sheet 8. The block diagram

of the interface is given in figure 4.11. On the contrary to figure 4.10 here two latches are clocked,

before data is put onto the bus using drivers. The reason for this is explained later, when the screenhandler is looked at.



•................................... ------ .._---_ .. -.._-_ __.__ _--- .I 0..15!

RECEIVER 1-__"-- ""IM'-'C""'LK'i-!..

DRIVER

SC 0..15!

SCR CLK!

:04•••••••••••••••• 04 ;

Figure 4.11 Block diagram of the ASP Picture

BUS interface

4.4 Circular buffer

The AOIs will be stored in the circular buffer until the screen to which they belong to is sent. The

composition of the circular buffer is given in figure 4.12. The hardware (appendix A, sheet 7) will be

explained in the next paragraphs.

.- ' - _---- _----------.- - __ .•....

:IMO..15

---_ _----_ _-- _-----_ -.-.-- _--_._--------- ..

!SCRn.1S :

LA LD

LA LD

WRITE BLOCKSELECT

::1IMAGEJHANDLER

!Sat:EN:HANDl£R

,:,:!!j!

I,!

I "'", '~,~' !

I I

L.......... 1

Figure 4.12 Block diagram of the ASP circular buffer



4.4.1 Memory

Because the infonnation per pixel consists of eight bit height and eight bit of intensity data, the

circular buffer should be 16 bit accessible. The choice is made to use eight l6Kx32 Static RAM

modules with separate I/O (CYM1822). Although these are 32 bit memories, they can be addressed

per 16 bit by means of chip select inputs. If /CSL is the inverted signal of /CSU the demand is

fulfilled.

Eight l6Kx32 memory modules put a maximum to the number of pixels (units) that can be stored in

the circular buffer of the ASP. In equation (4.4) this number is given. Consequences of this limitation

will be discussed in the chapter about the screen handler.

MAX #pixels = memory capacity#bits peT pixel

4.4.2 Cross Bar Switch

= 8 " 16K" 32 bits = 256K ixels16 bits peT pixel P

(4.4)

The input data busses of the memories are tied together. This means that every block has the disposalof the image data. Because this data have to be stored only in one of the blocks, the write address

(created by the image handler) has to be set to the correct block. Of course also setting the correct read

address (created by the screen handler) is part of this problem.

Direction of the address busses is achieved using crossbar switches (XBAR) L64270. Use is made of

two of these XBARs because the eight memory blocks have to be provided with 14 address inputs plus

two chip select inputs. This makes 8x(l4+2) = 2x64 outputs necessary.

The L64270 is a 64 to 64 crossbar switch in which any of the 64 outputs can be connected to any of

the 64 inputs without any blocking constraints. In addition any output can be set to a constant value

or put in a high impedance state. Each output of a XBAR has an 8-bit control word associated with

it. This control word specifies the behaviour of each output. Control data can be loaded into theloading latch without disturbing the operation specified in the active latches. Setting the input

BNKLDI high transfers data from all of the 64 loading latches to the 64 active latches.

In hardware (appendix A, sheet 7) the control latches of the XBAR can be written by the CPU. The

CPU is interrupted by the image or screen handler when it has to reprogram the XBARs. Then the

CPU reloads the XBARs during the time that several incoming units will be written to the dummy

address zero. This demand is necessary because it takes several processor clock cycles before an

interrupt is granted. Furthennore it takes at least 8 clock cycles to reprogram 8 outputs of a XBAR.



4.4.3 Write/Read block selection

Besides directing the address busses, the write enable and output enable inputs of the memory modules

have to be provided. Parallel to the address bus also the write enable has to be set to the correct block.

The write block selector has to ensure that only one of the blocks at a time can be written. This is

achieved by means of a l-of-8 demultiplexer (U714). In a register, which is written together with the

XBARs, the desired write block address can be written. The registers outputs fonn the address of thedemultiplexer. In this way the write enable is set to the correct block.

The same principle is used for avoiding bus conflicts at the output data bus of the memory blocks.

Only one of the eight blocks is allowed to output data at the same moment. In the same register asfor the write block selection, also the read block address can be written. The registers outputs fonn

again the address for a l-of-8 decoder (U713).

12322 21 20119 18 17 16[15 14 13 12 11 10

lNOTUSED

918 7 6 5 4

lREGISTERADDRESS

3 2 w::iIlNOTUSED

Figure 4.13 XBAR address composition

Writing to the XBARs is accomplished by setting the chip select to XBARI or XBAR2. In figure 4.13the address composition of the two XBARs is given. The meaning of the data lines is given in

table 4.6. Every write cycle to a XBAR the write block and read block (LD[8..13]) should be valid.

Table 4.6 Data bus composition XBAR

Data bus Written to:

LD[O..7] addressed XBAR registerLD[8..1O] read block register

LD[ll..l3] write block register



4.5 Image handler

In figure 4.14 the block diagram of the image handler is given. In the global description the counters

and line buffers were already mentioned. The hardware of the blocks (appendix A, sheet 3) will be

discussed in the next paragraphs.

.....--_ __ _-_ .LA[2..13) LOrO..11)

IMAGELINE

COUNTER

IMAGECOLUMNCOUNTER

LINEBUFFERSELECT

LINEBUFFER A

LINEBUFFER B

IM.LCO..4

IM.CCO..4

LB 0..10

LBBO..10

t __ __..1

Figure 4.14 Block diagram of the ASP image handler

4.5.1 Counters

The counters give a unique identifier for every pixel. They are controlled by the control signals of the

incoming image. In figure 4.15 these control signals are given. IMage LIne Enable (1M_LIE) is high

during a line of the image. IMage PIcture Enable (1M_PIE) is high during the complete image. If

1M_PIE and 1M_LIE are high, the rising edge of the clock denotes data valid of a pixel. The first pixel

is valid on the rising edge of 1M_PIE and the last pixel is valid one rising edge before the falling edge

of 1M_PIE. The last pixel of a line is valid one rising edge before the falling edge of 1M_LIE.



Figure 4.15 Control signals of the incoming image

Besides 1M_PIE and 1M_LIE also WINdow PIE (WIN_PIE) and WINdow LIE (WIN_LIE) can be

used as control signals of the image. These signals denote a window in the image. This might be

useful when only a part of the image is of interest. The control signals are illustrated in figure 4.16.

J L 1M LIE~WiN_LIE

Figure 4.16 Illustration of the image control signals

The column counter is reset with the 1M_LIE signal and incremented with the IM_CLK signal. This

means that after 1M_LIE goes high the counter starts counting. At the end of a line 1M_LIE goes low

again and in consequence the column counter will be set to zero again. The line counter is reset with

the 1M_PIE signal and incremented with the 1M_LIE signal. This means that after 1M_PIE goes high

the counter starts counting. At the end of an image 1M_PIE goes low again and in consequence the

line counter will be set to zero again.

In the previous section one also can read WIN_PIE and WIN_LIE instead of respectively 1M_PIE and

1M_LIE. The clock signal IM_CLK is the same in both cases. The choice for one of the control sets

is made in software and can be written in a register by the CPU during initialisation of the ASP (see

next paragraph).



The minimal size of the counters is calculated in equation (4.5) and (4.6).

MAX column counter value = MAX PCB widthMIN pixel width

= 30 10-2

m = 120002S 10~ m

(4.5)

MAX line counter value = MAX PCB lengthMIN pixel width

= SO 10-2 m = 2000025 10'"" m

(4.6)

A maximum of 12.000 means that a 14 bit column counter is necessary (214 =16384). This is realised

using two 8 bit binary counters (U303, U304). For the line counter a 15 bit counter would be required

(215 = 32768). However, from the line counter only the five LS bits are used to indicate the pixels

position within a unit (max. unit size is 32, 25 = 32). For that reason only one 8 bit binary counter

(U302) is necessary to implement the line counter.

4.5.2 Line buffers

In the line buffer the start address of a unit is coupled to the currently incoming unit. This address

denotes the start address of a unit in the circular buffer (if the unit is superfluous, the address is set

to zero). Together with the LS bits of the line and column counter (these denote the place of the pixel

within the unit), the store address is created.

The line buffer is addressed by the output of the column counter, divided by the unit size. Because

the unit size is at least 4x4, the two LS bits of the column counter are not used. If the unit size is 8,

16 or 32 respectively the 1, 2 or 3 LS bits of the line buffer address have to be nullified. This is

achieved using AND gates (U031, U032). These gates are controlled by the contents of a register.

During initialisation the CPU has to initialise this register (U308) which contains information about

unit size and mode of operation. When writing to the unit size register, the 16 LS bit of the address

are not used. In table 4.7 the possible contents are given.

The LS bit of the line buffer address is nullified if UNITI is set high in this register (set by LD2). The

second bit if UNIT3 is high and the third if UNIT4 is high.

The mode written in the register is used as select input for a multiplexer (U301). This multiplexer is

dependant of the mode transparent for the image control signals or for the window control signals.



Table 4.7 Description unit size register

ILD[5..0] IDescription IxOOOll unit size 4x4

x 0 0 1 1 1 unit size 8x8

x 0 1 1 1 1 unit size 16x16

xlIII 1 unit size 32x32

Ox xxx x nonnal modelxxxxx window mode

In the global description only one line buffer was mentioned. In the block diagram of figure 4.14

however two line buffers are shown. To understand the choice for two buffers, several options of line

buffer filling have to be examined.

o fIlling after the last pixel of a unit

o filling between the last line of units and the first line of the next units

o filling a second buffer during the use of the first one

Filling after every last pixel of a unit would mean, that the CPU during the last line of the current unit

continuously would have to poll the column counter, to check if filling is already allowed. A lot of

processing time would be spilled in this way. Also the use of interrupts would be too time consuming.

For that reason one could choose for the second option, where filling is done after the last line of the

current units. Here however, too little time is available to fill all positions in the buffer, before the first

pixel of the next line is valid (address bus should be cleared in time). The only choice left is the use

of two buffers. Here one buffer is in use, while the other can be fIlled. In this way the CPU can fill

the buffer using its processing time 100%.

In equation (4.7) the minimal needed size of a line buffer is calculated.

MIN line buffer size = MAX PCB widthMIN unit size " MIN piul width

30 10-2 m=-----4 o2S 10-t5 m

=3000

Hardware description of ASP

(4.7)

39


At least 3000 memory locations means that a 4K memory is necessary. The width of a line buffer

word is detennined by the 16K memory blocks of the circular buffer, which require 14 address bits

plus one bit to detennine the lower or upper 16 bit of a word in the block. These 15 bit are fonned

by the LS bit of the line and column counter and the output of the line buffer. The maximum available

line buffer width then should be eleven, because from both counters at least 2 bit each are used (4x4

unit size). Finally one bit has to be added for interrupt purposes. This bit has to be set if the write

block in the circular buffer has to be reprogrammed. Then an interrupt is given to the CPU.

Use is made of three 4Kx4 Static RAMs with separate I/O (CY7CI72A) per line buffer. In this way

the 4Kx12 line buffer is created. Because the input data always comes from the CPU and the output

data always goes to the circular buffer, separate I/O is used. Otherwise at the output again switch logic

would have been necessary.

line buffer value -- ~_--,1=2 ---=0'--__----'0 ----'-'13:........-

interrupt bit --~ ° 1 ° °t

interruptrequest

tXBAR

reprogrammed

Figure 4.17 Illustration new write block interrupt

In figure 4.17 interrupting the CPU for reprogramming the circular buffer (XBAR) is illustrated. In

the worst case a unit is only valid during 400 ns (frequency image clock 10 MHz, 4 pixels per unit).When the interrupt bit in the line buffer goes high at least 4 processor cycles pass before the interrupt

is granted. Then at least 16 outputs of a XBAR have to be reprogrammed. This again takes at least

16 processor cycles, which makes a total of 20 x 40 ns = 800 ns. After programming the last output

a propagation delay will even enlarge the required time before the new address path is correctly set.

In this case this would mean that at least three line buffer fields have to be zero to achieve correct

reprogramming of the XBAR. Of course the number of fields in the line buffer that have to be zero

is different for every configuration (frequency incoming image, unit size).


Nederlandse Philips Bedrllven B.V.Centre for manufacturing Technology

4.5.3 Multiplexers

The use of two buffers introduces the need for a switch to each of the two buffers. This switch has

to direct the CPU address bus to one buffer, while the column counter is switched to the other. The

two switches are created using six quad-2-input multiplexers. The outputs of the first switch (U31O

U312) are connected to the first line buffer. The other (U313-U315) to the second buffer. The select

input for all six devices is the same, but the input busses of the first switch are swapped compared tothose in the second switch. In this way always one of the switches is connected to the CPU and one

to the column counter. Another multiplexer (U307) is used to switch the write signal of the CPU to

the correct line buffer. Because nullifying of the address lines of the line buffer is achieved after the

multiplexers, writing to the line buffers by the CPU is only necessary to addresses, which can bedivided by the unit size. The composition of the address is given in figure 4.18.

123 2221 20119 18 17 16~13 12 11 10 9 8 7 6 5 4 3 2 D:::2l

LL l NOT USED

COLUM ADDRESS: 0 STEP (UNIT SIZEl4)

NOT USED

Figure 4.18 Line buffer: address composition

Like said before the select input for all the multiplexers is the same. This switch bit is created using

a presettable counter (U309) which is configured as down counter. When the unit size register (U308)is initialised, this counter is reset. On the first rising edge of the 1M_LIE it automatically preloads with

the value stored in the unit size register (unit size - 1). Every next rising edge of 1M_LIE the counter

is decremented, until its value is zero again. The next rising edge it preloads again etc. When the

counter goes zero the terminal count output is used to toggle the switch bit. Then the line buffer which

was filled in the mean time can be used. The signal to toggle the switch bit is also used as interrupt

for the CPU to denote that the next line buffer has to be filled. In figure 4.19 the operation of line

buffer selection is illustrated. In the shown example the unit size is four. This means that the counter

is preloaded with the value three. The switch bit is then stable during 4 lines.

TC=PE

NEXT_LB

SWITCH BIT

Figure 4.19 Illustration of the line buffer switch bit


Nederlandse Philips Bedrijven B.V.Centre for manufacturing Techno/ogy

4.6 Screen handler

After segmentation has taken place the stored AOIs have to be combined and send to a SBIP. Because

reading of the stored units can be done in a similar way as writing, the block diagram of the image

and screen handler look much alike. The block diagram of the screen handler is given in figure 4.20.

LA[2.. 15] LO[O..llj

...•·•••....·•··••.•······ ·····PO•••····•·.••··..•••.............

!>-START

r CLOCK !>-OISABLE

GENERATION !>-ENABLE

SCREENLINE

COUNTER

SCREENCOLUMNCOUNTER

LUT

SCR.LQO..4]

LU 0.. 13

SCR. 0..4:

t.......•...__ 4< •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• :

Figure 4.20 Block diagram of the ASP screen handler

In the next paragraphs the hardware of the shown blocks will be discussed. The hardware design of

the screen handler is given in appendix A, sheet 4, 5 en 6.

4.6.1 Look Up Table

In software the AOIs that are stored in the circular buffer are combined to a screen. In the image

handler line buffers were used to provide the start addresses in the circular buffer. In the screen

handler in a similar way the read address is stored in a Look Up Table (LUT). The size of this LUT

is detennined by the screen size. In equation (4.8) the required size for the LUT is calculated.

MIN LUT me =( screen.~ )2 = (512 ~ls)2 = 16384MIN umt SlU 4 pvcels

Hardware description of ASP

(4.8)

42


This means that a 16K memory is necessary. The width of the LUT has to be 12 bit. Eleven bit for

the circular buffer address (similar to the line buffer) and 1 bit which is used as interrupt to the CPU.

This bit has to be set if the read block in the circular buffer has to be reprogrammed.

Use is made of three 16Kx4 Static RAMs with separate I/O (CY7C162A). In this way a 16Kx12 LUT

is created.

4.6.2 Counters

To address the LUT a line and a column counter will give a unique identifier for every pixel. The

counters are controlled by the clock generator, which will be explained in the next paragraph.

The size of a screen detennines the size of the line and the column counter. Screen width is 512 pixels

which means that two 9 bit counters (29 = 512) can address each pixel in the screen. Both line counter

(U402, U403) and column counter (U404, U405) are realised using two 8 bit binary counters placed

in a cascade configuration.

4.6.3 Multiplexers

The LUT must be addressable by the screen counters during transmission of a screen. Besides that it

must be addressable by the CPU to load screen composition into the LUT. This introduces the need

for a switch between the two mentioned address busses and the LUT. The switch is created using four

quad-2-input multiplexers (U408-U411). The select input for the multiplexers is controlled by the CPU.

Writing to a flip flop (U406B) sets the select input to the desired value. In table 4.8 this is explained.

explained.

Table 4.8 LUT address bus control

I(CS.TO_LUD IDescription

ILDO

0 CPU address bus set to LUT

1 Counters set to LUT



After the multiplexer, similar to the image handler AND gates (U041, U042) are used to nullify the

LS bits of the LUT address. The unit size stored in the unit size register again is used to control these

gates.

Because nullifying of the address lines of the LUT is achieved after the multiplexers, writing to the

LUT by the CPU is only necessary to addresses, which can be divided by the unit size. The

composition of the address is given in figure 4.21

123 22 21 20119 18 17 16115 14 13 12 11 10 9! 8 7 6 5 4 3 21:i:.:il

l L lNOTUSED

COLUM ADDRESS: 0 STEP (UNIT SIZEl4)

LINE ADDRESS: 0 STEP (UNIT SIZE/4)

Figure 4.21 Look Up Table: address composition

4.6.4 Clock generation

On the contrary to the image handler, the screen handler does not receive pixels, but has to transmit

them. This means that the control signals belonging to the screen have to be created in the screenhandler. The clock generator provides these control signals. Before the block diagram of the clock

generator will be explained first the desired screen control signals are looked at.

If all fields of the LUT would be filled with addresses of the circular buffer (no dummy values), then(512)2 =256K pixels have to be available in the circular buffer. In equation (4.4) the maximum

number of pixels that can be stored in the circular buffer was already calculated to be 256K. This

means that the possibility exists that the circular buffer is filled completely with the screen that will

be sent. The currently incoming units then cannot be stored. To avoid a too high filling grade of the

circular buffer, burst sending is introduced. Instead of waiting until all units of a screen are available

in the circular buffer, transmission of an already available part of the screen is started. The control

signals are given in figure 4.22.

'-__---JL

SCR_PIE ~

BURST_PIE

SCR_L1E

<;--------l>

BURST

END_OF_BURST n n

Figure 4.22 Screen control signals



The control signals belonging to a screen are now extended with a signal called BURST_PIE. This

signal is high during the burst. Also an extra interrupt is introduced. This interrupt signals the CPU

that the burst is completely transmitted.

In figure 4.23 the block diagram of the implemented clock generator is given. In appendix A, sheet 5

the design of the clock generator is given. It will be implemented in an EPLD.

SCR_PIEBURST_PIESCR_L1E

EN_SCR_ClKEN_CP_CC

t==:::;-;::============:)EOB

CS.SEND c::::==~

CS.EN c::::==~

lLUT11 c::::==~

HClK==~

CC9

Figure 4.23 Block diagram of the screen clock generator

To achieve the sending of a burst (or the complete screen), the clock generator can be started by the

CPU (CS.SEND_SCR). During this start command the data bus (LD[O..7]) is used to write the length

of the burst (in units) in a counter. In the divider (appendix A, sheet 6) also a counter is present. This

counter is at the same moment set to zero. Then the SCR_LIE, SCR_PIE and BURST_PIE are set and

the counter is enabled. The timing diagram of starting a screen is given in appendix B1. Setting LD8

during the start of a screen denotes that the burst currently started is the last burst of the screen. If the

screen is sent at once of course this bit also has to be set.

When the screen is started, the column counter counts from 0 to 511 to address the pixels on this line.

Then counter value 512 (Column Counter, CC9 goes high) is used to set SCR_LIE low. CC9 is also

used for incrementing the line counter. Finally this signal is used by the divider. On the first rising

edge of CC9, the counter in the divider is loaded with the unit size minus one. Every next rising edge

this value is decremented until the counter value is zero again. Then a pulse is given to the burst

counter. The divide counter then preloads itself, etc.

In this way, the burst counter is decremented e.g. every 8 lines (if the unit size is 8). This is repeated

until the burst counter is zero. Then CC9 again is used to reset the SCR_LIE and BURST_PIE control

signals. If LD8 was set at the start of the burst SCR_PIE is also reset. To inform the CPU about the

end of the burst an interrupt is given to the CPU (END_OF_BURST). Of course also the counter is

disabled. The timing diagrams of end of line and/or burst situations are given in appendix B2 and B3.

Hardware description ofASP 4S


During the transmission of a screen or burst it might be necessary to change the current read block

in the circular buffer. Like said before similar to the line buffer for this an interrupt bit is used in the

LUT. If this bit is set in a unit, transmission of the screen is stopped immediately after the last pixel

of the unit (on the current line). The SCR_CLK for the receiving SBIP buffer is also stopped,

othelWise nothing would indicate the absence of valid data.

After the CPU reprogrammed the XBARs in the circular buffer, the transmission of the screen has to

be enabled again by the CPU (CS.EN_SCR). The SCR_CLK and the column counter are then again

enabled. The timing diagrams of both interrupting and enabling are shown in appendix B4 and B5.

LUT

LINEaCOLUMNCOUNTER

ENABLE

SCREENDRIVER

HCLK I-""'SCR'-"ClK""-- ---'- ----'

Figure 4.24 Clock usage in the screen handler

Finally in figure 4.24 the path from clock generator till data on the bus is illustrated. Due to the delay

introduced by the counters and the LUT, after the LUT the address has to be latched. Then the XBAR

and a memory block again introduce a delay. For that reason the screen data has to be latched after

the circular buffer. Then the clock which is used for column counter and latching is put on the bus

via a driver. Then it is taken from the bus using a receiver. This leads to the BUS_SCR_CLK, which

is used to clock the data and control signals on the bus. The receiving SBW buffer has also the

availability over this signal, so it can correctly receive the data and the control signals. In figure 4.25

the timing of the described block diagram is illustrated.

HeLl<

LLUT

LDORAM

Figure 4.25 Clock timing in the screen handler



5 Software description of ASP

The main activity during the graduate period concerned the development of the hardware of the ASP.

However, for test purposes some software development was necessary. In the next paragraphs a closer

look at the software concerning the ASP is given.

5.1 ERM

The prototype of the TB I inspection system will consist of a VME rack. In this rack the several

processing cards will be plugged. The master of the VME-BUS will be an ERM (Embedded Real-time

Monitor). This is a multi-tasking system used at Philips. During the development of the hardware tests

were also performed using an ERM system.

The ERM system can be loaded with software, originally written in C program language. In the used

test system the ERM system was coupled to the VAX network. On the VAX an editor, compiler and

linker are available to create machine code. The code on its turn can be downloaded to the ERM.

In table 4.5 the possible commands that can be used for the ASP were already given. In C language

some possible procedures could look as follows (ASP address dip switches set to zero):

#define writeLO_CAD(data)#define readCNT()

void setLO_CAD(data)short data;writeLO_CAD(data);

long getCNT ( ){ return«long)readCNT());

* «unsigned short *) (Ox30006))* «unsigned short *) (Ox30000))

data

During initialisation of the ASP by the HOST one should ensure that has been written at least once

to the counter and the four half word memory latches. This to ensure correct functioning of the ASP

VME-BUS interface.

5.2 ASP

The software which will run on the ASP has not been written yet. However, for correct understanding

of the function of the ASP, software will be explained in a global way. In figure 5.1 the flow chart

of the software is given.

Software description ofASP 47


INITIAl..ISATION

CALCULATION

no

NEW WRITEBLOCK

NEW READBLOCK

FILL NEXTLINE BUFFER

STARTSCREEN

ENABLESCREEN

interruptLAST_SCR

interruptSCR_READY

Figure 5.1 Flow chart of the ASP software

At the start moment shown in the figure the processor is enabled by the HOST. The processor starts

reading its program from address zero. During the initialisation the following should be taken care of

(given in pseudo code):

Software description ofASP 48


initialise DUART

initialise unit size register

initialise XBAR 1

initialise XBAR 2

calculate contents line buffer

load line buffer

calculate first screen

switch CPU to LUT

load LUT

switch counters to LUT

After the initialisation the main program is entered. This program only is concerned with calculations

(XBAR, line buffer, LUT contents). Purpose of these calculations is to have data available when an

interrupt occurs. After an interrupt occurred, the interrupt service routine is called. The tasks performed

in these routines are also shown in figure 5.1.

Not shown is the request by the CPU for new CAD data by an interrupt called SEND_SET_OF_ACS.

After this interrupt is placed, the HOST will write new CAD data to the communication memory

between HOST and ASP. From there the CPU can move the DATA to the CAD RAM.

Software description of ASP 49


6 Project status and Conclusions

At the time this report was written, the design of the ASP was almost ready. Only a communication

buffer between the HOST of the TB 1 inspection system and the ASP had to be added. With this buffer

the realised design will satisfy the requirements.

The VME-BUS interface has already been build and tested. The controller circuitry has only beenconnected, but not yet tested. Other blocks implemented in EPLDs are working properly, for

simulation with the development package showed no errors. Blocks designed using OrCAD design

tools were not simulated. Big problems however are not expected in these blocks, because timing

diagrams were set up to check their proper function.

Project status and Conclusions 50


Abbreviations

AOI

ASP

CAD

CFfCPU

DPS

EPLD

ERM

ESPRIT

FIFO

FMU

IMI

IRL

ISP

LIE

LS

LUTMS

PCB

PIE

RISC

RTMDSR

SBIP

SMT

SPARC

TBI

TTL

VME

Abbreviations

Area Of Interest

Area Segmentation Processor

Computer Aided Design

Centre for manufacturing Technology

Central Processing Unit

Data Processing System

Erasable Programmable Logic Device

Embedded Real-time Monitor

European Strategic Programme for Research and development in Information

Technology

First In First Out

Fiducial Measurement Unit

Industrial Measurement and Inspection

Interrupt Request Level

Industrial Signal Processing

LIne Enable

Least Significant

Look Up Table

Most Significant

Printed Circuit Board

PIcture Enable

Reduced Instruction Set Computer

Real Time Model Driven Shape Recogniser

Single Board Image Processor

Surface Mounted Technology

Scalable Processor ARChitecture

TestBed 1

Transistor Transistor Logic

VERSA Module Eurocard

51


Literature

* Esprit: Computer-Integrated Manufacturing and EngineeringThe Synopses

Commission of the European Communities

Volume 6 of 8, October 1991

* SPARC RISC User's Guide

Cypress Semiconductor Corporation

ROSS Technology, Inc.

Second Edition, February 1990

*

*

*

*

Cypress RISC Seminar Notebook (RISC 7C600)

Cypress Semiconductor

Seminar Series 1989

Development of the CAD Data Correction & Expansion Unitfor Esprit Project #2017

Frank van Leeuwen

Philips CPT Technology, September 1990

LSI Logic

Digital Signal Processing (DSP) Databook

June 1990

Electronic components and materials:Fast TTL Logic Series

Philips Data Handbook, Integrated Circuits 15 (IC15)

July 1986

* CMOS· BiCMOS Data Book

Cypress Semiconductor

March 1, 1991

* Users manual, VMEbus Prototyping Board PG2750IPG2751

Philips Export B.V.

1987

Literature 52


Appendix A

1 Hardware design controller2 EPLD design interrupt handler3 Hardware design image handler4 Hardware design screen handler5 EPLD design clock generator6 EPLD design divider7 Hardware design circular buffer8 Hardware design PI-bus interfaces9 Hardware design VME slave decoder10 Hardware design VME-bus interface

Appendix A 53

vee

UI098

f--#< S Q ---L.DCLK

:H:c D

:.~11

13 I:S 12

~ 74F02

7 Q e K~L

13

1vee eLK

---L PJ f-ll-Q I'

Ll\20

J: Ull0874F1l2

19

.A2 1

~ ~2

eo TROL e

D ..LA ..LD .. 1

U125

DO~Dl TXoA

D2r--LD3 TXDB

DOr-ll-05 OPO

06f---L07 OPI

AOp1LAl INTR

A2A3

I'D"

"SE

~ eEI'DWEMR

24 Xl

~- X2

8 RXOARXDBIP2

£OO"AC<o

B

U125A

~Me1489 ~MC1488

-

es

A

COMPONENT NUMBERS U118 AND U119 AREOPTiONAL FOR LATCHING DATA-BUS 016-D31WITH '74E'S'74 LATCHES

PHILIPS CE'T F.G.H. Smeets

TitleAREA SEGMENTATION PROCESSOR - CONTROLLER

Size I'Document Number IREVC CONTROL.SHT I

Date: .Jul 3 1992 Sheet 1 of 10

INTACI4

eLK

1:.0

INTl(,1

L2

INT2 [,3

INT3

INT4

INTS

,.....INTERRUPT HANDLERPHILIPS - eFT

F.G.M. Smeets' ... D "."'u EPM5016-1 .u"a'K 1. Oor'" A'AU 11:33a 8-17-1992 ..... 2 u· 10UKau ON ''''UK.• 1 OFF

o

C

B

A

lIM Lela .. 41 >11M cc ro.. 41 >

LBA ..U316

LBB .. 10 20 AO DOO 17 'B'O

Al 001 LBAA2 0023 A3 003

~ A4A5t' A6A7 19 ,nn

~A8 010A9 011 LDA10 012

I' All 013

r-;::lt WE/OECE

c:Y C" 1A- 5

U317

~0 20 AO 000 ~Al 001

A2 002 1:/

~A3 D03A4A5

~ A6A7 '.n.'t' A8 010 19

0 A9 011A10 DI21 All 013

~WE/OECE

C CI/1A- 5

U318'.RnA

t:: 20 AO 000 17Al 001

~ A2 002 BAA3 003A4

6A5A6

8 A7 -A8 010A9 011A10 012All 013

13 WE/OE...l1-< CE

....c: C1/1A- 5

U319T.RRO20 AO 000 17

~B Al 001

A2 002 BB2

~ A3 003 B

A4

~ iA5A6A7 19 LOn

~ A8 010A9 011 L~

BA10 012 3All Dr 3

:H:c WE/OECE

UNIT "

-C~ C171A- 5

.I""T ..,.U035A

INT .. 'U320

H2 t 1

II20 AO 000

74F04Al 001A2 002

U035B t:: A3 003

I""TT" m".. ' M4 t 3 ~ A5

74F04A6A7 T.noA8 010 19

"TI"" .... U035CUM''''

A9 011 L6 t 5 A10 Dr2

74F'04All 013

~ WE/OE< NEXT LB I CE

< UNITro .. 41 I C CI71A 5

11M LIE >

~U321

U20 U034BAD DOD 4LD .. Al 001 6 ~U308

A2 002 5 2:1A3 003

" T.no 3D1 01

2 A4 14F32D2 02 U

A5D3 03 sa ~ ~

A6D4 04 A7 19 '.nA05 05 A8 010 L06 06 A9 011

~ 9 1 A10 012 0CLK All 013

r-....!..c G

~HF31.WE/OECE

U034A C ClIlA- 5

CS.UNIT SIZ '"1

212: I 3

~HF32

o

C

B

A

Tit 1eAREA SEGMENTATION PROCESSOR - IMAGE HANDLER

Size Document Number

1M LCIM=CC

LALD

MAMB

LBALBB

image line counterimaqe column counter

latched address (processor)latched data (processor)

multiplexer Amult1plexgr B

line buffer Aline buffer B

C

Date:

PHILIPS eFT

Jul

F.G.H. Smeets

lMAGE.SHT1992 Sh,u~t of

REV

10

SCR LLC .. >.-U~15 {,

0 2 19 SC ur, SCR LCC .4D1 01D2 02 R C LLUT 0 .• 0

.!l£!:!L...,. D3 03 S RC D4 O~

S

D .. 4 D5 OS L·C S C 0

U401 D6 06 C CDO 1~ 23 D7 07 SCR C2LDO SCR PIE D8 08

~ D~LDI BURST ..IE :± r;:::tLD2 SC~LIE CLKLD3 ± OC

:'-- LD~ EN SCR eLI< DD LDS "t:.._~_ee I<F" 14

6 L06UNIT .. ~

L L07 EUB ,.......L U416

19~Ttee3L08 ~e: 2 Dl 01tT2 24 T D2 02

UNIT2 D3 03UNIT3 D~ O~UNIT~ D5 05 L

18 D6 06LLUTll ....£.!!.....

LLUTll f-i 07 07 ;-ee9 ~ D8 08 ~

N seR* 27 CS.EN,~ eLKS.

cs . E D SCR* eS.sEND oe~ LWE

I~F"I'

HeLKIS HeLl(

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~P~"5'032-1UT4 2 01 01 19.--U D2 02 i-UT6 D3 03

~D~ O~ TD5 05 TD6 06 i-U D7 07 i--D8 08 ~ LLUTI

~ eLK IF LUTll IS HIGHU035D oe AN INTERRUPT IS

9 1 8 "DI' GIVEN AND THE

7~FO~.. seR_eLK IS STOPPED

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PHILIPS eFT F.G.H. Smeet9LA : latched address (processor)LD latched data (processor 1 Title

M multiplexer AREA SEGMENTATION PROCESSOR - SCREEN HANDLERSize Document Number IREVLUT : look up table e SCREEN. SHT

Date: Ju1 3 1992 SheQt 4 of 10

LIl

~EOB

Ul

HI

I~BURST PIE

II

L~EN_CP_CC

~ EN_SCR_CLK

SCREEN DRIVERPHILIPS - CFT

)KS:GfiKR F.G.M. SmeetsiZE D IH~U EPM5032-1 r1TIlllT1< 1. oolu A

JAU 10: 57a 8-17-1992 ,,,n 5 UM 10:URHU ON 'KOURI" OFF

.TLKDIVIDER

PHILIPS - eFT".~"K F.G.N. Smeets'UK D IOPL

" EPMS032-1 '""80" 1.001"KV A'AU 11: 288 8-17-1992 .&06> 6 V. 10'UA"V ON UCUAU" OFF

1M H

1M I 0.. J

C

1M IE* J1M IE J"I PIE'"

IN LIE* J

K*SC CLK J

B

1M PIE image picture enableIM-LIE image l1ne enabl.e

AIM:CLK image pixel clock

WIN PIE window picture enableWIN:LIE window 11ne enable

1M- H image height (dat.a)1M- I image lnt.ens-1ty (data)

1M image (data)

SCR PIE screen picture enableSCR=LIE screen 11ne enable

SCR_H scroen height (data)SCR_ I screen intensity (data)

SCR screen (data)

0**

2

0

SCR H O.. * J

I:j

~ SCR * J '>..

~3

"7

~C

====1~g: PIE·l~~! ~LIE"

,--..-jSCR eLK* (J61 >

~.1-

B

A

PHILIPS CFT F.G.H. SHEETS

TitleAREA SEGMENTATION PROCESSOR - PI-BUS INTERF.

Size IDocument Number IREVC PIC INT. SHT

Date: Jul 3 1992 Sheet 8 of 10

C

B

D

CNT ~

s;v* tJ3 ~

DXS CPO ~

NIt 'a.: ....

f--=.i---1 S5-l3

Y7 r-!1Y6 r---

~i B=Y2 1-- .....Y1 r--i .....YO

0904

VC(C0905

VCC

_..

L...-+-i-16p.a G4......+4-'·!>ro G3

.....-+-Hri,4H G2L!L G1

1...-_+-_1:=.,7.0-1 CL...-_.....,1--~7H B

i..-__--1_.....:6:::.....j A

...._""i5;.a 01:2"---.ri4jH] OE1....--=-=~Z"""-t AL

Y7t-tr-+_--=1:,;7r-t C Y6

t-Ir-+-f---.,7H B Y5~1-+++--_.....:6y A Y4

fiE g:~ ~~AL YO

74F5~B

1--.;.2 .-+-1;r,6p.a G4

I-T---....+--t-T~'TQ·5 G3~ G2L!L G1

Q1Q2Q3Q4

g~ f-l",--

0903

74F27

n19

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~J D4J D5

9 0001C ~!.- D6

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1=~74VCC

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1lAM0 Q4Q5

H ;- Q6I-' :.... Q7

vrf 0901:J..

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J1 [.., P3P4

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IJ3)

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~ '- P7

/BA1.;a:;i"i5HH3H QO/ABA~l;o.4--1---iiO--l "'1

BA1.3 '",/'BA1.;a:;r,;2H f---..,H Q2·"BA~l~l:........j~~ Q3

Q4,/ H ;... Q5

~ H :- Q6_ I-' :.... Q7

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C

D

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A PRXLXPS CFT F.G.". saeeta A

T.itle

AREA SEGMENTATION PROCESSOR - SLAVE DECODER

S.ize Document NUlllber REV

A

Date:

DECODER. SST

3 1992 Sheet 9 of 10


Appendix B

1 Timing diagram starting transmission of a screen2 Timing diagram end of line of a screen

3 Timing diagram holding screen for programming XBAR

4 Timing diagram enabling screen after programming XBAR

5 Timing diagram end of burst of a screen

Appendix B 64


1 Timing diagram starting transmission of a screen

SCLI<

LWE

LD(O..7)

LD8

BURSCCNT

HCLK

BURSCPIE

--QJJ--QJJ

~'---------------------: ,--_.. :.. ,

:: ::

+=f'-3.:....4 _

fI'-------+-_--11

CC

Appendix B

____+-__-+'x 1 X 2 X 3 ix 4

65

DO •. J4

Ul009n ~!J001A ~~_ V 2 01 01 19

BAS J 1 Ul007

~,~ i ~02 02 0

12 1 o 8OS" J ~I IN SNS 03 03 0UDS'" J 10NS p;~O 04 04 0ISNS OS OS74F27 20NS p;~ i V06 06 0

2SNS 07 07 2330NS 08 083SNS ~ 0-

1140NS

~EeLK

4SNS r----"-< DeSONS 14",14

'OA-l0'OU1010

"0

0

I~2 01 01 1

S02 02 2603 03 004 04 o 8OS OS06 06

~±: 07 07 0

08 0811 eLK

...........!< DC,.. ,,.

.-.....U1017

AO 2 01 01 19 S 0 d2 02 02

03 03 S 3 ~04 04oS OS S 4 '---"S06 06 D6 ~07 0708 08 '---"

----4-:: eLKDe

,."'14e

e U10188 2 01 01 19 sn,9

•02 02 SO03 0304 04 ~ILD HI DATA > oS OS SO

06 06 ----I

1 07 07 S VM -----::08 08

L:::± CLKDe

U002A,.. ,,.

~A .. J)

& 12

74nO

WR LO PRGWR CA

R eN

oJ

ISLV'" (J3) >-

BB

~lEN CPU >-----

ISCLK IJ41 >-

vee

I LOCR (J4) >-

[J[ R6-710k

AA RO J

SIZE JSIZE J4WRT J4

[m9 WE" J4

I Wit HI CAD >- R8-1010k

PHILIPS CFT F.G.H. Smeets

TitleAREA SEGMENTATION PROCESSOR - VME-BUS INTERF

Sitze IDocument Number IREVC VME INT.SHT

Date: Julv 3 1992 Sheet 10 of 10


2 Timing diagram end of line of a screen

SCR_ClK

CC :=IX 511 X 512 1x 0 X ix 2

iSCR_CC9 I ILlJCPSCR_lC

lC 0 : X

iDIVIDE_CNT 3 X 2

SCR_L1E I

Appendix B 66

Nederlandse PhilipS BedrlJven B.V.Centre for manufacturing Technology

3 Timing diagram holding screen for programming XBAR

cc

LLUTll

Appendix B

!=tx 84 X,-_E5_+,X 88 X 87 X,-_68_....;.-__",-__

--W L_---4-__.:--__

67


4 Timing diagram enabling screen after programming XBAR

J1..WE LJLJi

--'-__--;--_J

~-----7--~

Appendix B

68 iX,-_69_-i-'X 70 X 71

68


5 Timing diagram end of burst of a screen

cc

LC

EOB

Appendix B

=tx 511

o

x'---__-:-' '---__-:--__--:--- _

I

· .· .· ... - _~:.. •• _. ~ - _ ••••• - _.. e •• •••• _ _ _ _ ••••• 0 •••••• _~

69

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