elct701_lecture1

7/25/2019 ELCT701_lecture1

1/12

09/11/1431

1

1 Dr. Ahmed H. Madian

Integrated Circuits Design

Lecture 1Dr. Ahmed H. Madian


Course Objective

Give an introduction to the primary design parameters

in digital integrated circuit.

Focus on the transistor level design and analysis.

Analyze digital circuits by calculating the delay, noise

margin, area, and power dissipation.

Cover different techniques to build digital circuits suchas static versus dynamic logic.

Discuss some industrial design issues such as globalsignals and testing.


2/12

09/11/1431

2


Text and Reference Books

Text Book

Sung-Mo Kang and Yusuf Leblebici, "CMOSDigital Integrated Circuits: Analysis and Design.WCB McGrew-Hill, 2003, ISBN: 0-07-246053-9.

Recommended reference books:

Jan M. Rabaey, Anantha Chandrakasan, andBorivoje Nikolic Digital Integrated Circuits:Second Edition. Prentice-Hall, 2003, ISBN-10: 0-13-090996-3, ISBN-13:9780130909961.


Administrative rules

Course schedule

Lecture : Wednesday (2nd slot), 10:30 12:00 (H11)

Office hours : Wednesday, 12:30-2:00 (C3.220)

Teaching assistant: Eng. Mohamed Zidan

Grading Assignments: 10%

Quizzes: 10%

Mid term exam: 30%

Final exam: 50%


3/12

09/11/1431

3


Course Outlines

Introduction

MOS inverters

Inverter switching characteristics

Power dissipation in digital circuits

Combinational and sequential MOS logic circuits

Dynamic logic circuits Memories

Design for testability


What is Integrated Circuits?

Integrated Circuit (IC): Is an electronic circuit whichcan perform a completed task

IC usually contains analog and digital circuits.

Analog circuits could be as simple as a diode(rectifier) or a simple amplifier or as complex as aPLL (Phase Locked Loop).

Digital circuits could be as simple as an inverterwhich inverts the polarity of the input signal or ascomplex as a micro-processor.

In this course we are only concerned with digitalICs.


4/12

09/11/1431

4


Design

hierarchy

overview

System specifications

Abstract High-level modelVHDL, Verilog, HDL

Logic synthesis

Circuit design

physical design

Manufacturing

Finished VLSI chip

Top design level

bottom design level

Initial concept

System designand verification

Logic designand verification

CMOS designand Analysis

Silicon logic designand verification

Mass production,testing andpackaging

Marketing

Our Course focus

on this area


Moores Law In 1965, Intel co-founder Gordon Moore predicted the future. His prediction,

now popularly known as Moore's Law, states that the number of transistors ona chip doubles about every two years. This observation about siliconintegration, made a reality by Intel, the world's largest silicon supplier, hasfueled the worldwide technology revolution.

Many predictions followed his statement such as Area/Power/Frequency.


5/12

09/11/1431

5


Design Parameters of Digital Circuits

Functionality

Area

Frequency

Power

Noise

Logic levels

These parameters are inter-dependentwhich means satisfying one of them couldcause a violation to the other.


Logic Levels

In binary system, theres onlytwo values logic 1 or logic 0.

For each logic theres a definedvoltage range.

If the signal voltage lies in the

range from VH1 to VH2 its logic 1

If the signal voltage lies in the

range from VL1 to VL2 its logic 0

Logic 1

Logic 0

Undefined

region

VH2

VH1

VL2

VL1

Volts


6/12

09/11/1431

6


Manufacturing Technology

Different technologies are used to build ICs: (GaAs, SiGe, Bipolar, ECL, NMOS, CMOS, etc.)

Why CMOS and not any of those? CMOS has a super-advantage over all other

technologies which is its power dissipation.

CMOS should dissipate no static power whichmakes it the most attractive technology until now.

Dissipated Static Power= 0W

So, we need to review the MOSFETcharacteristics


Revision on MOSFETs characteristics MOSFET (Metal Oxide Semiconductor Field Effect

Transistor)

It has two types (N-channel and P-channel)

NMOS PMOS

D: DrainS: SourceG: Gate


7/12

09/11/1431

7


Modes of operation of NMOSTransistor (1) Off Mode: VGS < VT ID = 0

(2) On Mode: VGS > VT

(a) Linear region VDS < VGS VT or VGD > VT

(b) Saturation region VDS > VGS VT or VGD < VT

( )

=

2

2

DSDSTGSnDS

VVVVKI

( )2,2

TGSn

satDS VVK

I =

=

L

WCK oxnn .

2

where

14Dr. Ahmed H. Madian

(1) Off Mode: VSG < |VTP | ID = 0

(2) On Mode: VSG > |VTP|

(a) Linear region VSD < VSG|VTP | or VDG > |VTP |

(b) Saturation region VSD > VSG|VTP | or VDG < |VTP |

Modes of operation of PMOS

Transistor

( )

=

2

2SD

SDTPSGPSD

VVVVKI

( )2,2

TPSGP

satSD VVK

I =

=

L

WCK

oxp

P .2

where


8/12

09/11/1431

8


Course Outlines

Introduction

MOS inverters

Inverter switching characteristics

Power dissipation in digital circuits

Combinational and sequential MOS logic circuits

Dynamic logic circuits Memories

Design for testability


MOS Inverter Static Characteristics Inverter is one of the basic elements in digital ICs.

A lot of circuit analysis are based on determining thecharacteristics of the inverter.

Inverter characteristics could be classified into static anddynamic characteristics.

Static characteristics define the noise margins of the device.

The function of an inverter is to invert the polarity of the inputsignal.


9/12

09/11/1431

9


The Basic Inverter

The ideal inverter has: Vth = VDD/2 VoL = 0 VoH = VDD

Where VDD is the supply voltage

BA

10

01

VTC (voltage transfer characteristics) of the inverter


Resistive Load MOS inverter

For Vin < VT The NMOSis in cut-off

IDS = 0

Vout = VDD


10/12

09/11/1431

10


Resistive Load MOS inverter For VT Vin < Vx

The NMOS is ON and in the saturation region

( )22

TGSn

DS VVK

I =

Vout = VDD IDs R

( ) TTGSn

DDTDSDDToutx VRVVK

VVRIVVVV +=+=+= .2

2

( )22

TGSn

DS VVK

I =

IDS

VDS

VGS

VDD

saturationLinear


For VX Vin The NMOS is ON and in the linear region

Resistive Load MOS inverter

( ) ( )

=

=

22

22out

outTinnDS

DSTGSnDS

VVVVK

VVVVKI

Vout = VDD IDs RL

VDD

Vout

VinVT

Cut-off

VX

Sat.

linear


11/12

09/11/1431

11


Noise Margin in the MOS Inverters

VOH : Maximum output voltage when the output level is logic 1 VOL : Minimum output voltage when the output level is logic 0 VIL : Maximum input voltage which can be interpreted as logic 0 VIH : Minimum input voltage which can be interpreted as logic 1

NML= VIL - VOLNMH= VOH - VIH


Noise Margin in Resistive Inverter VOH when Vin = 0 => IDS=0 => Vout = VDD VOH=VDD VOL when Vin = VDD

( )

Ln

DD

Ln

TDD

Ln

TDDOL

Ln

DDOL

Ln

TDDOL

OLtDDn

L

OLDD

Rk

V

RkVV

RkVVV

Rk

VV

RkVVV

VVVVk

R

VVOL

211

02

).).(

1.(2

2

2

2

2

++=

=++

=

VIL when dVout/dVin = -1 and NMOS in Saturation

( )( )

( )

Ln

TIL

TILn

L

Tinn

in

out

L

Tinn

L

outDD

RkVV

VVkR

VVkdV

dV

R

VVk

R

VV

1

).()1.(1

..1

.2

2

+=

==

=


12/12

09/11/1431

12


Noise Margin in Resistive Inverter

VIH when dVout/dVin = -1 and NMOS in Linear

( )( )

( )

[ ]

LnLn

DDTIH

outoutTIHnL

in

outoutout

in

outTinn

in

out

L

outTinn

L

outDD

RkRk

VVV

VVVVkR

dV

dVVV

dV

dVVVk

dV

dV

R

VVVVk

R

VVout

1.

3

8

)1.()1)((.)1.(

1

....1

2..

2

+=

+=

+=

=

elct701_lecture1

Documents