ele863 lab manual

EE8501/ELE863 - VLSI Systems

Laboratory Manual

F. Yuan, PhD., P.Eng.

Professor

Department of Electrical and Computer Engineering

Ryerson University

Toronto, Ontario, Canada

Copyright c©Fei Yuan 2011

Preface

This laboratory manual is an essential component of EE8501/ELE863

VLSI Systems offered by Professor F. Yuan in the Department of Electrical

and Computer Engineering at Ryerson University, Toronto, Ontario, Canada.

Permission to duplicate and distribute this document is granted for educa-

tional purpose only.

This laboratory manual consists of four laboratories. Laboratory 1 stud-

ies the cross-coupled CMOS current-controlled oscillators. In Laboratory 2,

the design of a D-flipflop phase/frequency detector is explored. Laboratory

3 deals with the design of a phase-locked loop. In Laboratory 4, the effect of

package parasitics is investigated. An complete chip set of the phase-locked

loop designed in the preceding four laboratories is analyzed in this laboratory.

Please report any error in this Laboratory Manual or problem encountered

during laboratories to Professor F. Yuan at [email protected].

Fei Yuan

Jan. 2011

1

Calendar Description of EE8501/ELE863 VLSISystems

This course deals with the design of low-power high-speed CMOS inte-

grated circuits using deep sub-micron CMOS technology at the system level.

The course consists of two essential components: theory and project. The

theoretical component consists of : advanced topics on modeling of MOS

transistors, modeling of interconnects (lumped, distributed RC, distributed

RLC, and transmission line models), impedance matching techniques, lay-

out techniques for high-speed digital and mixed analog-digital circuits, clock

generation and distribution on chip, power distribution on chip, analog and

digital grounding of mixed analog-digital circuits on chip, I/O and pad de-

sign, packaging and ESD protection, switching noise, and high-speed data

links. The project component consists of design, layout, and simulation of

CMOS circuits using state-of-the-art CMOS technology and CAD tools.

3 hours lecture, 1 hours laboratory each week.

Prerequisites ELE704 or ELE734.

2

Contents

1 Current-Controlled Ring Oscillators 7

1 Duration : 2 weeks . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Switching Noise Injector . . . . . . . . . . . . . . . . . 9

3.3 Simulation and Analysis . . . . . . . . . . . . . . . . . 9

4 Laboratory Report . . . . . . . . . . . . . . . . . . . . . . . . 10

2 D-flipflop Phase/Frequency Detectors 13

1 Duration : 2 weeks . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 D-Flipflops . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 D-Flipflops with RESET . . . . . . . . . . . . . . . . . 14

3.3 AND2 Gate . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 D-flipflop Phase/Frequency Detector . . . . . . . . . . 15


3 Phase-Locked Loops 19

1 Duration: 2 weeks . . . . . . . . . . . . . . . . . . . . . . . . . 19

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 20

3

3.1 Charge Pumps . . . . . . . . . . . . . . . . . . . . . . 20

3.2 Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3 Open-Loop Test . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Closed-Loop Test . . . . . . . . . . . . . . . . . . . . . 23


4 Phase-Locked Loop Chip Set 27

1 Duration : 4 weeks . . . . . . . . . . . . . . . . . . . . . . . . 27

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 Models for Packaging . . . . . . . . . . . . . . . . . . . . . . . 27

4 Models for Bond Pads . . . . . . . . . . . . . . . . . . . . . . 28

5 Models for Bond Wires . . . . . . . . . . . . . . . . . . . . . . 29

6 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 Complete Test Circuit Construction . . . . . . . . . . . 29

7.2 VDD and VSS Pads . . . . . . . . . . . . . . . . . . . . 30

7.3 VCO Output Buffering . . . . . . . . . . . . . . . . . . 31

7.4 PLL Test . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 Layout of PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.1 Floor-Planning of PLL . . . . . . . . . . . . . . . . . . 32

8.2 Layout of PLL . . . . . . . . . . . . . . . . . . . . . . 32

8.3 I/O Pin Assignment . . . . . . . . . . . . . . . . . . . 33

8.4 Layout of Pads . . . . . . . . . . . . . . . . . . . . . . 33

8.5 Layout of Output Buffers . . . . . . . . . . . . . . . . 33


4

List of Figures

1.1 Four-stage fully differential current-controlled ring oscillator . 9

1.2 Symbol of the delay cell of fully differential current-controlled

ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 D flip-flop phase/frequency detector. . . . . . . . . . . . . . . 15

2.2 D flip-flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Basic configuration of type II phase-locked loops. . . . . . . . 20

3.2 Current-steering charge pump. The charge pump conveys JUP

to the downstream loop filter when UP=1 and DN=0. It sinks

JDN from the loop filter when DN=1 and UP=0. . . . . . . . 21

3.3 Implementation of the current-steering charge pump. . . . . . 22

3.4 Open-loop test circuit. . . . . . . . . . . . . . . . . . . . . . . 23

3.5 Fully differential cross-coupled voltage-controlled oscillator. . . 24

4.1 Simplified schematic of complete chip set . . . . . . . . . . . . 30

5

List of Tables

4.1 Pad assignment of phase-locked loop chip set. . . . . . . . . . 31

6

Chapter 1

Current-Controlled Ring

Oscillators

1 Duration : 2 weeks

2 Introduction

Voltage (current)-controlled ring oscillators are used extensively in computer

systems and data communication networks. This laboratory investigates the

design of fully differential CMOS current-controlled ring oscillators with an

emphasis on switching noise and their impact on the timing jitter of the os-

cillators. In this laboratory, you are required to design a four-stage fully dif-

ferential CMOS current-controlled ring oscillator using TSMC-0.18µm 1.8V

CMOS technology and analyze the performance of the designed oscillator

using Spectre from Cadence Design Systems with BSIM3.3v device models.

The oscillation frequency of the oscillator is 900 MHz. The delay cell of the

oscillator was the originally reported in [1], as shown in Fig.1.1. This delay

cell utilizes a positive latch formed by M1∼2 to combat the switching noise

present on the power and ground rails in the following ways : (i) The positive

feedback reduces the transition time and sharpens both the rising and falling

7

CHAPTER 1. CURRENT-CONTROLLED RING OSCILLATORS 8

edges of the waveform of the oscillator. (ii) A fast transition minimizes the

timing jitter of the oscillator. As pointed out in [2] the noise of the MOS de-

vices and the switching noise of the VCO’s output at the threshold-crossing

shifts the actual threshold-crossing time (timing jitter) by an amount that is

proportional to the power of the total noise injected at the threshold-crossing

and inversely proportional to the slew rate of the output voltage [2].

∆τ 2 =v2

n

(dvo/dt)2, (1.1)

where ∆τ 2 is the timing jitter, v2n is the power of the total noise injected at

the threshold-crossing, and dvo/dt is the slew rate of the output voltage of

the oscillator at the threshold-crossing. (iii) The latch effectively rejects the

noise presented on the power and ground rails once the latch is established.

3 Laboratory Work

3.1 Oscillator

Design a four-stage CMOS fully differential current-controlled ring oscillator,

as per the schematic of Fig.1.1 where all n-well pickup contacts of pMOS tran-

sistors are connected to a clean power supply. The bond wire connecting the

VDD bonding pad and the power supply pin is modeled as an ideal inductor

with its inductance L = 0.1 nH. The inductance of the bond wire connecting

VSS and ground is neglected so that no ground bouncing is considered. The

capacitance of the bonding pads is neglected for simplicity. The width of

M3∼4 should be at least twice that of M1∼2 in order to be able to break the

positive feedback. Over-sizing M3∼4 will result in a large capacitance at the

output nodes, slowing down the oscillator.


VDD1

L

CL

Switching noise injector

VDD2

L

Vin+ Vin-

Vo+Vo- 4

Cross-coupled delay cell (Stage 1)

Ictrl

M1 M2M3 M4

M5 M6

Figure 1.1: Four-stage fully differential current-controlled ring oscillator

3.2 Switching Noise Injector

A static CMOS inverter whose dimension is much larger than the dimension

of the transistors in the delay stage of the oscillator is powered by the same

power supply as that of the oscillator. Let the load of the large CMOS

inverter be a large capacitor. The input of the large CMOS inverter is an

ideal square wave generator whose period is much smaller than the oscillation

period of the oscillator. This clocked large inverter is used to simulate the

injection of switching noise to the power rail of the oscillator.

3.3 Simulation and Analysis

• Construct the symbol of the delay cell of the oscillator that has (i)

two input terminals vin+ and vin−, (ii) two output terminals vo+ and

vo−, (iii) one VDD connection terminal, (iv) one VSS connection termi-

nal, (v) one n-well connection terminal vn−well, and (vi) one substrate

connection terminal vsub, as per Fig.1.2.

• Construct the current controlled oscillator by including (i) all delay

stags, (ii) the biasing circuit, (iii) the switching noise injection circuit,

and (iv) VDD and VSS circuitry including bonding wires.

• Perform time-domain analysis of the designed oscillator. The start of


Delay cell

Vin+

Vin-

Vo-

Vo+

VDD Vn-well

VSS Vsub

Figure 1.2: Symbol of the delay cell of fully differential current-controlled

ring oscillator

the oscillation of the oscillators can be activated by connecting a small

capacitor to the output node of one of the delay stages of the oscillator

with an initial voltage. Note that the value of the capacitor should be

small in order to minimize unwanted loading effect.

• Plot the output voltage of each stage of the oscillator with two different

transistor widths of the latch. Measure the timing jitter. Comment on

the waveform difference.

• Plot the output voltage of each stage of the oscillator with two different

control currents. Measure the rise and fall times of the output voltage

in both cases. Measure the timing jitter. Comment on your findings.

• Use parametric analysis and calculator tools to obtain the oscillation

frequency-control current plot. Estimate the frequency tuning range

and frequency control sensitivity of the designed oscillator.

4 Laboratory Report

A professionally prepared laboratory report containing the followings is due

at the start of the next laboratory.


• The schematic of the current-controlled oscillator (delay cell + entire

test circuit) with a boarder section showing your name and student ID.

• A table tabulating the exact dimension of all transistors used in your

design.

• The waveform of the voltage of the output of each stage of the current-

controlled oscillator with two different transistor widths of the latch.

Measure the peak-to-peak timing jitter at the threshold-crossing points

of the output waveform of the oscillator.

• The waveforms of the voltage of the output of each stage of the current-

controlled oscillator with two different control currents. Measured the

rise and fall times in these two cases. Measure the peak-to-peak timing

jitter at the threshold-crossing points of the output waveform of the

oscillator.

• Oscillation frequency - control current plot. Determine the frequency

tuning range and frequency control sensitivity.

Bibliography

[1] X. Mailand, F. Devisch, and M. Kuijk, “A 900 Mb/s CMOS data re-

covery DLL using half-frequency clock,” IEEE Journal of Solid-State

Circuits, vol. 37, No. 6, pp 711-715, June 2002.

[2] T. Weigandt, B. Kim, and P. Grey, “Analysis of timing jitter in ring

oscillators,” in Proc. of IEEE International Symposium on Circuits and

Systems, pp. 27-30, London, 1994.

12

Chapter 2

D-flipflop Phase/Frequency

Detectors


2 Introduction

Phase/frequency detectors (PFDs) are one of the vital building blocks of

phase-locked loops (PLLs) and delay-locked loops (DLLs). The main func-

tionality of PFDs is to sense the phase/frequency difference between an input

digital stream and a reference clock and to output a pair of phase/frequency-

modulated pulses called UP and DOWN whose pulse width is directly pro-

portional to the phase/frequency difference. The output signals UP and

DOWN are then used to control a downstream charge pump whose output

voltage controls the oscillation frequency of a downstream voltage (current)-

controlled oscillator.

In this laboratory, you will investigate the characteristics of a widely

used phase/frequency detector called D-flipflop phase/frequency detector.

The D-flipflop phase/frequency detector employs two positive edge-triggered

resettable D-flipflops to detect the phase/frequency difference of two input

13

CHAPTER 2. D-FLIPFLOP PHASE/FREQUENCY DETECTORS 14

digital signals, as shown in Fig.2.1. The output voltage waveforms with

A leading B are shown in the figure. The waveforms for B leading A are

the same as those for A leading B due to the symmetrical structure of the

phase/frequency detector.

3 Laboratory Work

3.1 D-Flipflops

There are a number of ways to construct a D-flipflop in CMOS. Conventional

implementations of D-flipflop, such as the one shown in Fig.2.2(a), suffers

from a large number of transistors, high power consumption, and a long

propagation delay. True-single-phase-clocking (TSPC) logic circuits initially

developed in [1] offer the advantages of a low transistor count, a small chip

area, and a fast transient response. In this laboratory, TSPC logic circuits

are employed to construct the D-flipflop, as shown in Fig.2.2(b) [2, 3]. Only

6 transistors are needed for the construction of the positive-edge triggered

D-flipflop.

3.2 D-Flipflops with RESET

Modify the D-flipflop of Fig.2.2(b) by adding a RESET control mechanism

that resets Q to Logic-0 when RESET=1. Measure the propagation delay

from D to Q and record the delay.

3.3 AND2 Gate

Construct the schematic of an static AND2 gate. Construct the symbol of

the AND2 gate. Measure the average propagation delay of the AND2 gate

and record the delay.


DQ

R

DQ

R

A

B

Df0

Vm

2p

A

B

Q

Vm

A

B

A

QB

A

B

QmA

QB

V /40

0

(a) Df=0 (b) Df=p/2

Df0

Vm

-2p

QA Q B

Figure 2.1: D flip-flop phase/frequency detector.

3.4 D-flipflop Phase/Frequency Detector

Construct the schematic of the D-flipflop phase/frequency detector. Apply

two square waves A and B of the same oscillation period and duty cycle but

difference phases to the phase/frequency detector. Let input A lead input B

with a phase difference ∆φ. The following simulations are to be carried out

in the laboratory work.

• Plot the waveform of QA and QB when ∆φ is in the neighborhood

of zero. Both QA and QB for ∆φ > 0 and ∆φ < 0 are considered.

Estimate the average value of QA and QB over a period.

• Plot the waveform of QA and QB when ∆φ is in the neighborhood ofπ2. Both QA and QB for ∆φ > π

2and ∆φ < π

2are considered. Estimate

the average value of QA and QB over a period.

• Plot the waveform of QA and QB when ∆φ is in the neighborhood of

π. Both QA and QB for ∆φ > π and ∆φ < π are considered. Estimate



D

Q

D

CLK

Q

Q

(a) (b)

CLK

CLK

CLK

CLK

Figure 2.2: D flip-flops.

• Plot the waveform of QA and QB when ∆φ is in the neighborhood of 3π2

.

Both QA and QB for ∆φ > 3π2

and ∆φ < 3π2

are considered. Estimate


• Plot the waveform of QA and QB when ∆φ approaches 2π. Estimate


• Use the above estimated average value of QA and QB to construct a plot

shown the relation between “average output voltage” and “phase differ-

ence”, i.e. the transfer characteristics of the D-flipflop phase/frequency

detector.

4 Laboratory Report



• The schematic of the resetabble D-flipflop with a boarder section show-

ing your name and student ID.

• The schematic of the AND2 gate with a boarder section showing your

name and student ID.

• The schematic of the D-flipflop phase/frequency detector with a boarder

section showing your name and student ID.


• A table tabulating the exact dimension of all transistors used in your

design.

• The waveform of QA and QB when ∆φ is in the neighborhood of zero.

The plot of QA and QB for ∆φ > 0 and ∆φ < 0 are required.

• The waveform of QA and QB when ∆φ is in the neighborhood of π2.

The plot of QA and QB for ∆φ > π2

and ∆φ < π2

are required.

• The waveform of QA and QB when ∆φ is in the neighborhood of π.

The plot of QA and QB for ∆φ > π and ∆φ < π are required.

• The waveform of QA and QB when ∆φ is in the neighborhood of 3π2

.

The plot of QA and QB for ∆φ > 3π2

and ∆φ < 3π2

are required.

• The waveform of QA and QB when ∆φ approaches 2π.

• The plot “Average output voltage versus phase difference”.

Bibliography

[1] J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflops

with improved speed and power savings,” IEEE J. Solid-State Circuits,

vol. 32, No.1, pp. 62-69, Jan. 1997.

[2] J. Rabaey, Digital Integrated Circuits : A Design Perspective, Upper

Saddle River, NJ : Prentice-Hall, 1996.

[3] K. Martin, Digital Integrated Circuit Design, New York : Oxford Uni-

versity Press, 2000.

18

Chapter 3

Phase-Locked Loops

1 Duration: 2 weeks

2 Introduction

Phase locked loops are used extensively in data communications, computer

systems, RF communications, instrumentation, and signal processing. The

basic configuration of type II phase-locked loops is shown in Fig.3.1. The

phase/frequency detector detects the phase/frequency difference between the

incoming signal Vin and the output of the local ring oscillator and converts

the phase/frequency difference into two Boolean control signals UP and DN.

The pulse width of UP and DN is proportional to the phase difference. UP

and DN are then fed to the downstream charge pump whose mainly function

is to convert UP and DN pulses into currents of constant amplitude. When

UP=1 and DN=0, JUP is conveyed to the loop filter, increasing the output

voltage of the loop filter. When UP=0 and DN=1, JDN is sinked from the

loop filter, lowering the output voltage of the loop filter. The loop filter

is a low-pass that filters out the high-frequency components of the output

current of the preceding charge pump and outputs a voltage. The output of

the loop filter is a dc voltage that controls the oscillation frequency of the

19

CHAPTER 3. PHASE-LOCKED LOOPS 20

downstream voltage-controlled oscillator (VCO). The oscillation frequency

(period) of the VCO is proportional to the phase difference between Vin

and Vo of the VCO. By adjusting the oscillation period of the VCO, the

phase/frequency difference can be driven to zero.

Vin

J

JC1

UP

DN

UP

DN

Vvco C2

R2

Charge pump

Loop filter

PFDVoltage-controlled oscillator

Figure 3.1: Basic configuration of type II phase-locked loops.

In this laboratory, you are required to design a phase-locked loop that

makes use of the fully differential cross-coupled 4-stage voltage-controlled

oscillator and the D-flipflop phase/frequency detector designed in previous

laboratories. In order to construct the phase-locked loop, you are also re-

quired to design and analyze two additional function blocks of phase-locked

loops, namely the charge pump and the loop filter, as shown in Fig.3.1.

3 Laboratory Work

3.1 Charge Pumps

The main functionality of a charge pump is to convert the width-modulated

pulses UP and DN from the preceding D-flipflop phase/frequency detector

into a current whose amplitude is constant and whose direction is controlled

by UP and DN signals. A charge pump is essentially a digital-to-analog

converter. Fig.3.2 is the schematic of a current-steering charge pump. The

charge pump conveys a constant current JUP to or sinks a constant current


JDN from the output node, depending upon the control signals UP and DN

from the preceding D-flipflop phase/frequency detector. For more informa-

tion on charge pumps, please read reference [1] and the main reference text

of the course.

Construct the schematic of the charge pump and its symbol. The charge

pump symbol should have the following inputs : UP, UP, DN, DN, Vout, VDD

and VSS. All n-well and substrate contacts are connected to the same power

supply and ground as those of the charge pump.

JUP

UPUP

JDN

DNDN

vo

M1 M2M3 M4

M5M6

Figure 3.2: Current-steering charge pump. The charge pump conveys JUP to

the downstream loop filter when UP=1 and DN=0. It sinks JDN from the

loop filter when DN=1 and UP=0.

An implementation of the preceding charge pump is shown in Fig.3.3.

The current sources JUP and JDN are generated by the current reference

circuit consisting of M7∼9 and the two current mirrors M9∼10 and M9∼11. Vcp

is an external voltage that controls the value of JUP and JDN . Vcp should be

assigned as a variable so that it can be adjusted during simulation. You can

also make use of advanced biasing circuits studied in ELE704. Note that JUP

and JDN must not be too small as they directly affect how fast the control

voltage can be controlled by UP and DN signals. They must also not be too

large to avoid instability of the phase-locked loop.


UPUP DNDN

vo

M1 M2M3 M4

M5M6Vcp M7

M8

M9

M10 M11

Figure 3.3: Implementation of the current-steering charge pump.

3.2 Loop Filters

In order to convert the output current of the preceding charge pump into a

voltage whose value is proportional to the pulse width of the control signals

UP and DN of the charge pump, a loop filter consisting of two capacitors C1

and C2 and a resistor R2 is employed at the output of the charge pump, as

shown in Fig.3.1. Note that C2≫C1. C2 and R2 form the main part of the

loop filter. Note that high-frequency sparks can pass through R2−C2 network

and create reference spurs at the output of the oscillator. To minimize this

unwanted effect, a smaller capacitor C1 is used in parallel with R2 − C2 to

filter out the high-frequency sparks.

Construct the schematic of the loop filter and its symbol. The value of

C1, C2, and R2 should be assigned as variables so that they can be tuned

when the phase-locked loop is constructed.

3.3 Open-Loop Test

Construct an open-loop test schematic containing (i) the D-flipflop phase/frequency

detector, (ii) the current-steering charge pump, and (iii) the loop filter de-

sign, as per Fig.3.4. Apply two 900 MHz square waves A and B of the same


oscillation period and duty cycle to the D-flipflop phase/frequency detector.

Let input A lead input B with a phase difference ∆φ. Use parametric anal-

ysis of Cadence to sweep ∆φ and plot the waveform of the output voltage of

the loop filter. Repeat the simulation with A lagging B.

PD

J

JC1

UP

DN

UP

DN

C2

R2

Charge pump

Loop filter

AB Vc

Figure 3.4: Open-loop test circuit.

3.4 Closed-Loop Test

Construct a 4-stage fully differential cross-coupled voltage-controlled oscilla-

tor as per Fig.3.5. The VCO is very similar to the CCO that you designed in

previous laboratories except that the oscillation frequency is now controlled

by a voltage rather than a current. The oscillation frequency of the oscillator

should be in the neighborhood of 900 MHz. Simulate the VCO for a given

control voltage Vc and record the oscillation period (frequency). Make sure

that the oscillation frequency of the oscillator covers 900 MHz.

Construct a test schematic containing (i) the D-flipflop phase/frequency

detector, (ii) the current-steering charge pump, (iii) the loop filter design,

and the 4-stage 900 MHz fully differential cross-coupled voltage-controlled

oscillator as per Fig.3.5. Apply a 900 MHz square wave to the input A of the

phase/frequency detector. The other input of the phase/frequency detector

B comes from the output of your VCO. Plot the waveform of A and B, as

well as the control voltage Vc of the VCO. When a lock state of the PLL


Vin+ Vin-

Vo+Vo-

Vc

Vc

Figure 3.5: Fully differential cross-coupled voltage-controlled oscillator.

is established, the phase difference between A and B should be zero and

the control voltage Vc of the VCO should settle down to a constant value

approximately.

4 Laboratory Report



• The schematic of the charge pump with a boarder section showing your

name and student ID.

• The schematic of the open-loop test circuit with a boarder section show-

ing your name and student ID.


• The response of the open-loop test circuit.

• The schematic of the closed-loop test circuit with a boarder section

showing your name and student ID.

• The response of the closed-loop test circuit at the locked state.

• The waveform of the control voltage Vc of the VCO.

• A table documenting the exact dimension of all transistors used in your

design.

Bibliography

[1] M. El-Hage and F. Yuan, “Architectures and design considerations of

CMOS charge pumps for phase-locked loops,” in Proc. Canadian Conf.

Electrical and Computer Eng., Vol. 1, pp. 223-226, Montreal, May 2003.

26

Chapter 4

Phase-Locked Loop Chip Set


2 Introduction

In this laboratory, you are required to complete the schematic-level design of

a complete chip that contains the phase-locked loop that you designed in the

previous labs. Your design and simulation must take into account the effect

of

• bond pads used for soldering bond wires,

• bond wires used to connect bond pads and traces,

• traces used to connect traces and pins and,

• textfixture used to model the packaging between traces and pins.

3 Models for Packaging

CMC provides many packaging options, depending upon the operation fre-

quencies of the design chips. In this lab, you will use 24 CFP (Ceramic

27

CHAPTER 4. PHASE-LOCKED LOOP CHIP SET 28

Flat Pack), which has 24 pins, a small cavity and is suitable for high-

frequency (up to 4 GHz) designs. CMC has developed a library for both the

package and testfixture for 24 CFP. These files are located in

• Library :

package

• Cellview :

24cfp_140_half_cell, 24cfp_140_test_fixture_half

Note that only a half of the package is provided. You need to make a

copy and rotate it to complete the package. These models are valid up to 4

GHz. CMC requires that all unused pins be grounded. This will increase the

level of signal isolation and improve the performance.

4 Models for Bond Pads

Bond pads are not part of the above package. You need to add bond pads

explicitly in your design to account for their capacitive effect. CMC does

not have bond pad cells developed in package library. CMC requires that

the bond pads must not be smaller than 64µ×64µ. We use 64µ×64µ in this

laboratory. You need to use this value to estimate the parasitic capacitance

of the bond pads. Bond pads should be modeled as a shunt capacitor between

signal path and the substrate. M6 ∼ M5 are to be connected together and

used for the bonding pads. You need to look at the electrical parameter file

of TSMC-0.18µm CMOS technology to find out the capacitance from M5 to

substrate per unit area to estimate the capacitance of the pads.


5 Models for Bond Wires

Bond wires are also not part of the above package. You need to add bond

wires explicitly in your design in order to account for their inductive effect.

CMC has developed a bond wire cell located at

1) Library : package

2) Cellview : bondwire

The bond wires have a diameter of 31.75 µm. The length of the bond

wires depends upon the pin/pad assignment and the location of pads. They

can only be determined once the complete layout is available. For your

simulation, we use the default parameters given in the library (hwl (horizontal

wire length)=2000 µm, d = 31.75µm, r = 0.05Ω,...).

6 Schematics

In order to take into account the effect of bond wires, bond pads, and pack-

aging, you need to add

• Bond pads

• Bond wire cells

• 24cfp_140_half_cell

• 24cfp_140_test_fixture_half

External test devices, such as supply voltage and loads can be connected

directly to the testfixture. The arrangement is shown in Fig.4.1.

7 Laboratory Work

7.1 Complete Test Circuit Construction

Construct the complete test circuit of the designed phase-locked loop. The

test circuit should contain the follows


Your

design

Pad Bondwire

Parasitic cap. of pad

Cavity

Externalvoltagesource

Testfixture

Physical boundaryof CFP chip

Load

Figure 4.1: Simplified schematic of complete chip set

• The phase-locked loop

• The bonding pads.

• The bonding wires.

• The model for the package.

• The model for the testfixture.

• External power supply, ground, and input signals.

7.2 VDD and VSS Pads

To minimize the effect of switching noise, for each VDD and VSS connection

to the outside, four pads/bond wires should be used. The number of pads

are as the followings :


Table 4.1: Pad assignment of phase-locked loop chip set.

Type pf pads Number of pads

VDD pads 4

VSS pads 4

VCO output pads 8

Input signal pad 1

Charge pump control voltage Vcp pad 1

7.3 VCO Output Buffering

To bring the output voltage of the VCO to the outside of the chip, buffers

are needed in order to drive the parasitics of the package and the load. Add

eight voltage buffers to the eight outputs of the VCO (Two inverters are

connected in series with the first inverter of small dimensions. Note that the

first inverter should not be made large. Otherwise, it will load the VCO.).

7.4 PLL Test

Apply a 900 MHz 50% duty-cycle square wave to the input A of the phase

detector. The other input of the phase detector B comes from the output of

your VCO. Plot the waveform of A and B, as well as the control voltage Vc of

the VCO. When a lock state of the PLL is established, the phase difference

between A and B should be zero and the control voltage Vc of the VCO

should settle down to a constant value.

8 Layout of PLL

Once the simulation of the designed PLL is completed and design specifi-

cations are met, it is the time to complete the physical design of the PLL

chipset. Since all of you already have the experience in layout in either

ELE704 or ELE734, you will find this step a rather enjoyable design expe-


rience. Note that you should not make any change to the dimension of all

transistors used in your schematic-level design.

8.1 Floor-Planning of PLL

Before you proceed with the actual layout of the PLL chipset, the first step

that you should do is the floor planning. You MUST make a decision on

critical issues such as (i) where to route your power and ground rails. (ii)

Where to route signals, both low-frequency and high-frequency signals. (iii)

How to isolate high-frequency signals from others. (iv) How to assign I/O

pins. (v) How to ensure that n-wells are properly connected to the most

positive voltage. (vi) Where to put guard rails and how to put the guard

rails. (vii) How to protect dc biasing circuits from noisy digital circuits, (viii)

How to minimize switching noise, and (xi) How to minimize the interaction

between analog and digital circuits of the PLL system.

8.2 Layout of PLL

Once the floor of your PLL is planned, you can proceed with the layout

of each functional block of your PLL. The following guidelines should be

followed in the layout : (i) Try to put all n-wells together. This will reduce

the chip area required for n-wells. Use as many as n+ pull-up connections

as possible for n-wells to ensure that n-well is uniformly connected to the

most positive voltage of the circuit. (ii) Multiple p+ pull-down connections

of the substrate should be used throughout your layout to ensure that the

substrate of your chip is uniformly connected to the ground. (iii) Use as

many as pins/pads as possible for VDD and VSS connections to minimize

the inductance of the bonding wires of VDD and VSS pads subsequently

the switching noise associated with these pads. (iv) High-frequency signals

should be guarded with either ground or VDD rails to minimize their effect

on other parts of the circuit. The bottom line here is to minimize the loop

area of high-frequency signal lines so that their inductance is minimized.


Note that the shielding rails increase the capacitance of the high-frequency

signal lines.

8.3 I/O Pin Assignment

The following guidelines should be followed in the assignment of I/O pads

and pins: (i) Use as many as pads and pins as possible for VDD and VSS

connections to minimize switching noise. (ii) Separate analog pins and digital

pins as far as possible. Often analog pins should be guarded with VSS pins

(shielding pins). (iii) Separate small-signal pins (input pins) and large-signal

pins (output pins) as far as possible to minimize cross-talks from the large-

signal pins to the small-signal pins. You should assign input pins to one

side of the chip and output pins to the other side of the chip to physically

separate them. (iv) Avoid using corner pins and pads. They should be left

as dummy. (v) DC biasing pins and clock pins should be dealt with caution

as the former are high-frequency pins while the latter are analog pins.

8.4 Layout of Pads

Following the design rules of TSMC for pads. Use only M6 and M5 for all

pads to minimize the capacitance from the pads to the substrate.

8.5 Layout of Output Buffers

Output buffers are usually large in size and generate large switching noise and

substrate noise. To minimize their effect, the followings guidelines should be

followed : (i) Use a separate set of VDD and VSS pads and pins for the output

buffers to eliminate the injection of their switching noise to the system. (ii)

Use guard rings to isolate the output buffers from the rest of the system.

Guard ring VDD and VSS should be completely separated from those of the

rest of the system as they carry a high level of switching noise. (iii) Minimize

the length of the interconnects connecting the output buffers and their pads.

Techniques should be used to minimize the inductance of these interconnects.


9 Laboratory Report


at the start of the next week’s laboratory.

• The schematic of the complete test circuit with a board section showing

your name and student ID.

• The response of the closed-loop test circuit at the locked state.

• The waveform of the voltage of all eight outputs of the VCO.

• The waveform of the control voltage Vc of the VCO.

• The complete layout of the PLL chipset.

• The post-layout simulation results of the waveform of the voltage of

all eight outputs of the VCO and that of the control voltage Vc of the

VCO.

ele863 lab manual

Documents