electric circuit (nillson) (7th...
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Electric Circuit (Nillson) (7th edition)Ch1.Circuit Variables1-2 The International system of units1.Derived unit in system of units Unit name(1)electric potential:(2)electric resistance:(3)electric conductance:(4)inductance:(5)energy or work(6)power:
2.Standardizede prefixes to signify power of 10(1)pico(2)nano(3)micro(4)milli(5)centi(6)deci(7)deka(8)hector(9)kilo(10)mega(11)giga(12)tera
1-4 Voltage and current1.voltage:
2.current:單位時間(t)內,通過截面積之電荷
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1-6 Power and energy1.power: 單位時間(t)內,產生或消耗之能量(W)
f.e.1.2.3.
Ch2. Circuit elements2-1 voltage and current sources1.ideal independent voltage source:2.ideal independent current source:3.dependent voltage source:4.dependent current source:
5. active element: a device capable of generate electric energy6.passive element: devices that cannot generate electric energy
2-2 Electrical resistance(Ohm’s law)1.resistance:電流流過導體, 導體產生電壓(V)
2.conductance
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2-3 Construction of a circuit model1.short circuit:
2.open circuit:
2-4 Kirchhoff’s Law1.Kirchhoff’s current law(KCL): algebraic sum of all the currents at any node in a circuit equals zerof.e.
2. Kirchhoff’s voltage law(KVL): algebraic sum of all the voltages around any closed path in a circuit equals zerof.e.
2-5 Analysis of a circuit containing dependent sourcesf.e.
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CH3.Simple resistive circuits3-1 Resistors in series
3-2 Resistors in parallel
f.e.
3-3 The voltage divider and current divider circuits1. voltage divide circuit
2. current divider circuits
3-4 voltage division and current division1. voltage division
2. current division
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3-6 Measuring resistance ----The Wheatstone Bridge目的:測量電阻值
3-7 Delta-to-Wye(Pi-to-Tee) equivalent circuits1.△-to-Y transformation
f.e.
CH4. Techniques of circuit analysis4-1 Torminology1.node2.path3.branch4.loop5.mesh6.essential node(3個以上 branches之 node)7.essential branch(連接 2個 essential node之 branch)8.planar circuit
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4-2 Introduction to the Node-Voltage methodNode-Voltage method:1. find all nodes2. 以最底下之 node 為 ground3. 將 node未知電壓者標上代數4. 依據KCL,寫出 node voltage equations5. 幾個未知數,設幾個 equations,再求解f.e.
4-3 The node voltage method and dependent sourcesf.e.
4-5. Introduction to the mesh current method1.
f.e.
4-6 the mesh current method and dependent sources
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4-10 Thevenin and Norton equivalentsThevenin Theorem:1. 求Vth時:
(1) 移開負載(2) 若無相依電源時,可直接求得若有相依電源時,用KVL或 KCL求得
2.求 Rth時:(1) 移開負載(2) 獨立電壓源------短路, 獨立電流源------斷路, 相依電源-------保留(3) 若無相依電源時-------可直接求出若有相依電源時------ 自己設立Vo和 Io Rth =
VIo
o , 如果仍然無法
求得 Rth, 則將獨立電壓源和獨立電流源恢復再將 load短路得 Isc則 Rth =
VIth
sc
f.e.
4-12 Maximum power transfer
4-13 Superposition: when circuit 具有兩個以上 sources時,可先求出各別 source之response最後再將 all response 相加即為總 response(電壓源視為 short; 電流源視為 open)
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Ch5. The operational amplifier5-1 opereation amplifier terminals1. op的 circuit symbol
2. op的兩種輸入
3. op的 IC接腳圖
5-2 Terminal voltage and current1.negative feedback
2.positive feedback
5-3 The inverting amplifier circuit
5-4 The summing amplifier circuit
5-5 The noninverting amplifier circuit
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CH6 Inductance Capacitance and Mutual Inductance6-1The Inductor1.
f.e.
6-2 The Capacitor1.
f.e.
6-3. Series-parallel combination of inductance and capacitance1. series of inductance
4. parallel of inductance
5. series of capacitance
6. parallel of capacitance
f.e.
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CH7.Response of first-order RL and RC circuits7-1 The natural response of an RL circuit
f.e.
7-2 The natural response of an RC circuit
f.e.
7-3 The step responses of RL and RC circuits1. The step responses of RL circuit
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2. The step responses of RC circuit
7-4 A general solution for step and natural responses
Ch9. Sinusoidal steady-state analysis9-1 The sinusoidal source1.sinusoidal voltage source:隨時間做弦波變動的電壓源2. sinusoidal current source:隨時間做弦波變動的電流源3.period4.phase angle5.frequency6.Hz7.angle frequency8.maximum amplitudef.e.
9.root mean square(rms)
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Millman(第二版)Chapter 1 Semiconductors1-1 Forces , Fields and Energy
(A) charged particles(帶電粒子)在平時狀態下之原子組態:
(1) electron電子: q = m =(2) proton質子:q = m =(3) neutron中子
(B) Field intensity 帶電粒子之運動方程式:
(C) Potential帶電粒子之運動模型
1-2 Conduction in metals(A).mobility(): 帶電粒子在均勻電場作用下: drift velocity:
(B). mobility()與溫度(T)之關係:
(C). Conductivity () 和 Resistivity ()
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1-3 The intrinsic semiconductor(A).intrinsic semiconductor: 由+4價原子所組成之材料
(B).covalent bond:(1)intrinsic semiconductor內之原子與原子,電子與電子間,由於材料之 關係會某種能量互相束縛,而將此種現象等效成共價鍵之作用 o(2)此種束縛能量大小稱為(Energy Gap)Eg(3)共價鍵內之電子稱為:(4)intrinsic semiconductor之帶電模型(00K時,所有電子都在 covalent
bond內,此時沒有自由電子)
(C).Free electron和 hole: 當溫度上升時,共價鍵之能量也上升 o當加於共價鍵之能量超過共價 鍵之能隙(Eg)時,會將共價鍵內之束縛電子拉出,形成 Free electron, 並 在共價鍵內產生 hole效應。 (D). intrinsic concentration (ni ):在常溫下電子濃度與電洞濃度會相等,稱之
(1) electron concentration (n)(2) hole concentration (p)
(3) n,p和 ni 與溫度的關係:
(E).半導體,導體,絕緣體分別:(1) 從關點:(2) 從 Eg關點:
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1-4 Extrinsic semiconductors(A) n-type semiconductors﹝donor impurity﹞﹝n-type impurity﹞
由+5價原子與 Si合組成之半導體磷(Phosphorus)砷(Arsenic)銻(Antimony)
施體雜質濃度﹝ND﹞(B) p-type semiconductors﹝acceptor impurity﹞﹝p-type impurity﹞
由+3價原子與 Si合組成之半導體硼(Boron)鎵(Gallium)銦(Indium)
受體雜質濃度﹝NA﹞
(C) The mass-action law 在半導體內任何位置之 np乘積為定值
無論有無雜質都成立(D) minority carrior majority carrior
n-type semiconductors p-type semiconductorsmajority carriorsminority carriors
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(E) Carrier concertration(1) 電荷密度公式利用混雜前和混雜後之正電荷=負電荷
(2) 半導體濃度問題分析(i) 精確解法:
step1.ND + p = NA + nstep2.np = ni
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step3.聯立 step1 和 step2 求得 n 和 pstep4.σ= nqun +pqup
f.e.
(ii)近似解法:
f.e.
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1-6 Diffusion(A) 由來:電子電洞由濃度高處往濃度低處移動時所產生之電流現象(B) Diffusion電流公式推導
(C) 半導體中之二種電流現象:擴散電流現象:
漂移電流現象:
總電洞流:
總電子流:
總電流:
(D) Einstein relationship
1-7 Graded semiconductors(A) Boltzmann equation濃度不一樣,但不會擴散
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(B) mass action law (由 Boltzmann equation證明)(C) Contact potential ﹝Millman﹞
Barrier potential ﹝Smith﹞ step-graded junction濃度均勻之 p-type與 n-type 接面
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Chapter 2 The pn Junction Diode2-1 The open-circuited Junction(A) pn junction
p-type表示法: n-type表示法:
中央產生:﹝depletion region﹞﹝transition region﹞﹝space-charge region﹞
(B) The depletion region
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2-2 The Biased pn junction(A) the Forward-Biased pn junction (F.B.)
(B) the Reverse-Biased pn junction (R.B.)Is:reverse saturation current
(C) Ohmic contacts﹝Millman﹞, Metal contacts ﹝Smith﹞高濃度的 p或 n與金屬接觸→形成小電阻值
2-3 The voltage-ampere characteristic(A) junction diode
(B) the effect of nf.e. Determine the change in diode voltage corresponding to a 10:1 change in ID for T=3000K
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2-4Temperature dependence of the V-I characteristicIs與溫度的關係:T↑100C Is加倍 or T↑10C Is↑7%
2-5 Germaium diodesn值與 Si和Ge的關係:
2-10 Junction-Diode switching time
(1) ts(storage time)儲存時間正負電荷至未加偏壓狀態之時間(2) tt(transition time)過渡時間排除空乏區外側正負電荷由未加偏壓到逆向
偏壓之時間(3)trf(forward recovery time)順向恢復時間二極體外加電壓由 R.B.到 F.B.二
極體兩端電壓由 10%上升到 90%之時間
(4)trr(reverse recovery time)逆向恢復時間 二極體外加電壓由 F.B.到 R.B.時通過二極體之電流減少到反向飽和電流(Is)之時間
trr= ts+ tt (約 1n second ~ 1u second)
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2-11 Zener diodes(A)avalanche breakdown
(1)崩潰原因:當 R.B.增加時,逆向電場強度也增加使得 free electron 之逆向速度也增加, 速度增加亦即動能也增加,當 free electron之動能超過其共價鍵之 Eg,則會以累增的方式將共價鍵之束縛電子撞出,形成 free electron,而產生全面崩潰現象 o
(2)Vz(崩潰電壓)之大小(3)Vz與溫度之關係
(B)Zener breakdown(1) 崩潰原因:當 R.B.增加時,逆向電場強度也增加使得逆向力增強,當逆向力超過其共價鍵之 Eg,則會強力將共價鍵之束縛電子拉出,形成 free electron,而產生全面崩潰現象 o
(2) Vz(崩潰電壓)之大小(3) Vz與溫度之關係
(4) avalanche breakdown與 Zener breakdown同時存在if Vz > 7V:
if Vz < 5V:
2-12 Schottky barrier diode(D)符號:(E) 材料
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(F) 主要電流成份:(G)用途:Smith(第五版)CH3 Diodes3-1 The ideal diode
1. current-voltage特性曲線:
(1) 順向偏壓 forward-biased, turned on, on (V > 0)(2) 逆向偏壓 reverse biased, cut off, off (V < 0)(3) Anode Cathode
2. diode logic gates:(1) OR gate
(2) AND gate
3-2 Terminal characteristics of junction diodes1. 特性曲線:
三個工作區域: I 區
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II 區 III 區2. The forward-Bias region
(1) n:
(2) VT = (thermal voltage)
K: Boltzmann’s constantT: the absolute temperatureq: the magnitude of electronic charge
(3) IS: (saturation current, scale current)每上升 50C 加倍
f.e.1: If i=1mA, VT = 25mV, forward voltage V = 0.7V Find: (1) n = 1, IS = ? (1) n = 2, IS = ?
(4) 二極體兩端電壓(V)與電流之關係:
f.e.:劃出(1) T1 = 3000 K, (2) T1 = 3500 K,之 I-V 曲線
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(5) Vr :
3. the Reverse-Bias region
4. the Breakdown Region
3-5 Rectifier circuit1. The Half-wave rectifier2. TheFull- wave rectifier3.The Bridge rectifier
3-8 Special diode types1. The Schottky-Barrier Diode (SBD)
2. Varactors
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3. Photodiodes(1)符號:
(2)偏壓方式:
(3)特性:讓光照空乏區之束縛電子即可釋出而形成電流4.Light Emitting Diode (LED)(1)符號:
(2)偏壓方式:
(3)特性:電子電洞結合以光方式釋放能量
Chapter 5 Bipolar Junction Transistors (BJTs)
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5-1 Device structure and Physical operation1. Simplified structure and modes of operation:(1)物理結構:
(2)濃度比:
(3)寬度比:
(4)工作modes:
(5)工作組態:
2. Operation of the npn and pnp transistor in the active mode(1) 作用區電流方程式:
(i) CB組態的電流方程式:
(ii) CE組態的電流方程式:
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(iii) 與 之互換
(iv) 增加 之方法:
5-2 Current-voltage characteristics1. Circuit symbols and conventions
f.e.
2. Graphical representation of transistor characteristic
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(1) CB 組態之輸入特性曲線 (pnp) 由 vBC 控制 iE -vBE曲線
(2) Early effect (Base-width modulation effect) BJT工作在 active region 必須保持 Jc在 R.B.狀態,利用 Jc 逆偏電壓大小來 調變有效基極寬度之效應稱之 o
(3) CB 組態之輸出特性曲線 (pnp) 由 iE(vEB) 控制 iC-vBC曲線
(4) CE 組態之輸入特性曲線 (npn) 由 vCE 控制 iB-vBE曲線
(5) CE 組態之輸出特性曲線 (npn) 由 iB(vBE) 控制 iC-vCE曲線
5-3 The BJT as an amplifier and as a switch
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CC組態: 多級串接放大器之輸入端與輸出端用之(當緩衝用)CE組態: 中級用之(當放大用)CB組態: 高頻響應用(當寬頻用)1. Graphical analysis (cut-off region and saturation)
5-4 BJT circuit at DC一 電晶體直流分析的目的:找出工作點方法一:可立即判斷出工作在何區判斷方法:if JE 逆偏 BJT在截止區或反向作用區;
if JE 順偏 (Vpn Vr)則必須看 Jc :if Jc 逆偏(Vpn Vr) 作用區;if Jc 順偏 (Vpn Vr) 飽和區二 如果 BJT在作用區其分析方法:
1. VBE Si = 0.7V, Ge = 0.2V2.Ic = IB + ( 1 + ) Ico
3.取含VBE之 loop equation4.解得Q ( IBQ, ICQ, VCEQ)三 如果 BJT在飽和區其分析方法:1. VBE Si = 0.8V, Ge = 0.3V2. VCE Si = 0.2V, Ge = 0.1V3.取含VBE之 loop equation4.取含VCE之 loop equation5.聯立 3和 4, 解得Q ( IBQ, ICQ, VCEQ)
四 如果無法判斷出工作在何區, 可先假設工作在作用區, 最後再驗證五 如果為多電源時,則先化成 Thevenin等效電路,變成單一電源後再用 1或 2的方法求解!
5-6 Small-signal operation and models
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二階model 一階model T-model推導與例題5-7 Single-stage BJT amplifiersCE CB CC組態例題BJT的 small-signal分析要領:1. DC analysis得工作點Q(IB IC VCE) gm,rπ,re和 ro值2. DC電壓源視同 -----short; DC電流源視同 -----open Coupling capacitance 和 Bypass capacitance DC analysis視同 ---open AC analysis視同 ---short3. <1> 已知VA, ro ,值時用二階mode
<2> 沒有VA, ro ,值時用一階mode<3> CE 有旁路電阻但無旁路電容 用 T-mode;有密勒阻抗用一階mode<4> CB 用 T-mode<5> CC 用 T-mode<6> 差動放大器用 T-mode
4. 用KVL KCL分析, 求Av , AI , Rin , Rout
5.Coupling capacitance and Blocking capacitance 之功能 直流分析:open的效應,用以阻隔直流訊號至輸入端和負載端,形成單一級之
直流偏壓電路以利於工作點之分析! Small-signal:short的效應,使得輸入訊號直接傳到放大器,並在已建立好之
工作點上放大,而再直接傳到負載端!
6.Bypass capacitance.之功能 直流分析:open的效應,以源極電阻來匹配最佳工作點 Small-signa分析:short的效應,使得源極之電阻效應為零,而可得到最大電
壓增益!
CH4 Field-Effect Transistors (MOSFETs)
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FET: (1) MOSFET (金氧半場效體) 又名: insulated-gate FET (IGFET)強調G端與 Body被 oxide 隔離 (2) JFET
優點: 1.high input impedance 2.small size(one chip can include 100,000 MOSTEF) 3.low power dissipation 4.ease of fabrication 5.可取代電容和電阻,所以可只用MOSTEF合成系統(system)
4-1 Device Structure and Physical Operation 1. Device structure
2. 正常工作時:(1) IG=0 (2) 保持 Body 對 chennel逆偏 (3) VGS 必須保持順偏以吸引 Body之電子而形成 channel
3. 輸出特行曲線(iD – vDS)
4. Applying a small vDS (vDS very small)
5. Operation as vDS is increased (vDS not small)
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Vt (threshold voltage)足以形成 channel之最小VGS 順偏電壓值﹝一般約: 0.5V ~ 1V﹞
When vGD= vt (1) D-S channel 幾乎無法形成 (2) JD = ,
6. 分為三區(I) 區:triode region
(II) 區:saturation region or pinch-off region
(III) 區:cutoff region
7. NMOS:PMOS:CMOS:
4-2 Current-Voltage characteristics(The Enhancement-type MOSFET) 1. circuit symbol ( n-channel)
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2. iD-vDS characteristics(1) rDS值
(2) ro值
3. characteristic of the p-channel MOSFET(1) triode
(2) pinch-off
(3) circuit symbol
4.Body effect of substrate (基體效應) ﹝channel-length modulation﹞ MOS正常工作時必須保持 B端對 channel逆偏,此時 B端對 S端之逆偏電壓
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大小會對 channel寬度有所影響,此現象稱之 o(1) body effect 會使 channel之有效寬度變窄, 所以 vt 必須 , 所以必須再使 vGS ,才能使 channel導通(2) vt 與 vSB 關係 (vSB : B端對 S端之逆偏電壓絕對值)
(3) 消除 body effect之方法 let vSB= 0﹝即 B端對 S端 short﹞
5. Breakdown and input protection
(1) when B端對D端之逆偏電壓大於崩潰電壓(VZK)時, iD會瞬間變大稱為 punch-through, 一般約 20 V(無破壞性)(2) when vGS > 50V, 會將 oxide 層打破 o(有破壞性) 解決方法:在 B端與G端加上 Zener diode以限制 vGS < 50V
4-11 The Depletion-type MOSFET1. Depletion Metal-Oxide-Semiconductor FET (DFET)
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(1) Device structure (n-channel)
(2) circuit symbol
(3)輸出特行曲線(iD – vDS)
(i) Applying a small vDS (vDS very small)
*VP:使得空乏區佔滿 channel iD= 0 之最小 vGS的逆偏電壓值(約 –4V)*when 外加逆偏電壓被排除時, 被排除之電子又會回到原處(ii)Operation as vDS is increased (vDS not small)
35
When vGD= vP (a) D端的空乏區有能力佔滿 channel (b)
(iii)電流方程式: (同 EMOS) (iv) P-channel DMOS PMOS circuit symbol
(v)NMOS 與 PMOS比較(a)相同電場下, NMOS為 PMOS速度 2倍 (b)相同電壓(同 iD)下, PMOS為NMOS面積 2倍
5-3 MOSFET circuit at DC1. EMOS的直流分析:Step1.判斷出工作在何區, VGS Vt cut-off Vt VGD Vt : pinch-off VGD Vt : triode
Step2.列出 iD equation , if at pinch-off region iD = 12 kn’ (
WL ) (VGS Vt)2
Step3.列出含VGS之 loop equationStep4.聯立 2和 3 , 消去 iD得VGS之一元二次 equation ,取大於Vt值者為VGSq
Step5.得Q (IDQ, VGSQ, VDSQ)
5-7 Basic configuration of single-stage IC MOS amplifierA. three basic configuration
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CS CD CG
共用端輸入端輸出端
B. MOS的 small-signal分析:1. DC analysis得工作點Q gm和 ro值2. DC電壓源 -----short DC 電流源 -----open Coupling cap. and Bypass cap. DC analysis ---open AC analysis ---short3. <1> 已知VA, ro , 值時用二階mode
<2> 沒有VA, ro , 值時用一階mode<3> CS 有源極電阻但無旁路電容 用 T-mode 有密勒阻抗用一階mode<4> CD 用 T-mode<5> CG 用 T-mode<6> 差動放大器用 T-mode
4. 用KVL KCL分析, 求Av , AI , Rin , Rout
5-9 The MOSFET as an analogy switch1. NMOS switch 與 CMOS switch 比較
控制訊號與輸入訊號 通道電阻(rDS) 組成NMOS 不同位準 隨訊號而變 NMOSCMOS 可為同位準 不變 NMOS與
PMOS
5-11 The Junction FET (JFET)1. Device structure
(1) 工作原理:利用第三端(Gate)的外加電壓產生 pn接面的電場效應,進而控制 另兩端(D端與 S端)通道的大小 o(2) 物理結構:
(3) circuit symbol2. 輸出特行曲線(iD – vDS)
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(1)正常工作, vGS為逆偏(2)Applying a small vDS (vDS very small)
* VP:使得空乏區佔滿 channel iD= 0 之最小 vGS的逆偏電壓值(約 –4V)(3) Operation as vDS is increased (vDS not small)
When vGD= vP (a) D端的空乏區有能力佔滿 channel (b)
3. 電流方程式:4. JFET 的直流分析:Step1.判斷出工作在何區, VGS Vp cut-off Vp VGD Vp : pinch-off VGD Vp : triode
Step2.列出 iD equation , if at pinch-off region iD = IDSS [1-( )]2
Step3.列出含VGS之 loop equationStep4.聯立 2和 3 , 消去 iD得VGS之一元二次 equation ,取介於 0~Vp值者為VGSq
Step5.得Q (IDQ, VGSQ, VDSQ)
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