E. Pop

Electronics and Energy Applications of 1D and 2D Nanomaterials

Eric PopElectrical Engineering (EE) and Precourt Institute for Energy (PIE) Stanford University

http://poplab.stanford.edu

1

E. Pop

• Alumni:– Prof. D. Estrada, Drs. Z.-Y. Ong, A. Liao, J. Wood, Z. Li,

V. Dorgan, F. Xiong, Z. Li, E. Carrion, S. Islam, K. Grosse

– 8 M.S. and 10 B.S. theses

• Post-docs:– Feng Xiong, Yong Cheol Shin, Eilam Yalon, Miguel Munoz

• Grad students:

– C. English, F. Lian, S. Deshmukh, S. Bohaichuk

– M. Mleczko, C. Neumann, I. Datye, M. Chen, A. Gabourie

– K. Smithe, S. Suryavanshi, N. Wang, R.L. Xu, C. McClellan

• Undergrads:– Andrew, Tim, Job, Justin, Yeshar, Erin

• Sponsors:– National Science Foundation (NSF), Army Research Office (ARO)

– Air Force (AFOSR), Intel, STARnet-SONIC, SystemX Alliance

• Collaborators:– Z. Bao, K. Goodson, S. Mitra, Y. Nishi, E. Reed, K. Saraswat, H.-S.P. Wong (Stanford), D. Cahill, W. King,

J. Lyding, J. Rogers, M. Shim (UIUC), M. Rudan (Bologna), C. Jacoboni (Modena), M. Hersam (NWU), I. Knezevic (Wisc.), D. Jena (Cornell), D. Ielmini, R. Sordan (Milano), J. Shiomi (Tokyo)

Acknowledgements

2

http://poplab.stanford.edu

E. Pop

What Motivates Us

3

20 Watts

200 kiloWatts

(IBM Watson, Jeopardy! champion)

10,000x

(conventional Moore’s Law size scaling can get us ~10x)

E. Pop

Electronics Use (and Waste) Much Power

4

http://phys.ncku.edu.tw/~htsu/humor/fry_egg.html

1

10

100

1990 1994 1998 2002 2006 2010

AMD

Intel

Power PC

CP

U P

ower

Den

sity

(W

/cm

2)

Year

Pentium 4(2005)

Core 2 Duo(2006) Atom

(2008)

Single CPU?

energy limits performance from processors, to mobile devices, to data centers

Single Processor?E. Pop, Nano Research 3, 147 (2010)

new course: Energy in Electronics, EE 323 (Fall 2014)

Limited by power & heat since 2005!

~exp

E. Pop

Electronics Use (and Waste) Much Power

5

Calibrating: 1 GW ~ 1 nuclear power plant12 GW ~ all electricity used by Argentina

1

10

100

1990 1994 1998 2002 2006 2010

AMD

Intel

Power PC

CP

U P

ower

Den

sity

(W

/cm

2)

Year

Pentium 4(2005)

Core 2 Duo(2006) Atom

(2008)

Single CPU?Single Processor?

US data center*power use (GW)

*World-Wide about 30 GW

J. Koomey (Stanford)

E. Pop, Nano Research 3, 147 (2010)new course: Energy in Electronics, EE 323 (Fall 2014)

E. Pop

Our Work: Two Sides of the Same Coin

Lower power at its source

(devices, sensors, circuits)

6

Harvest and manage heat

(energy, thermoelectrics)

fundamental understanding

practical applications

E. Pop

Outline of Talk

• The SystemX Alliance at Stanford

• Transistors

– Heterogeneous integration of beyond-Si materials

• Data Storage

– Approaching limits of phase-change memory

• Thermal Energy at Nanoscale

– Ballistic heat flow and fundamental limits

7

E. Pop

What Is the SystemX Alliance at Stanford?• Center for Integrated Systems (CIS) SystemX Alliance

– Industry-academic Alliance to repositioned for 21st century research

– Become “the” hub for electronic research at Stanford

• What’s New?– Stronger emphasis of top-down, systems research

– Introduce focus areas to create coherent thrusts

– Additional sponsor benefits including workshops, E-Seminars

8

E. Pop

Value Proposition for Industry Sponsors• See everything that is going on at Stanford

– Real-time view of all faculty research, including NSF, DARPA, etc. activities

– Student recruiting, internships, and networking

• Participation in Focus Area research

– Invitation-only attendance to bi-annual workshop & discussion

• Customized Fellow-Mentor-Advisor (FMA) projects

– Company-specific research performed by student & advisor with industry mentor

• Faculty liaisons, company visits, and weekly E-Seminars

9

E. Pop

SystemX Focus Areas

• Focus areas change dynamically and have finite life-cycle (~3-5 years)

10

E. Pop

Heterogeneous Integration Focus Area• Heterogeneous Integration of Everything onto Anything (HIEA)

• Integration of “beyond-Si” platforms for “beyond Moore” applications– Monolithic integration of logic, memory, sensors, thermal management, flexible substrates

– Energy-efficient and brain-inspired design opportunities

– Autonomous electronics and energy-harvesting opportunities

• Core faculty: E. Pop, H.-S.P. Wong (co-leads), J. Fan, K. Goodson, S. Mitra, Y. Nishi, J. Plummer, K. Saraswat, D. Senesky, X. Zheng

11

E. Pop

Outline of Talk

• The SystemX Alliance at Stanford

• Transistors

– Integration of electronics based on 2D materials

• Data Storage

– Approaching limits of phase-change memory

• Thermal Energy at Nanoscale

– Ballistic heat flow and fundamental limits

12

E. Pop

Transistors Beyond Silicon?• Problem: 20th century transistors “carved” out of 3D materials (Si)

surface roughness restricts mobility, band gap, variability

13

roughness

tch

tch (nm)1 2 3 40

10

102

µ(c

m2 V

-1s-1

)

104

103

SOI

0.3 1 10 1000

0.5

1

1.5

2

2.5

GaAs

Si

Ge

InAs

InSb

tch (nm)

±1 atomic layer

EG

(eV

)

3D

E. Pop

Transistors Beyond Silicon?• Problem: 20th century transistors “carved” out of 3D materials (Si)

surface roughness restricts mobility, band gap, variability

• Solution? 21st centuryatomically thin materials

14

roughness

tch

1 2 3 40

10

102

104

103

CNTsgraphene

SOI

MoS2

WSe2

0.3 1 10 1000

0.5

1

1.5

2

2.5

GaAs

Si

Ge

InAs

InSb

±1 atomic layer

2DTMDs

1DCNTs

tch (nm)

µ(c

m2 V

-1s-1

)

tch (nm)

EG

(eV

)

<1 nm

1 nm

1D carbonnanotube (CNT)

2D TMD (MoS2,WTe2, ZrSe2)

3D

E. Pop

Beyond-Silicon 2D Materials

15

CVD growth of graphene, BN and MoS2

20 µm

ZrSe2 HfSe2

monolayer MoS2

A1g 194 cm-1

100 200 300 400Raman Shift (cm-1)

Inte

nsi

ty (

a.u

.)

10 µm

WTe2 (metallic)

MoTe2

BN

CVT growth of MoTe2, WTe2, ZrSe2, HfSe2

50 100 150 200 250 3000

0.5

1

1.5

2

2.5

3

3.5

4x 10

Raman Shift (cm-1)

Inte

ns

ity

(a.

u.)

~ ~~ ~

~ ~

3-6 Layer

Bulk

WTe2

exfoliate

collab. H.S.-P. Wong, Y. Nishi, I. Fisher

E. Pop

Heterogeneous Integration Progress

16

Monolithic 3D: low‐temperature 3D integration of CNT logic and RRAM memory on CMOS substrate

source: Shulaker, Wong, Mitra (IEDM-2014) source: K. Smithe (Pop Lab, 2015)

Wet or Dry Transfer: layer transfer of 2D monolayers onto insulators while preserving the electronic properties

Cu-assisted Dry Transfer

CuSiO2/Si SiO2/Si

CuCuSiO2/Si

New substrateCu

New substrateCu

MoS2Thermal Release Tape

CuSiO2/SiNew substrate

Cu etch

heat

peel

pressure

Cu

graphene

Cu

PMMA

Cu

PMMA

Cu etch

PMMA

PMMA-assisted Wet Transfer

PMMA

New substrate New substrate

acetone

E. Pop

Band Gaps (EG) of Several 2D Materials

• Low-EG but high mobility high-speed and RF applications

• Medium-EG (0.3 to 1.1 eV) low-power CMOS

• High-EG power devices

17

EG 0 eV 1 eV 2 eV

Graphene

Ge 0.67 eV Si 1.11 eV GaAs 1.42 eV

Black Phosphorus0.3 eV (Bulk) 1.1 – 1.9 eV (1L) Low-Power CMOS

~0.5-1.2 eV

Layered Insulatorsh-BN

WSe2, WS2, MoS2~1.4 – 1.8 eV 1L

High-Speed / RF Power Devices

courtesy of M. Mleczko (Pop Lab)

E. Pop

Early Work: Graphene Transport Parameters

18

• Lack of transport data* at T > 300 K and high-field vsat (>1 V/μm)

• High-field vsat measurement is tricky, needs constant field

• Also extracted practical electrical and thermal compact models

0 B ox SiT T T P R R R

V. Dorgan, M.-H. Bae, E. Pop, Appl. Phys. Lett. 97, 082112 (2010)

0 1

( , )1 / 1 / 1ref ref

n Tn n T T

300 400 5002500

3000

3500

4000

4500

5000

T (K)

(c

m2 /V

s)

5x1012 cm-2

n = 2x1012 cm-2

0 3 6 9 12 150

1

2

3

4

n (1012 cm-2)

v sat (

107 c

m/s

)

(c)ω

(a)

vsat,Si

vsat,Ge

(b)

2

2

2 1( , ) 1

4 1OP OP

satF OP

v n Tnv Nn

ωOP/vFkx

ky

*J.-H. Chen, Nature Nano (2008); W. Zhu, PRB (2009); I. Meric, Nature Nano (2008)

E. Pop

mobility = characterizes “ease” of current flow in a material; e.g. I nμE

Graphene Mobility – Where Does it Stand?

suspended graphene(T=230 K)

InSb

Si

Ge

graphene on SiO2

graphene on BN

T = 300 K

19

E. Pop

Today: Graphene-Based Functions and Systems• Goal: graphene switched analog circuit (SAC). Why?

• Graphene = nanofabrics with high mobility (~10x > Si), flexible…

• SAC tolerates low Ion/Ioff ratio (~5x) of graphene (no band gap)

• Breakthroughs in heterogeneous integration of graphene & CMOS

20

4” AixtronBlack Magic

System

Growth Chamber

E. Pop

Graphene Dot Product (GDOT) Nanofunction

• Dot product nanofunction used for image processing, neural networks…

• Takes advantage of native graphene properties, tolerates drawbacks

21

N. Wang, S. Gonugondla, I. Nahlus, N. Shanbhag, E. Pop, VLSI Symp. (2016)

1500300

15030

15

1.22.2

3.54.2

6.758

10.512.5

0

5

10

15

Err

or [%

]

1500300

15030

15

1.22.2

3.54.2

6.758

10.512.5

0

5

10

15

Err

or

[%]

Gaussian blur filter with σ2 = 0.85

-40

-35

-30

-25

-20

-15

-10

-5

0

180 nm CMOS 1 µm GFET

Noise [dB]

+ Fast+ Smaller area+ Low noise- Narrow input range

+ High accuracy+ Wide input range- Slow and noisy- Larger area

Idea: Simulation:

R’

C’

Φ1

Φ2

ΦN

Vout

R’C’ ≫ max(T,τFET)

Vx

V(t)

V1

V2

VN

Vout

t

T

Φ1(t)

Φ2(t)

TON,2

ΦN(t)

TON,N

TON,1

V1

V2

VN

t

t

t

weights encoded by pulse widths piT

E. Pop

… and Implementation

22

Test Structures

GDOT

RF

Cap TLM

Calib

RFCap

RF TLM

MOScaps MIMcap

4” Wafer Prototype Die

GDOT

E. Pop

CVD Growth of Monolayer MoS2

23

PTAS: perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt

90 nm SiO2/Si (p++)

Continuous, mostly 1L MoS2

optical

P = 760 TorrT = 850 oC

Y.-H. Lee, et al., Nano Lett. 13, 1852 (2013) Y.-H. Lee, et al., Adv. Mater. 24, 2320 (2012)

Kirby Smithe (Pop Lab)

E. Pop

Digital Electronics Monolayer CVD MoS2

• Large-area monolayer CVD MoS2, direct band gap ~1.8 eV

• Wish to scale up devices for low-power digital electronics

24

K. Smithe, C. English, S. Suryavanshi, E. Pop, Device Research Conf. (2015)

Good current achieved (~275 µA/µm) in 80 nm device, but contact resistance remains dominant

monolayer MoS2

E. Pop

Scaled Semiconducting MoS2 Transistors

25

Source: C. English, G. Shine, K. Saraswat, E. Pop, Nano Lett. (2016)

• Demonstrated how contacts are limiting the performance of small MoS2 transistors

• Built devices with ~40 nm channel length and variable contact sizing (LC = 20 to 100 nm)

• Smallest MoS2 transistor with smallest contacts to date (contacted gate pitch CGP ~ 70 nm, smaller than “22 nm” Si technology from Intel and Samsung

Goal: Aggressively scale 2D transistors (e.g. MoS2) for ultra-low power digital electronics

E. Pop

Metal Contacts to MoS2 (Clean but Undoped)

• Contacting 2D materials is difficult

• Cleaner Au deposition (~10-9 torr) leads to improved contact resistance

– RC ~ 740 Ω∙μm and ρC ≈ 4 x 10-7 Ω∙cm2

26

0 250 500 750 10000

20

40

60

80

L (nm)

RTO

T (k

m)

2RC

5 µm

WL

d

VD

VG

0 2.5 5 7.5 100

2.5

5

7.5

10

n (1012 cm-2)

RC (

k

m)

Sc2

Ti

this work

Au

Au

Au1 10-9 torr

Dep. Press.10-6 torr

Ni1

C. English, G. Shine, V. Dorgan, K. Saraswat, E. Pop, Device Research Conf. (2014)

MoS2

1H.Liu & P. Ye (2013), 2S. Das & J. Appenzeller (2013)

Transfer Length Method (TLM)

E. Pop

0 0.5 1 1.5 2 2.5 30

2

4

6

8

Drain Voltage (V)

Dra

in C

urr

ent (

µA

/µm

)

WTe2

Ag

Ag

WTe2

2D Contacts to 2D Transistors

• WTe2 (2D metal) contacts to WSe2 (semic.)

• Residue-free transfer process

• 2x improvement over Ag contacts (“best known”)

• Observed current saturation

27

C. McClellan, M. Mleczko, Y. Nishi, E. Pop, Device Research Conf. 2016

SiO2/p++ Si

SiO2/p++ Si

WSe2

SiO2/p++ Si

WSe2

PDMSWTe2 WTe2

PDMSWTe2 WTe2

PDMSWTe2 WTe2WSe2

−10 −5 0 5 10 15

0

1

2

3

4

Gate - Threshold (VG-V

T) (V)

Dra

in C

urre

nt (

µA

/µm

) Drain Voltage = 1 V

E. Pop

Summary of Challenges in 2D Devices

28

Material Quality:

Contact Resistance (RC):

SiO2 (90 or 300 nm)

Si (p++)

VD VSVTG

VBG

L

W

Metals

Oxide

Graphene

Si (p++) VBG

LT

Metals

Si (p++)

High-κ

Substrate

Graphene

VBG

SiCGrowth

CVD[2][1]

Interfaces:

o Pre vac. annealo Post vac. anneal

tOFF

VD

VTG

tON,TGtON,D

Rprobe

RL

50 Ω

VP VTG

GFET

VD

VS

CprobeCpad

Scope

-8 -4 0 4 80.4

0.8

1.2

1.6

VTG [V]

R [

K

]

DC

tON,TG = 100 µs

= 10 µs

= 400 ns

(air)

(b)

0 100 2000

0.5

1

1.5

Time [ns]

V [

V]

d

tON,D

tON,TG

+Variability!E. Carrion, E. Pop et al, IEEE TED, 61, 1583 (2014)

E. Pop

Outline of Talk

• The SystemX Alliance at Stanford

• Transistors

– Integration of electronics based on 2D materials

• Data Storage

– Approaching limits of phase-change memory

• Thermal Energy at Nanoscale

– Ballistic heat flow and fundamental limits

29

E. Pop

Phase-Change Memory (PCM) Materials

• Chalcogenide compound: Ge2Sb2Te5 (GST)

• Used in RW-DVDs

• Crystalline vs. amorphous: fast phase change (~1 ns)

• Large change in resistance (>100x)

• Promising candidate for memory, BUT… high programming current(~0.1 mA at IBM, Intel, Samsung)

30

Rcrystalline << Ramorphous

Kolobov et al. Nature Materials (2004)Lee et al. Nature Nano (2007), Chen and Pop IEEE-TED (2009)

switching induced by Joule heating

E. Pop

Phase-Change Memory with CNT Electrodes

• Key idea: CNTs are smallest possible electrodes (1-2 nm diameter)

• Use CNT to contact sub-10 nm bits of phase-change material

• Switching at ~100x lower power than conventional PCM!

F. Xiong, A. Liao, D. Estrada, E. Pop, Science 332, 568 (2011)

31

carbon nanotube

(CNT)

also see. J. Liang, H.-S.P. Wong, et al., IEEE-TED (2012)

E. Pop

Self-Aligned Nanotube-Nanowire Devices

nanogapCNT covered

by PMMA

nanotrenchin PMMA

self-alignedGST nanowire

• “Marshmallow” memory bit optimized for thermal confinement

• PCM nanowire self-aligned with CNT electrodes

• Excellent ROFF/RON ratio (> 1000) approaches intrinsic GST limits

F. Xiong, M.-H. Bae, Y. Dai, A. Liao, A. Behnam, E. Carrion, S. Hong, D. Ielmini, E. Pop, Nano Lett. 13, 464 (2013)

32

~ 40 nm

CNT

PCMnanowire

0 2 4 6 80

0.2

0.4

0.6

0.8

1

V (V)

I (

A)

1st VT

10th VT

100th VT

0 2500 5000 7500 1000010-1100101102103104105

Time (s)

R (

M

)

AmorphousCrystalline

crystalline

amorphous

~2000

E. Pop

We Can Also Use Graphene Electrodes

• Graphene “edge” electrode enables sub-10 µA Ireset

• Heterogeneous integration challenges

33

A. Behnam, F. Xiong, E. Pop et al., Appl. Phys. Letters. 107, 123508 (2015)C. Ahn, S.W. Fong, Y. Kim, S. Lee, A. Sood, C. Neumann, K. Goodson, E. Pop, H.-S.P. Wong, Nano Lett. 15, 6809 (2015)

Lateral Device Vertical Device

• Graphene as ultra-thin thermal barrier to block PCM heat loss

• 40% lower Ireset than control devices

0 5 100.0

0.5

1.0

1.5

2.0 ON State Sweeps SET Sweeps

Cur

rent

A

)

Voltage (V)

(a)VT

IT

0 50 100 150 200

1

10

100

Time (sec)

OFF

ON

R (

kΩ·µ

m)

E. Pop

Where These Results Fit In

34

• These devices are highly scalable with electrode and bit size

• Lowest power <1 μW, energy <1 fJ/bit (with ~1 ns pulse)

• Have not hit fundamental limits yet (~10-100x lower… 1.2 aJ/nm3)*

*review: S. Raoux, F. Xiong, M. Wuttig, E. Pop, MRS Bull. (2014)

this work, withCNT electrodes

HSP Wong et al, Proc IEEE (2010)ITRS 2010

E. Pop

Outline of Talk

• The SystemX Alliance at Stanford

• Transistors

– Integration of electronics based on 2D materials

• Data Storage

– Approaching limits of phase-change memory

• Thermal Energy at Nanoscale

– Ballistic heat flow and fundamental limits

35

E. Pop

2D Material Thermal Properties

• Large in-plane thermal conductivity of graphene, BN (>500 W/m/K)

• Ultra-low cross-plane thermal conductivity of layered WSe2 (<0.1 W/m/K)

– Lower than plastics and comparable to air

• Huge thermal anisotropy in all layered 2D materials (>10-100x)

• MRS Bulletin review with AFRL:

• Large thermopower in TMDs (S ~ 0.5 mV/K) Thermoelectrics?

36

E. Pop, V. Varshney, A.K. Roy, "Thermal Properties of Graphene: Fundamentals and Applications," MRS Bulletin 37, 1273 (2012)

2S TZT

k

E. Pop

Thermal Conductivity (κ) of 2D Materials

• Flexural phonon modes play important role in 2D materials

• Anisotropy: κ|| from ~6 Wm-1K-1 (WTe2) to ~2000 Wm-1K-1 (graphene)

– Cross-plane κ is typically very small, e.g. 1 to 6 Wm-1K-1

37

E. Pop, V. Varshney, A. Roy, MRS Bull. 37, 1273 (2012); Table courtesy of Z. Li (Pop Lab)

κ(W

m-1

K-1

) susp

en

de

d

GN

Rs

T ~ 300 K

WS

2

MoS

e 2

blac

k ph

osph

orus

h-B

Nsup

po

rte

d

en

case

d

gra

phite

h-B

N

MoS

2

WS

e 2

MoS

2

gra

phite

in-plane cross-plane

graphene

Q”= -κT

heat flux thermal

conductivity

T gradient

E. Pop

Heat (and Current) Flow in Nanoscale Samples

• Macroscale, R is additive: 1 + 1 = 2

• Nanoscale, R is quantized: 1 + 1 = 1

– Occurs when system size is comparable to electron or phonon (heat) wavelengths and mean free path (10-100 nm)

– Both electrical and thermal resistance can be quasi-ballistic

resistance R

size L

R = L/(σA)

nanoscale

38

conductivity (σ or k)

size L

σ,k = const.

σ,k L

macroscalemacroscale

quantized, ballistic

225.8 kΩb

M hR

q

E. Pop

Heat Flow in Nanoscale Graphene

∆T (K)1010.1

290 nm SiO2 Silicon

graphenenanoribbons

M.-H. Bae, Z. Li, Z. Aksamija, P. Martin, F. Xiong, Z.-Y. Ong, I. Knezevic, E. Pop, Nature Comm. 4, 1734 (2013)

10 100 1000 1000010

100

1000

k (W

m-1K

-1)

W (nm)

T = 300 K

T = 190 K

T = 150 K

T = 70 K

edge limited

substrate limited

~200 nm

10 100 1000 100000

100

200

300

400

500

600

700

k (W

m-1K

-1)

L (nm)

ballisticlimit kball

100 K

W2

39

Bulk thermal properties do not apply at <1 µm!

Thermal conductivity k(T) = f(W,L) even at room T– 35% (quasi-)ballistic heat flow in short devices (λ ~ 100 nm)

– Strong edge scattering in narrow devices

“short” (quasi-ballistic) “long” (diffusive + edges)

E. Pop

Looking Ahead: Future OpportunitiesCould we:

– Exploit anisotropy for routing heat? (thermal diode)

– Separate thermal and electrical flow? (thermal transistor)

– Design electronics with built-in thermoelectric cooling?

– Achieve transparent heat spreaders and flexible thermoelectrics?

40

collab: E. Reed, K. Goodson, K. Saraswat, H.-S.P. Wong, Y. Cui

E. Pop

Looking Ahead: Future OpportunitiesCould we:

– Exploit anisotropy for routing heat? (thermal diode)

– Separate thermal and electrical flow? (thermal transistor)

– Design electronics with built-in thermoelectric cooling?

– Achieve transparent heat spreaders and flexible thermoelectrics?

41

( )

1

3

9 Pristine MoS2

0 2 4 6 8

G(M

W/m

2 /K

)

Time (min)

Al / MoS2Li

electrolyte LiPF6

Thermal Switching

A. Sood, F. Xiong, […], E. Pop, Spring MRS (2015)

collab: E. Reed, K. Goodson, K. Saraswat, H.-S.P. Wong, Y. Cui

E. Pop

Summary• Moore’s Law ~10x

• Energy scaling & harvesting ~104x

• Opportunity for convergence of:

– Novel nanomaterials

– Low power devices

– Anisotropy, ballistic, thermoelectric

• Understand fundamental limits

• Future opportunities

42

slowing down

exciting

http://poplab.stanford.eduepop@stanford.edu