electronics developments in rd53 · 2019-08-07 · with (1x4) regions and distributed tot storage...

Valerio Re – Belle II VXD Open Workshop – CERN – July 9, 2019

Valerio Re

Electronics developments in RD53

INFN

Sezione di Pavia


RD53 and the design of a 65 nm CMOS pixel readout chip

• RD53 is a great collaborative effort for the development of new large scale pixel readout chips for ATLAS and CMS

• RD53 tested the capability of the 65 nm CMOS technology to address the requirements of pixel detectors operating at very high luminosity

• Results of RD53 and of other projects (e.g. MPA for the CMS Outer Tracker) confirm that progress in microelectronics can be exploited to advance the performance of detectors in HEP

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RD53: an ATLAS-CMS collaboration

• RD53 was organized to tackle the extreme and diverse challenges associatedwith the design of pixel readout chips for the innermost layers of particletrackers at future high energy physics experiments (LHC – phase II upgrade of ATLAS and CMS) A 50 µm x 50 µm

mixed-signal

pixel readout chip65 nm CMOS technology was chosen to address the requirements of theseapplications. It was fully studied and qualifiedin view of the design of these chips.

• ATLAS: Annecy-LAPP, Bergen, CERN, Bonn, CPPM, LBNL, LPNHE Paris, Milano, NIKHEF, New Mexico, Prague, RAL, UC Santa Cruz.

• CMS: Aragon, Bari, Bergamo-Pavia, CERN, Fermilab, Padova, Perugia, Pisa, RAL, Sevilla, Torino.

– Collaborators: ~100, ~50% chip designers

RD53 – An overview

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• Focused R&D program aiming at the development of pixel chips for ATLAS/CMS phase 2 upgrades

• 65 nm CMOS is the common technology platform

• RD53 Goals

• Detailed understanding of radiation effects in 65nm à guidelines for radiation hardness

• Design of a shared rad-hard IPs library

• Design and characterization of full sized pixel array chip

• The efforts of the RD53 collaboration led to the submission of the RD53A chip

• It is a 20x11.5 mm chip, featuring a matrix of 400x192 pixels (50x50 µm2 each)

• It contains design variations for testing purpose (3 analog front-ends, 2 digital readout architectures)

• Submitted in August 2017, comprehensive testing activity carried out in 2018 and 2019

RD53A


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Study of the 65 nm CMOS technology and of its performance in view of the requirements of LHC pixel detector upgrades and of future applications:

• Operation at extremely high total ionizing dose

• Capability of handling extremely high data rates

• Operation at low charge threshold (low noise and threshold dispersion)

• Integration of mixed-signal circuits in small pixel cells integrated in a large scale chip

• Test of different low-power analog front-end architectures

• Creation of a shared IP library

• Development of tools and methodology to efficiently design large complex mixed-signal chips

RD53 goals


L.Demaria - Results from RD53A and perspectives - Vertex 2018 - Chennai 22-26 Oct 2018, India

Pixel Detector at HL_LHC

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Requirements from HL_LHC experiments

Small pixels: 50x50um2.

Large chips : 2cm x 2cm ( ~0.5 billion transistors)

Pixel Hit rates: up to 3 GHz/cm2 ( 200 P.U.)

Radiation : 1Grad, 1016 n/cm2 (unprecedented)

Trigger: up to 1MHz with 12.8us latency

(~100x buffering and readout)

Low power - Low mass systems

Data readout : up to 4-5 Gbs/s

TRIGGER Latency up to 12.8us (x3) ==> deeper storage

buffer

overlap of 200 collisions in 1 BX

Valerio Re – Belle II VXD Open Workshop – CERN – July 9, 2019 6

RD53 timeline

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Building blocks: Analog FEs, IPsDigital Architecture

Verification environmentComplex Chip Integration

Radiation characterization of the CMOS 65 nm

Small demonstrators (64x64 pixel matrix)FE65P2

CHIPIX65-FE0

RD53A large scale prototype400x192 pixel matrix

RD53B~400x400 pixel matrix

ATLASpixel chip

CMSpixel chip

2013

2015

2017

2019

Two submissions with different matrix size: ATLAS

chip first (Sep. 2019), then CMS chip (Apr. 2020)


RD53A specifications

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2PH-ESE Seminar 15 May 2018 F.Loddo, INFN-Bari

RD53A Specifications

http://cds.cern.ch/record/2113263

Technology 65 nm CMOS

Pixel size 50x50 um2

Pixels 400x192 = 76800 (50% of production chip)

Detector capacitance < 100 fF (200 fF for edge pixels)

Detector leakage < 10n A (20 nA for edge pixels)

Detection threshold <600 e-

In-time threshold <1200 e-

Noise hits < 10-6

Hit rate < 3 GHz/cm2 (75 kHz avg. pixel hit rate)

Trigger rate Max 1 MHz

Digital buffer 12.5 us

Hit loss at max hit rate (in-pixel pile-up) ≤ 1%

Charge resolution ≤ 4 bits ToT (Time over Threshold)

Readout data rate 1-4 links @ 1.28Gbits/s = max 5.12 Gbits/s

Radiation tolerance 500 Mrad at -15oC

SEU affecting whole chip < 0.05 /hr/chip at 1.5GHz/cm2 particle flux

Power consumption at max hit/trigger rate < 1 W/cm2 including ShLDO losses

Pixel analog/digital current 4uA/4uA

Temperature range -40oC ÷ 40oC


RD53A

• Submitted on 31st August 2017• First diced chips received in 06.12.2017• Total transistor count: 310M (x2 for final)• First bump-bonded chip test: April 2018

Chip size: 20.066 x 11.538 mm2

400x192

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L.Demaria - Results from RD53A and perspectives - TREDI 2019 - Trento 25 Feb 2019

RD53A

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~200M transistors

RD53A core design

team Flavio Loddo (Bari)

Tomasz Hemperek (Bonn) Roberto Beccherle (INFN PI)

Elia Conti (CERN)

Francesco Crescioli (Paris) Francesco De Canio (INFN BG-PV)

Leyre Flores (Glasgow)

Luigi Gaioni (INFN BG-PV) Dario Gnani (LBNL)

Hans Krueger (Bonn)

Sara Marconi (CERN / INFN PG) Mohsine Menouni (CPPM)

Sandeep Miryala (FNAL)

Ennio Monteil (INFN TO) Luca Pacher (INFN TO)

Andrea Paternò (INFN TO)

• Aug. 31, 2017: Submission • Dec. 6, 2017: First chip test

• Mar. 15, 2018: 25 wafers ordered • Apr. 13, 2018: First bump-bonded chip test

• Aug. 1, 2018: Other 25 wafers ordered

2 x 1,15 cm2


RD53A floorplan

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Top pad row (debug)120 µm

~ 2

70 µ

m~

1.5

mm

MacroCOLBias

70 m

An

alo

g B

IA

S

Bias

Bias

MacroCOLBias

MacroCOLBias

Padframe

ShLDO_An ShLDO_Dig Driver/Rec

Digital Chip Bottom (DCB)

Dig

ital lin

es

ADC Calibr. Bias DACs SensorsCDR/PLL POR

Analog Chip Bottom (ACB)

Ring osc.

9.6

mm

An

alo

g B

IA

S

An

alo

g B

IA

S

Dig

ital lin

es

Dig

ital lin

es

ShLDO_An ShLDO_Dig ShLDO_An ShLDO_Dig ShLDO_An ShLDO_Dig

400 columns x 192 rows

RD53A floorplan


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Pixel Matrix• The pixel matrix is built up of 8 x 8 Pixel Cores

• 16 analog islands (2x2 quads) embedded in a flat digital synthesized sea• 50% of area to Analog, 50% to digital

• A Pixel Core can be simulated at transistor level with analog simulator• All Cores (for each FE flavour) are identical Hierarchical verifications

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FE

Digital logic

35 15

PIXEL ANALOG ISLAND PIXEL CORE

• All the digital logic for signal digitisation, storage, trigger-matching and readout is shared among

several pixel, called Pixel Regions. Two different Pixel region architectures have been

implemented

Distributed Buffering architecture (DBA)• with (1x4) regions and distributed ToT storage • implemented for two Analog FE (Lin, Diff)

Centralized Buffering architecture (CBA)• with (4x8) regions and centralised ToT storage • implemented for one Analog FE (Sync)

both allow to run at high rate (3 GHz/cm2), high trigger rate (1MHz)

long latencies (12.8 us) with <1% inefficiency

(2x2)

(8x8)


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RD53A test results

A very extensive testing campaign was carried out and is still ongoing to characterize the performance of the chip, also after bump bonding with sensors, after irradiation and in beam tests

In this talk I’ll focus on:

• Analog front-end

• Radiation hardness


Analog design in 65 nm CMOS in RD53

• RD53 evaluated various design choices for the front-end stages, that interface the silicon sensor with the large and mostly digital readout chip

• Severe constraints for noise, power, speed, silicon area, immunity to digital interferences had to be taken into account in the design of the analog blocks (preamplifier, discriminator,…)

• Scaling of transistor size to the nanoscale region also stimulated analog design ideas departing from the usual schemes of pixel front-end circuits, and going beyond a simple translation of old schematics into a more advanced technology. Among them:

Switched-capacitor techniques

(avoid local tuning in the pixel cell and additional hardware)

Fully differential architectures

(increase immunity to interferences)

Current-mode schemes

Techniques for preamplifier feedback reset and sensor leakage current compensation


Analog Front-End (FE) in RD53A

• Three different analog FE designs for performance comparisons with same layout area

• Common calibration injection circuit

Telescopic cascodedesign

Auto-zeroing mechanism:

threshold trimming is not needed

Folded cascode amplifierClassical FE architecture:linear pulse amplification and low power current

comparator

Straight cascode design Differential threshold

circuit optimized for low threshold and low noise

operation


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Analog FE• small Analog FE : ~ 50% of the 50x50 um2 area

• high efficiency : <1% dead-time, low threshold

• low power : reference is 5uA per pixel

• charge measurement (~1ke- /count ) - 4-bit

• low level of fake rate : <1E-6 per chip

• applied to sensor choice and radiation conditions : reference 50fF detector, 10nA; 500 Mrad

Specification on analog FE have been evolving with time

• Initial RD53A requirements

• Important feedback from Analog FE Review

• Now moving to ATLAS requirements and CMS requirements

Take in mind that

• Essential to understand the impact of AFE performances to the CMS/ATLAS pixel detectors : simulation work essential

• The sensor R&D is heavily dependent on RD53A : no sensor choice done yet

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Synchronous Analog Front-end

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• One stage CSA with Krummenacher feedback for linear ToT charge encoding

• Synchronous discriminator, AC coupled to CSA, including offset compensated differential amplifier and latch

• Threshold trimming by means of autozeroing (no local trimming DAC)

• Fast ToT counting with latch turned into a local oscillator (100-900 MHz)


SYNC front-end: preamplifier response

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• Telescopic cascode with current splitting and source follower

• Two switches controlling the feedback capacitance value

Preamplifier output (TOP PAD frame)

Preliminary


Linear Analog Front-end

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• One stage Krummenacher feedback to comply with the expected large increase in the detector leakage current

• High speed, low power asynchronous current comparator

• 4 bit local DAC for threshold tuning


LIN front-end: preamplifier response

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• Gain stage based on a folded cascode configuration (~3 uA absorbed current) with a regulated cascode load


Preliminary


Differential Analog Front-end

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• Continuous reset integrator first stage with DC-coupled pre-comparator stage

• Two-stage open loop, fully differential input comparator

• Leakage current compensation a la FEI4

• Threshold adjusting with global 8bit DAC and two per pixel 4bit DACs


DIFF front-end: preamplifier response

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Preliminary

• Straight regulated cascode architecture with NMOS input transistor in weak inversion

• Simple follower as buffer


Characterization of analog front-ends

All Front-Ends are operational and can be operated at low threshold

These results provide a nice demonstration of the possibility of designing high performance analog front-end circuits in sub-100 nm CMOS technologies

SynchronousLinear Differential


22.5

33.5

44.5

55.5

6A)m

FE current per pixel (

0 20 40 60 80

100

120

140

160

180

200

ENC (electrons)

0x0A48 Sync

0x0A48 Lin

0x0A48 Diff

0x0A58 Sync

0x0A58 Lin

0x0A58 Diff

0x0A57Y Sync

0x0A57Y Lin

0x0A57Y Diff

RD53ACold 50x50 m

odule, 0 dose

Noise measurements on RD53A chips connected to pixel sensors

Chips were connected to pixel sensors; ENC increases as expected according to the sensor capacitance


Noise measurements for the RD53A Linear FE connected to a planar pixel sensor

(25 µm x 100 µm pixels, about 50 fF capacitance)

ENC ≅ 60 e rms → ≅ 90 e rms


Tolerance to high Total Ionizing Dose

• CMOS scaling brings along an increased level of tolerance to high doses of ionizing radiation (thinner gate oxides, higher substrate doping levels,…) without the need of using enclosed layout transistors

• Intrinsic radiation hardness is confirmed in the 65 nm CMOS node: however, beyond 100 Mrad the performance of minimum size transistors (typically used in digital circuits) is degraded; high-speed circuits are critical and rad-hard design rules must be followed

• The RD53A large-scale chip prototypes remain fully functional (even at 1 Grad) with acceptable degradation if they are kept at cold (-20 °C)

• Using large transistors in analog circuits, analog parameters (noise, threshold dispersion, transfer characteristics,..) are moderately affected (10 – 20%)


Thin (rad-hard) gate oxide for core devices,becomes thicker (and rad-softer) for I/O

transistors

Thick Shallow Trench Isolation Oxide (~ 300 nm); radiation-induced charge-buildup may turn on lateral parasitic transistors and

affect electric field in the channel)

Doping profile along STIsidewall is

critical; doping increases with CMOS scaling, decreases in I/O devices

N+ N+

G

S D

P-well

STI STI

P-substrate

Increasing sidewall doping makes a device less sensitive to radiation (more difficult to form parasitic leakage paths)

Radiation effects in 65 nm CMOSSpacer dielectrics may be radiation-sensitive


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L. Ratti, Effects of ionizing and non-ionizing radiation on electronic devices and circuits, INFN LNL, Italy, 1-5 April 2019 46

Dependence on device dimensions: PMOS

Tests performed with the CERN X-ray radiator (~6 Mrad/h)

Change in current driving capability is strongly dependent on W

More likely to be ascribed to mobility degradation (è change in the transconductance) than to threshold voltage change

Room T, VSG=VSD=1.2V

M. Menouni, CPPM

In RD53, 200Mrad and 500Mrad simulation models were developed to ‘predict’ the circuit behavior during design phase. Significant radiation damage is observed above 100Mrad

Tolerance to high Total Ionizing Dose

Analog: transconductance, threshold voltage shift:Analog design guidelines: Wp ≥ 300nm Lp ≥ 120nm Ln ≥ 120nm

Digital: speed degradation

At room temperature, beyond 100 Mrad the performance of small size transistors sizably degrades (threshold shift and current drive reduction)

Better results at cold (tests down to – 30 °C)


3. RADIATION TOLERANCE• When annealing iscarried out withoutpowering the chip,no significant gatedelay degradationincrease is seen.

• In conclusion, controlof environmentalconditions in thereal experiment iscrucial, andannealing historybecomes verysignificant.

500 Mrad cold + annealing with bias vs without bias

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Temperature and bias duringirradiation and annealing

Operating conditions must be kept under accurate control to ensure that the chip remains functional at extremely high TID


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Moderate but detectable noise increase at low frequency, non significant change in channel thermal noise

1/f noise increase related to

• specifically in NMOS, charge trapping in STI and state density increase at the interface between STI and bulk silicon (depending on the operating point)

• state density increase at the gate oxide/channel interface

Noise in irradiated transistors at room T

These results are consistent with a small (if any) ENC increase in irradiated RD53A chips


RD53A Results: Analog FE Characterization After Irradiation (A. Dimitrievska, RD53A talk, VCI 2019)

• Noise for different current settings (for 0, 200, 300, 500 Mrad)

• Threshold distribution after 1 Grad irradiation of a bare chip

22.5

33.5

44.5

55.5

6A)m


0 20 40 60 80

100

120

140

ENC (electrons)

0x0C95 Sync

0x0C95 Lin

0x0C95 Diff

0x0761 Sync

0x0761 Lin

0x0761 Diff

0x0769 Sync

0x0769 Lin

0x0769 Diff

0x0759 Sync

0x0759 Lin

0x0759 Diff

RD53ACold bare chip, irradiated

pre-rad200 Mrad

300 Mrad500 Mrad

22.5

33.5

44.5

55.5

6A)m


0 20 40 60 80

100

120

140

ENC (electrons)

0x0C95 Sync

0x0C95 Lin

0x0C95 Diff

0x0761 Sync

0x0761 Lin

0x0761 Diff

0x0769 Sync

0x0769 Lin

0x0769 Diff

0x0759 Sync

0x0759 Lin

0x0759 Diff


pre-rad200 Mrad

300 Mrad500 Mrad

22.5

33.5

44.5

55.5

6A)m


0 20 40 60 80

100

120

140

ENC (electrons)

0x0C95 Sync

0x0C95 Lin

0x0C95 Diff

0x0761 Sync

0x0761 Lin

0x0761 Diff

0x0769 Sync

0x0769 Lin

0x0769 Diff

0x0759 Sync

0x0759 Lin

0x0759 Diff


pre-rad200 Mrad

300 Mrad500 Mrad

Synchronous Linear

Differential


30

ENC ≅ 60 e rms sQth ≅ 55 e rms


A final remark: how to avoid digital-to-analog interferences

The very goodperformance of the RD53A chip ismade possible by the isolationstrategy used to avoid digitalinterferences in the low-noiseanalog front-end

31


From RD53A to RD53B

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• All RD53A elements with bug fixes and, where needed, technical improvements

• Improved versions of some IPs àTest chips have been submitted and characterized:

• ShuntLDO (with new reference scheme/Bandgaps and overvoltage and under-shunt protection)

• CDR/PLL (improved lock stability)

• New “thin” temperature sensor (to be placed on top of the chip)

• SEU test chip, to evaluate different options of SEU hardening surrounded by the new Sealring

• Linear FE (with TDAC fix) + Bandgaps

• Differential FE: option to add 2 trim bits on the preamp discharge current

• Additional features to be implemented

• Bias of edge and top “long” pixels

• 6-to-4 bit dual slope ToT mapping

• 80 MHz ToT counting

• ATLAS 2-level trigger support

• Power saving ~20%

• Improved design for testability

• TMR for pixel configuration

• Optimal data formatting and compression

• …

Towards RD53B• The success of RD53A is the baseline for the design of the pixel

readout chips of CMS and ATLAS at the HL-LHC

• RD53B is the common design framework for the design of the final production pixel chips for ATLAS and CMS

• ATLAS and CMS chips are planned to be submitted in September 2019 and April 2020 as implementation of the RD53B design

• After a very detailed review process, a choice was made for the analog FE by ATLAS (Differential) and CMS (Linear)

• Improvements and few fixes to RD53A have been found and are being implemented in RD53B

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Conclusions

• RD53 organized a community of IC designers that worked very effectively towards the design and fabrication of ATLAS and CMS pixel readout chips

• 65 nm CMOS demonstrated its capability to provide the required performance for very demanding applications; several other projects are also based on this technology

• The know-how that was acquired in RD53 can provide the basis for new designs of readout electronics for pixel detectors

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Backup slides

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35L.Demaria - Results from RD53A and perspectives - Vertex 2018 - Chennai 22-26 Oct 2018, India

AFE Linear: measurements

16

• Front End can operate with

Thresholds < 1000e-

• Good performance for noise,

threshold, time-walk

• Radiation hardness: good,

studied up to 500 Mrad, new

promising results up to 1 Grad

CS

A o

utp

ut,

(5k

e-

ste

ps

)

ISSUES : • matching with simulation of threshold dispersion • Trimming DAC: LSB behaviour, dynamic range

• NEW design submitted - now under test to see if fixed

Threshold scan: • measures probability of

discriminator to fire vs input

charge • Fitting S-curve provide

measurement of threshold and

noise

electronics developments in rd53 · 2019-08-07 · with (1x4) regions and distributed tot storage...

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