electronics issues, frontend (strips that is, not pixels) us-atlas upgrade r&d meeting ucsc

10-Nov-05 1

Electronics Issues, Frontend 1E.N. SpencerSCIPP-UCSC

ATLASATLAS

Electronics Issues, FrontendElectronics Issues, Frontend

(Strips that is, not Pixels)(Strips that is, not Pixels)

US-ATLAS Upgrade R&D Meeting

UCSC

10-Nov-2005

A.A. GrilloSCIPP – UCSC

10-Nov-05 2


ATLASATLAS

ExperienceExperience

We have shown for past experiments that the bipolar technology has advantages over CMOS in power and performance for front-end amplification of silicon strip readout when the capacitive loads are high and the shaping times short.

• ZEUS-LPS Tek-Z IC

• SSC-SDC LBIC IC

• ATLAS-SCT ABCD, CAFE-M, CAFE-P ICs

CMOS is the preferred technology for back-end data processing but biCMOS technologies have not been readily available, making it difficult to find a one chip solution.

Experience with the commercial 0.25 m CMOS has shown the great advantage of using a high volume commercial rather than a niche technology.

10-Nov-05 3


ATLASATLAS

Technical IssuesTechnical Issues

The ATLAS-ID upgrade will put even larger constraints on power.

Can we meet power and shaping time requirements with deep sub-micron CMOS?

• Achieving sufficient transconductance of the frontend transistor typically requires large bias currents.

The changes that make SiGe Bipolar technology operate at 100 GHz for the wireless industry coincide with the features that enhance performance for our application.

• Small feature size increases radiation tolerance

• Extremely small base resistance (of order 10-100 W) affords low noise designs at very low bias currents.

Can these features help us save power?

Will the SiGe technologies meet rad-hard requirements?

10-Nov-05 4


ATLASATLAS

J. Kaplon et al., 2004 IEEE Rome Oct 2004, use 0.25 m CMOS

For CMOS: Input transistor: 300 A, other transistors 330 A (each 20 – 90 A)

Example CMOS Front-EndExample CMOS Front-End

Can SiGe beatthese numbers?

10-Nov-05 5


ATLASATLAS

biCMOS with Enhanced SiGebiCMOS with Enhanced SiGe

The market for wireless communication has now spawned many biCMOS technologies where the bipolar devices have been enhanced with a germanium doped base region (SiGe devices).

We have identified at least the following vendors:

• IBM (at least 3 generations available)

• STm

• IHP, (Frankfurt on Oder, Germany)

• Motorola

• JAZZ

Advanced versions include CMOS with feature sizes of 0.25 m to 0.13 m.

The bipolar devices have DC current gains () of several 100 and fTs up to 200s of GHz. This implies very small geometries that could afford higher current densities and more rad-hardness.

Growing number of fab facilities

10-Nov-05 6


ATLASATLAS

Radiation vs. Radius in Upgraded TrackerRadiation vs. Radius in Upgraded Tracker

The usefulness of a SiGe bipolar front-end circuit will depend upon its radiation hardness for the various regions (i.e. radii) where silicon strip detectors might be used.

1

10

100

0 20 40 60 80 100

Fluence for 2,500 fb -1

Radius [cm]

InnerPixel

Mid-RadiusShort Strips

Outer-Radius “SCT”

Flu

ence

[10

14 n

eq/c

m2 ]

10-Nov-05 7


ATLASATLAS

Tracker Regions Amenable for SiGeTracker Regions Amenable for SiGe

For the inner tracker layers, pixel detectors will be needed, and their small capacitances allow the use of deep sub-micron CMOS as an efficient readout technology.

Starting at a radius of about 20 cm, at fluence levels of 1015 n/cm2, short strips can be used, with a detector length of about 3 cm and capacitances of the order of 5 pF. At a radius of about 60 cm, the expected fluence is a few times 1014 p/cm2, and longer strips of about 10 cm and capacitance of 15 pF can be used.

It is in these two outer regions with sensors with larger capacitive loads where bipolar SiGe might be used in the front-end readout ASICs with welcome power savings while still maintaining fast shaping times.

10-Nov-05 8


ATLASATLAS

Biasing the Analogue CircuitBiasing the Analogue Circuit

The analog section of a readout IC for silicon strips typically has a special front transistor, selected to minimize noise (often requiring a larger current than the other transistors), and a large number of additional transistors used in the shaping sections and for signal-level discrimination.

The current for the front transistor is selected in order to achieve the desired transconductance (minimize noise). For the other bipolar devices, bias levels for the other transistors are determined to achieve the necessary rad-hardness, matching and shaping times.

Depending upon the performance (especially radiation hardness) of the bipolar process, power savings could be realized in both the front transistor and in the other parts of the analogue circuit.

10-Nov-05 9


ATLASATLAS

Evaluation of SiGe Radiation HardnessEvaluation of SiGe Radiation Hardness

The Team

D.E. Dorfan, A. A. Grillo, J. Metcalfe, M Rogers, H. F.-W. Sadrozinski, A. Seiden, E. N. Spencer, M. Wilder

SCIPP-UCSC

Collaborators: A. Sutton, J.D. Cressler

Georgia Tech, Atlanta, GA 30332-0250, USAM. Ullan, M. Lozano

CNM, Barcelona

and newly joined:S. Rescia et al.

BNL

10-Nov-05 10


ATLASATLAS

First SiGe High-rate Radiation Testing First SiGe High-rate Radiation Testing

Radiation testing has been performed on some SiGe devices by our Georgia Tech collaborators up to a fluence of 1x1014 p/cm2 and they have demonstrated acceptable performance. (See for example: http://isde.vanderbilt.edu/Content/muri/2005MURI/Cressler_MURI.ppt)

In order to extend this data to higher fluences, we obtained some arrays of test structures from our collaborator at Georgia Tech. These were from a -enhanced 5HP process from IBM. (i.e. the was ~250 rather than ~100.)

The parts were tested at UCSC and with the help of RD50 collaborators (Michael Moll & Maurice Glaser) they were irradiated in Fall 2004 at the CERN PS and then re-tested at UCSC.

For expediency, all terminals were grounded during the irradiation This gives slightly amplified rad effects than with normal biasing.

Annealing was performed after initial post-rad testing.

10-Nov-05 11


ATLASATLAS

Irradiated SamplesIrradiated Samples

Pre-rad

1.15 x 10144.15 x 1013 3.50 x 1014

1.34 x 10153.58 x 1015

1.05 x 1016

ATLAS Upgrade

Outer Radius

Mid RadiusInner Radius

10-Nov-05 12


ATLASATLAS

Radiation Damage MechanismRadiation Damage Mechanism

10-14

10-12

10-10

10-8

10-6

10-4

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Forward Gummel Plot for 0.5 mm x 2.5 mm:

IC, IB vs. VB pre-rad and after 1*10 15 p/cm2 + anneal

IC (pre-rad)IB (pre-rad)IC (1e15, anneal)IB (1e15, anneal)

VB [V]

Ionization Damage (in the spacer oxide layers)• The charged nature of the particle creates oxide trapped charges and

interface states in the emitter-base spacer increasing the base current.

Displacement Damage (in the oxide and bulk)• The incident mass of the particle knocks out atoms in the lattice

structure shortening hole lifetime, which is inversely proportional to the base current.

Radiation damage increases base current causing the gain of the device to degrade.

Gain=Ic/Ib (collector current/base current)

I c , I

b [A

]

Forward Gummel Plot for 0.5x2.5 m2

Ic,Ib vs. Vbe Pre-rad and After 1x1015 p/cm2 & Anneal Steps

Vbe [V]

Base current increases after

irradiation

Collector current remains the same

10-Nov-05 13


ATLASATLAS

Annealing EffectsAnnealing Effects

0.1

1

10

100

1000

10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3

Annealing of 0.5 um x 2.5 um: Current Gain beta vs. Ic

pre-rad and after 1*1015 p/cm2 and anneal steps

pre-rad1e15, no anneal1e15, 5 days RT1e15, +6 days RT+1 day 60deg C1e15, +1 day 100deg C1e15, +6 days 100deg C

IC [A]

We studied the effects of annealing. The performance improves appreciably. In the case above, the gain is now over 50 at 10A entering into the region where an efficient chip design may be implemented with this technology. The annealing effects are expected to be sensitive to the biasing conditions. We plan to study this in the future.

Cur

rent

Gai

n,

Ic [A]

Annealing of 0.5x2.5 m2: Current Gain, , vs. Ic

Pre-rad and After 1x1015 p/cm2 & Anneal Steps

Before Irradiation

After IrradiationAfter Irradiation & Full Annealing

10-Nov-05 14


ATLASATLAS

Initial ResultsInitial Results

0.1

1

10

100

1000

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Current Gain beta vs. Ic for 0.5 um x 10um pre-rad and for all Fluences including full annealing

Pre-rad3e131e143e141e153e151e16

IC [A]

After irradiation, the gain decreases as the fluence level increases. Performance is still very good at a fluence level of 1x1015 p/cm2. A typical Ic for transistor operation might be around 10 A where a of around 50 is required for a chip design. At 3x1015, operation is still acceptable for certain applications.

Cur

rent

Gai

n,

Current Gain, , vs. Ic for 0.5x10 m2

Pre-rad and for All Fluences Including Full Annealing

Ic [A]

Before Irradiation

Highest Fluence

Lowest Fluence

Cur

rent

Gai

n,

Increasing Fluence

10-Nov-05 15


ATLASATLAS

Universality of ResultsUniversality of Results

0.0001

0.001

0.01

0.1

1013 1014 1015 1016

Delta(1/beta) post-rad+anneal to pre-rad @ Jc = 10 uA

0.5 um x 1 um0.5 um x 2.5 um0.5 um x 10 um0.5 um x 20 um4 um x 5um

Proton Fluence F [p/cm2]

0

0.2

0.4

0.6

0.8

1

1013 1014 1015 1016

Ratio of Current Gain beta post-rad+anneal to pre-rad @ Jc = 10 uA

0.5 um x 1 um0.5 um x 2.5 um0.5 um x 10 um0.5 um x 20 um4 um x 5um

Proton Fluence F [p/cm2]Proton Fluence [p/cm2]

1/(

fina

l) -

1/

( ini

tial

)

(1/)

Post-rad & Anneal to Pre-rad @ Jc=10A

Proton Fluence [p/cm2]

Ratio of Current Gain, Post-rad & Anneal to Pre-rad @ Jc=10 A

Rat

io

(fin

a l)/ (

init

ial)

Universal behavior independent of transistor geometry when compared at the same current density Jc. For a given current density D(1/b) scales linearly with the log of the fluence. This precise relation allows the gain after irradiation to be predicted for other SiGe HBTs. Note there is little dependence on the initial gain value.

10-Nov-05 16


ATLASATLAS

Feasibility for ATLAS ID UpgradeFeasibility for ATLAS ID UpgradeQualifications for a good transistor:

A gain of 50 is a good figure of merit for a transistor to use in a front-end circuit design.

Low currents translate into increased power savings.

At 3.5x1014 in the outer region (60 cm), where long (10 cm) silicon strip detectors with capacitances around 15pF will be used, the collector current Ic is low enough for substantial power savings over CMOS!

At 1.34x1015 closer to the mid radius (20 cm), where short (3 cm) silicon strip detectors with capacitance around 5pF will be used, the collector current Ic is still good for a front transistor, which requires a larger current while minimizing noise. We expect better results from 3rd generation IBM SiGe HBTs.

Fluence: 3.50E14 p/cm2 (2.17x1014 neq/cm2)=50

Transistor Size m2 cirrad Ic anneal

0.5x1 2.E-060.5x2.5 4.E-06 5.E-080.5x10 3.E-05 8.E-070.5x20 5.E-05 2.E-064x5 9.E-06 5.E-07

Fluence: 1.34E15 p/cm2 (8.32x1014 neq/cm2)=50

Transistor Size m2 cirrad Ic anneal

0.5x1 3.E-05 1.E-070.5x2.5 7.E-05 4.E-060.5x10 4.E-04 9.E-060.5x20 6.E-054x5 1.E-04 1.E-05

10-Nov-05 17


ATLASATLAS

IHP has the SG25H1 200 GHz SiGe process available on Europractice. is ~200. In parallel with radiation testing by Barcelona, UCSC is developing an eight channel amplifier/comparator with similar specifications to the present ABCD.

The x4 minimum transistor has base resistance of 51 m x 3.36 m. 0.25 m CMOS is also included. Extensive use is made of the 2.0 k/ square unsilicided polysilicon resistor structure, since this is expected to be radiation resistant.

The purpose of this FE design is to estimate the low current bias performance of SiGe, and to see whether it can produce significant power savings. The target voltage bias level is 2 V.

IHP Design to Estimate Power of IHP Design to Estimate Power of Upgrade FrontendUpgrade Frontend

10-Nov-05 18


ATLASATLAS

IHP provides a Cadence Kit, with support for both Diva and Allegro.

The bipolar devices are complete as provided, no editing allowed, with some hidden layers to protect IHP intellectual property.

Radiation hard annular NMOS transistor drawing is well supported. This is done by allowing 135 degree bends of Poly lines on Active in the DRC. There are included Virtuoso utilities that are needed for successful DRC.

Cadence Spectre does not DC converge well. Mentor has Eldo utility “Artist Link” that enables Eldo to run with Cadence schematic Composer. Eldo converges vigorously. Overall, the Cadence Kit is complete enough, and with the help of Eldo, is a good toolset.

Design Procedure DetailsDesign Procedure Details

10-Nov-05 19


ATLASATLAS

Frontend Simulation ResultsFrontend Simulation Results

10-Nov-05 20


ATLASATLAS

First Guess at Potential Power SavingsFirst Guess at Potential Power Savings

CHIP TECHNOLOGY FEATURE

0.25 m CMOS ABCDS/FE

J. Kaplon et al.,(IEEE Rome Oct 2004)

IHP SG25H1 SCT-FE Preliminary design

Power: Bias for all but front transistor

330 A 0.8 mW= 30 A(conservative)

.06 mW

Power: Front bias for 25 pF load 300 A 0.75 mW

150 A 0.30 mW

Power: Front bias for 7 pF load 120 A 0.3 mW A 0.10 mW

Total Power (7 pF) 2x1015

0.36 mWTotal Power (25 pF) 3x1014

1.1 mW

1.5 mW

0.16mW

Using similar estimates of bias settings and transistor counts, an estimate for power can be obtained.

10-Nov-05 21


ATLASATLAS

Conclusions on SiGe Evaluation So FarConclusions on SiGe Evaluation So Far

First tests of one SiGe biCMOS process indicate that the bipolar devices may be sufficiently rad-hard for the upgraded ATLAS tracker, certainly in the outer-radius region and even perhaps in the mid-radius region.

A simulation estimate of power consumption for such a SiGe front-end circuit indicates that significant power savings might be achieved.

More work is needed to both confirm the radiation hardness and arrive at more accurate estimates of power savings.

In particular, with so many potential commercial vendors available, it is important to understand if the post-radiation performance is generic to the SiGe technology or if it is specific to some versions.

10-Nov-05 22


ATLASATLAS

Work AheadWork Ahead

Along with our collaborators, we plan two parallel paths of work.

First, we plan more irradiations with several SiGe processes. In particular, we plan to test at least the IBM 5HP, IBM enhanced 5HP, IBM 8HP, IHP SG25H1 and one from STm.

• CNM has obtained a first set of test structures from IHP and is proceeding.

• UCSC has recently received the IBM test structures.

• We have been promised test structures from STm but a schedule is not yet fixed.

• Irradiations will be done with neutrons (Ljubljana), gammas (BNL) and protons (CERN).

To obtain a better handle on the true power savings, we will submit an IHP 8 channel amplifier/comparator early in 2006. This work is in parallel with IHP radiation characterization.

10-Nov-05 23


ATLASATLAS

Other IssuesOther Issues

Joining forces with CMOS:

• As was pointed out, the data processing backend of the readout IC will use CMOS technology.

• The SiGe technologies we are looking at come with 0.25 m to 0.13 m CMOS, so a biCMOS solution is possible.

• It is assumed that these CMOS technologies will be or can be made rad-hard as the 0.25 m process was for current ATLAS. However, this required 2-3 man-years to modify the IBM standard cell library.

• The current CERN-IBM frame contract will expire at end of 2006.

• The tendering process for a new frame contract has started and SiGe is stated as an option, but only an option.

10-Nov-05 24


ATLASATLAS

More IssuesMore Issues

Joining forces with CMOS (cont.):

• If a frame contract is signed for a technology that does not include SiGe, the SiGe biCMOS may require a duplication effort for library conversion.

• A new frame contract itself may be an issue since the total number of wafers expected for LHC Upgrade is expected to be much less than it was for the present LHC construction and IBM has already expressed disappointment in volume.

• With or without a frame contract, it would be very unfortunate (and possibly not financially viable) to be forced to modify two CMOS libraries, one for straight CMOS (e.g. for Pixels) and one for SiGe biCMOS.

10-Nov-05 25


ATLASATLAS

Yet More IssuesYet More Issues

Readout architecture:

• The present readout IC uses binary readout (hit/no-hit).

• There is not universal satisfaction with this within the present SCT community

• There is a call to re-evaluate the architecture choice

• Choice will be driven by lowest power option

There is a proposal to build an “ABCD-next” IC on 0.25 m CMOS

• Prototype vehicle for detector development

• Dual polarity input

• Compatible with present SCT DAQ

• Some power regulation structures

• No identified funding source as yet

electronics issues, frontend (strips that is, not pixels) us-atlas upgrade r&d meeting ucsc

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