elg6163 introduction
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Introduction
SYSC5603 (ELG6163) Digital Signal Processing
Microprocessors, Software and Applications
Miodrag Bolic
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Outline
Introduction to the course
Computer architectur es for signal processing
Design cycle
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Course Outline
Hardware
DSP Systems, A/D and D/A
conver ters
Architectural Analysis of a
DSP Device, TMS320C6x,
Tiger Sharc, Blackfin
FPG A for signal processing
(Altera, Xilinx),
Application domain specific
instruction set processors
SoC, DSP Multiprocessors
Signal processing arithmetic
units
Algorithm design and
transformations
Scheduling, Resource
Allocation, Synthesis
Finite-word length eff ects
Algorithmic transformations
FIR filter design
FFT design
IIR filter design
Adaptive filter design
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Course Conduct
Course notes will be posted on the course web page
Assignments with solutions will be provided and will not be graded
Ther e is no text-book
The exam will be pr epar ed based on lectur e slides,
r ef er ences and assignments
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Paper Analysis and Presentation
Topics ar e r elated to the studied material
Each student will pr esent for 15 minutes
Discussion will follow af ter the pr esentation
Each student has to choose one topic befor e January 16th at 7pm.
Each student have to send a document (from 8-10 pages) font 12 single spaced thr ee days befor e the pr esentation.
The document has to be r evised af ter my comments
15 pr esentation slides max (10 minutes, 15min max)
The mark is 50% document, 50% pr esentation
Some pr eliminary time schedule is given on the course web page.This time schedule will be updated on January 16th
Your r epor ts will be posted on the course Web page. Please see the
paper on plagiarism: How to Handle Plagiarism: New Guidelines
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Presentation topics- Computer architectur es
Configurable processors for DSP applications
± The analysis of processors with configurable instructions sets.
Analysis of the tools. Include Tensilica, Altera and Cowar e
solutions (Lisatek). An example of existing designs using
configurable processors.
Multiprocessors for DSP ± Analysis of papers including [Kumar 05] and [Wiangtong05].
Analysis of curr ent hardwar e solutions. Analysis of tools
including CMPWARE. An example of existing designs using
multi-processors.
IP cor e design.Curr ent standards r elated to IP cor e design. Standard buses
used for IP cor es. Advantages and disadvantages of hard and
sof t IP cor es. DSP processor cor es. DSP hardwar e cor es.
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Presentation topics- Tools
Design space exploration tools
± The analysis of the tools for design space exploration. Simulink basedtools AccelChip vs. C-based tools (Cowar e). Performance anddiff er ences.
Dir ect mapping from algorithms to hardwar e
± Analysis of diff er ent tools (Simulink, Synopsys System Studio,CoWar e's SPW 5-XP) and design processes used for automated
implementation of signal processing algorithms to FPG A. Analysis of quality and speed of these automated implementations.
Comparison between HandleC, SpecC and SystemC
± What is the main diff er ence of these languages. Which language shouldbe taken for which application? Which of these languages have totalsuppor t from algorithm design to the implementation (example
Synopsys SystemC solution). Tools for the analysis of the optimal-word length
± Analyze the tools for floating to fixed point pr ecision. Compar e solutionsfrom Mathworks, Synopsys and AccelChip.
TI standard for writing algorithms - eXpr essDSP Algorithm
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Presentation topics - Applications
Sof twar e-defined radio
± Analysis of signal processing algorithms used for sof twar e defined
radios. Computer architectur es for sof twar e defined radios. List of
commercial platforms and development tools.
Signal processing for wir eless sensor networks
± Analysis of signal processing algorithms used for wir eless sensor
networks: positioning, tracking, data fusion, sensor processing. Analysisof DSP architectur es used in sensor networks. Specifics of algorithm
designs for wir eless sensor networks.
Tracking applications
± Detailed analysis of diff er ent tracking and navigation application
including: aircraf t positioning, target tracking for radar and sonar
applications, car collision detection, and positioning and tracking in homeland security applications. Define the r equir ements for each
application such as sampling rate, accuracy, latency, range. Discuss
about the algorithms and about the hardwar e platforms used for each
applications
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Project
Project proposals ar e expected by February 6th.
Deadline for project demonstration: March 31 Deadline for project r epor t: March 27
Grade: 20% Project Proposal, 20% Project Repor t, 20% Project Pr esentation, 40% Demonstration
You propose the algorithm and the application
Two defined projects ± Float-to-fixed point analysis and implementation of par ticle filters (Simulink or Synopsys System Studio) using FPG A
± Comparison of diff er ent implementations of atan function using PDSP and FPG Aplatforms (VHDL)
Project platforms and tools:1. Implementing signal processing algorithms using configurable processors with
DSP blocks (Tensilica and NIOS II1)
2. The analysis of VLIW architectur es and simulators for signal processing(Hardwar e design)
3. System level design using Simulink & Altera's DSP Builder 1
4. System level design using SystemC under Synopsys System Studio
5. Multiprocessing using CMPWARE (Java, NIOS II)
1 ± might be the license problem
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Project topics
Implementations of diff er ent algorithms on the same platform for the
purpose of comparison of the algorithmsExamples: ± Implementation of multimedia signal processing algorithm in programmable dsp
chips (TI TMS 32060) using the algorithm transformation techniques andcompar e to existing implementations. It is r equried to discuss the VLIWinstructur e architectur e and demonstrate how algorithm transformation/mapplingtechniques ar e being used to generate the code.
± Comparison of diff er ent implementations of atan function using PDSP and FPG A
platforms (VHDL).
Implementation of a DSP algorithm on new platforms.
Examples: ± Comparison of performance of Kalman filter implementations on configurable
processors
± Development of parallel Kalman filtering algorithm suitable for multiprocessor
implementation.
Implementation of complex algorithms on FPG As ± It r equir es full implementation cycle from the implementation of these algorithms
on Matlab/Simulink to their implementation. Mapping between the algorithms andthe hardwar e have to be performed. Floating to fixed point analysis have to be performed
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Project report
Proposal: The purposes of writing a project proposals ar e: (i) to determine the topic, (ii) to show that pr eliminary study
of the subject materials have been done, (iii) to assess the likelihood of success of the project, (iv) to give the plan to carry out the project. You should submit a thr ee to five pages proposal to the instructor for approval of the project. A face to face discussion lasting 5-10 minutes between the instructor and the student is required.This discussion should take place during one of the office hours of the instructor. At the end of this discussion, the instructor will either approve the proposal and assign a grade, or r e ject the proposal and let the team know the r eason. In the latter case, the team must come up with an r evised proposal or an alter nate new proposal befor e adeadline specified in the course outline. Pr eliminary discussion and the instructor can also be held in advance during their office hours. However, the opinion expr essed by the teaching staff during these pr eliminarydiscussions ar e only suggestions. The team members ar e r esponsible to use their best judgement to pr epar e the proposal for approval.
The format of the proposal is as follows:
title of the project project highlight -- explain what you want to do in this project, Motivation -- explain the significance of the proposed project and the r elevance of the project to this course Prior ar t -- listing at least thr ee pr evious works (papers, books, etc.) that r epor ted work most closely r elated to the
curr ent project. Briefly r eview their approaches, advantages and shor tcomings. Approach -- outline proposed approaches. Including pr eliminary analytical r esult, or implementation prototype as
appropriate, a schedule of tasks to be performed, etc.
expected r esults -- what can be promised in the final project r epor t that is not par t of the proposal.
Task planning --specify when you will do what.
Report: A type-written, hardcopy project r epor t, as well as an electronic version (including source code, design filesdeveloped) ar e to be submitted at the end of the semester. The length of the r epor t is not r estricted. However, the r epor t must be include the following sections:
Introduction: Motivation and backgrounds. Main body of r epor t. Depending on types of project, this par t may include method used, approaches taken,
problem description, etc.
Conclusion and discussion: Highlight your achievement in this project and things may be done in the futur e.
Mor e details about the project will follow
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Course Objectives « To
Understand tradeoffs in implementing DSP algorithms
Know basic DSP architectur es
Know some r educed complexity strategies for algorithms
mainly on FPG A.
Know about commercial DSP solution
Know and understand system-level design tools
Understand r esearch topics r elated to algorithmic
modifications and algorithm-architectur e matching
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Why this course?
Ther e is the demand to derive mor e information per signal.
³Mor e´ means
Faster: Derive mor e information per unit time;
± Faster hardwar e
± Newer algorithms with f ewer operations
Cheaper: Derive information at a r educed cost in processor size, weight, power consumption, or dollars;
Better: Derive higher quality information, (higher
pr ecision, finer r esolution, higher signal-to-noise ratio)
[Richards04 ]
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Hardware and software elements
Progr ess in signal processing capability is the product of
progr ess in IC devices, architectur es, algorithms andmathematics.
[Richards04 ]
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Moore¶s Law
http://www.icknowledge.com/trends/uproc.html
Predicts doubling of circuit density every 1.5 to 2 years.
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What is Signal Processing?
Ways to manipulate
signal in its original
medium or an abstract
r epr esentation.
Signal can be abstracted
as functions of time or spatial coordinates.
Types of processing: ± Transformation
± Filtering
± Detection
± Estimation
± Recognition and
classification ± Coding (compr ession)
± Synthesis and r eproduction
± Recording, archiving
± Analyzing, modeling
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Digital Signal Processing
Signals generated via
physical phenomenon ar e
analog in that
± Their amplitudes ar e
defined over the range of
r eal/complex numbers
± Their domains ar e
continuous in time or
space.
Digital signal processingconcer ns processing
signals using digital
computers.
± A co ntinuous time/space
signal must be sampled toyield countable signal
samples.
± The r eal-(complex) valued
samples must be quantized
to fit into inter nal wordlength.
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Signal Processing Systems
The task of digital signal processing (DSP) is to process sampled
signals (from A/D analog to digital conver ter ), and provide its output
to the D/A (digital to analog conver ter ) to be transformed back to
physical signals.
Digital Signal
ProcessingA/D
D/A
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Stratix DSP Development Board
40-Pin Connectors
for Analog DevicesTexas Instruments Connectors
on Underside of Board
Mictor-Type Connectors
for HP Logic Analyzers
MAX 7000 Device
Analog SMA
Connectors
D/A Converters
A/D Converters
Prototyping Area
Nios Expansion
Prototype Connector
[AlteraDSP]
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Example DSP Applications«.
DSPDSP
MILITARYMILITARY
Secure Communications
Sonar Processing
Image Processing
Radar Processing
Navigation, Guidance
VOICE/SPEECHVOICE/SPEECH
Speech Recognition
Speech Processing/Vocoding
Speech Enhancement
Text-to-Speech
Voice Mail
INSTRUMENTATIONINSTRUMENTATION
Spectrum Analyzers
Seismic Processors
Digital Oscilloscopes
Mass Spectrometers
MEDICALMEDICAL
Patient Monitoring
Ultrasound Equipment
Diagnostic Tools
Fetal Monitors
Life Support Systems
Image Enhancement
INDUSTRIAL/CONTROLINDUSTRIAL/CONTROL
Robotics
Numeric Control
Power Line Monitors
Motor/Servo Control
CONSUMERCONSUMER
Radar Detectors
Power Tools
Digital Audio / TV
Music Synthesizers
Toys / Games
Answering Machines
Digital Speakers
PROPRO--AUDIOAUDIO
AV Editing
Digital Mixers
Home Theater
Pro Audio
COMMUNICATIONSCOMMUNICATIONS
Echo Cancellation
Digital PBXs
Line Repeaters
Modems
Global Positioning
Sound/Modem/Fax Cards
Cellular Phones
Speaker Phones
Video Conferencing
ATMs
www.analog.com/dsp
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Implementation of DSP Systems
Platforms: ± Native signal processing
(NSP) with general purpose
processors (GPP)
Multimedia extension
(MMX) instructions
± Programmable digital signal
processors (PDSP)
± Application-Specific
Integrated Circuits (ASIC)
± Field-programmable gate
array (FPG A)
Requir ements: ± Real time
Processing must be done befor e a pr e-specified deadline.
± Str eamed numericaldata
Sequential processing
Fast arithmeticprocessing
± High throughput Fast data input/output
Fast manipulation of data
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How Fast is Enough for DSP?
Real time r equir ements:
± Example: data captur e
speed must match
sampling rate. Other wise,
data will be lost.
± Processing must be done
by a specific deadline.
Diff er ent throughput rates
for processing diff er ent
signals
± Throughput wsampling
rate.
± CD music: 44.1 kHz ± Speech: 8-22 kHz
± Video (depends on frame
rate, frame size, etc.) range
from 100s kHz to MHz.
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ASIC: Application Specific ICs
Custom or semi-custom
IC chip or chip sets
developed for specific
functions.
Suitable for high volume,
low cost productions. Example: MPEG codec,
3D graphic chip, etc.
ASIC becomes popular
due to availability of IC foundry ser vices. F ab-less design houses tur n innovative design intoprofitable chip sets using
CAD tools. Design automation is a
key enabling technologyto facilitate fast design cycle and shor ter time to
market delay.
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Programmable Digital Signal Processors (PDSPs)
Micro-processors designed
for signal processingapplications.
Special hardwar e suppor t for:
± Multiply-and- Accumulate (MAC) ops
± Saturation arithmetic ops ± Zero-over head loop ops
± Dedicated data I/O por ts
± Complex addr esscalculation and memoryaccess
± Real time clock and other embedded processingsuppor ts.
PDSPs wer e developed to fill a
market segment between GPP and ASIC:
± GPP flexible, but slow
± ASIC fast, but inflexible
As VLSI technology improves,role of PDSP changed over
time. ± Cost: design, sales,
maintenance/upgrade
± Performance
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PDSP Market ± By Company
2 1 M r et are
40%
12%16%
%
24%
exas str ents
M t r aAgere
Analog Dev es
ther
2002 Mar et hare
43%
14%
14%
9%
20%
Ref: Forward Concepts
http://www.fwdconcepts.com/Pages/press42.htm
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DSP Market ± By Application
S - 2 3
8
8
4 3
W R L SS
CO SU ERMULT UR OSE
W REL NE
COM UTER
UTOMOT VE
Ref: Forward Concepts
http://www.fwdconcepts.com/Pages/press42.htm
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Computing using FPGA
FPG A (Field programmable
gate array) is a derivative of PLD (programmable logic
devices).
They ar e hardware
configurable to behave
diff er ently for diff er ent configurations.
Slower than ASIC, but faster
than PDSP.
Once configur ed, it behaves
like an ASIC module.
Use of FPG A
± Rapid prototyping: run
fractional ASIC speed
without fab delay.
± Hardwar e accelerator:
using the same hardwar e
to r ealize diff er ent function modules to save hardwar e
± Low quantity system
deployment
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Stratix EP1S10
Altera Corp., Stratix Module 2: Logic Structur e & MultiTrack Interconnect, 2004.
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IP Cores
Processor cor es
Star t-Cor e ± 16-bit fixed-point VLIW DSP cor e from Lucent/Motorola (a company is
established by Lucent for DSP section called ³Ager e´)
± First VLIW machine to target low-power applications
± Pipeline r elatively simple
± Targeting 198 mW @ 300 MHz, 1.5 V
Hardwar e cor es
Altera DSP cor esDevice Type
± FIR Compiler
± IIR Compiler
± FFT/IFFT Compiler
± NCO Compiler ± Reed-Solomon Compiler
± Constellation Mapper/Demapper
± Viterbi Compiler
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SoC (System-on-Chip)
With the continuing scaling of
moder n IC devices, it is now possible to incorporate
± Micro-processor cor es + ASIC function blocks
± Analog + digital components
± Computation + communication
functions ± I/O, memory + processor
into the same chip to form acompr ehensive ³system´.Thus, the notion of System-on-chip (SoC)
Soc uses intellectual
proper ties (IPs) that ar e pr e-designed modules.
Designing SoC thus becomes
a task of system integration.
Challenge issues in SoC
design: ± Interface among IPs from
diff er ent venders
± Verification of function
± Physical design challenges
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Design Issues
Given a DSP application,
which implementation
option should be chosen?
For a par ticular
implementation option,
how to achieve optimaldesign? Optimal in terms
of what criteria?
Sof twar e design:
± NSP, PDSP ± Algorithms ar e implemented
as programs.
Hardwar e design:
± ASIC, FPG A
± Algorithms ar e dir ectly
implemented in hardwar e modules.
S/H Co-design: System leveldesign methodology.
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Design Process Model
Design is the process
that links algorit hm to
implementation
Algorithm
± Operations
± Dependency between operations determines a
par tial ordering of
execution
± Can be specified as a
dependence graph
Implementation
± Assignment: Each
operation can be r ealized
with
One or mor e instructions
(sof twar e)
One or mor e function modules (hardwar e)
± Scheduling: Dependence
r elations and r esource
constraints leads to a
sc hedule.
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A Design Example «
Consider the algorithm:
Program:y(0) = 0
For k = 1 to n Do
y(k) = y(k-1)+ a(k)*x(k)
End
y = y(n)
Operations:
± Multiplication
± Addition
Dependency
± y(k) depends on y(k-1)
± Dependence Graph:
§!
!n
k
k xk a y1
)()(
*
+
a(1) x(1)
*
+
a(2) x(2)
*
+
a(n) x(n)
y(0) y(n)
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Design Example cont¶d «
Sof twar e Implementation: ± Map each * op. to a MUL
instruction, and each + op. to a ADD instruction.
± Allocate memory space for {a(k)}, {x(k)}, and {y(k)}
± Schedule the operation bysequentially execute y(1)=a(1)*x(1), y(2)=y(1) +a(2)*x(2), etc.
± Note that each instruction isstill to be implemented in hardwar e.
Hardwar e Implementation:
± Map each * op. to a multiplier,
and each + op. to an adder.
± Interconnect them according to
the dependence graph:
*
+
a(1) x(1)
*
+
a(2) x(2)
*
+
a(n) x(n)
y(0) y(n)
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Observations
Eventually, an
implementation isr ealized with hardwar e.
However, by using the
same hardwar e to r ealize
diff er ent operations at diff er ent time
(scheduling), we have a
sof twar e program!
Bottom line ± Hardwar e/
sof twar e co-design.Ther e is a continuation between hardwar e andsof twar e implementation.
A design must explor e
both simultaneously toachieve best performance/cost trade-off.
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A Theme
Matching hardwar e to
algorithm
± Hardwar e architectur e
must match the
characteristics of the
algorithm.
± Example: ASIC architectur e is designed to
implement a specific
algorithm, and hence can
achieve superior
performance.
Formulate algorithm to match
hardwar e ± Algorithm must be formulated
so that they can best exploit
the potential of architectur e.
± Example: GPP, PDSP
architectur es ar e fixed. One
must formulate the algorithm
properly to achieve best
performance. Eg. To minimize
number of operations.
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Algorithm Reformulation
Algorithmic level equivalence
± Diff er ent filter structur es implementing the same specification
Exploiting parallelism
± Regular iterative algorithms and loop r eformulation
Well studied in parallel compiler technology
± Signal flow/Data flow r epr esentation Suitable for specification of pipelining
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Mapping Algorithm to Architecture
Scheduling and Assignment Problem
± Resources: hardwar e modules, and time slots
± Demands: operations (algorithm), and throughput
Constrained optimization problem
± Minimize r esources (objective function) to meet demands
(constraints) For r egular iterative algorithms and r egular processor
arrays -> algebraic mapping.
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Implementation process for PDSP
[Wiangtong05]
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Direct Mapping Techniques
[Wiangtong05]
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FIR Filters
[DSPPrimer -Slides]
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Transposed FIR Filter
Algorithm transform techniques: ± Pipelining and parallelism,
± retiming,
± Unfolding-loop unrolling
[DSPPrimer -Slides]
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A B C D
A B C Dallocation
A B C Dassignment
A B C Dpipelining
clocked flip-flop
ff
clock
|
Example: One-to-one mapping and pipelining
Analyse timing
if OK then stop
else pipelining
[Meerbergen-Slides]
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Coware SPW Design Flow
www.cowar e.com
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System-level design flow: Simulink-Altera
[AlteraDSP]
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http://slidepdf.com/reader/full/elg6163-introduction 47/49
47
Arithmetic
CORDIC
± Compute elementary functions
Distributed arithmetic
± ROM based implementation
8/8/2019 ELG6163 Introduction
http://slidepdf.com/reader/full/elg6163-introduction 48/49
48
Floating to fixed point analysis
Overflow of the number range
Large errors in the output signal occur when the available number range is exceeded² overflow.
Round-off errors
Rounding or truncation of products must be done in r ecursive loops
soth
at the
w
ord len
gth
does
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eas
efor
eac
hite
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n.
Coefficient errors
Coefficients can only be r epr esented with finite pr ecision.
Design for fixed-point arithmetic:
Peak value estimation
Word-length optimization
Saturation arithmetic
8/8/2019 ELG6163 Introduction
http://slidepdf.com/reader/full/elg6163-introduction 49/49
49
References
In order to pr epar e these slides, the following material is
used:
Slides from [Hu04-Slides] ³Design and Implementation of
Signal Processing Systems: An Introduction´ ar e copied
with permission. Slides from [DSPPrimer -Slides] and [Meerbergen-Slides]
[Richards04], [AlteraDSP], [Seshan98]
Details about these r ef er ences can be found at:http://www.site.uottawa.ca/~mbolic/elg6163/Ref er ences.htm