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DEPARTMENT OF INFORMATION TECHNOLOGY

EMBEDDED SYSTEMS LAB (89S52 Development Board)

VI Semester

c

DECCAN COLLEGE OF ENGINEERING & TECHNOLOGY

Dar-us-Salam, Hyderabad -500 001.

DECCAN COLLEGE OF ENGINEERING & TECHNOLOGY

Dar-us-Salam, Hyderabad -500 001.

Lab Manual for the Academic Year 2016

SUBJECT : EMBEDDED SYSTEMS LAB

SUBJECT CODE : PC631 IT

SEMESTER : IV – II

STREAM : INFORMATION TECHNOLOGY

NUMBER OF EXPERIMENTS DONE:

INDEX

S.No Name of the Content PAGE NO.

1 Lab Objective

2 Introduction About Lab

3 LAB CODE

4 List of Lab Exercises

5 Description about ES Concepts

6 Programs List

7 Viva question

8 References

Lab Objective:

An embedded system is some combination of computer hardware and software, either

fixed in capability or programmable, that is specifically designed for a particular kind of

application device. Industrial machines, automobiles, medical equipment, cameras, household

appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone

and PDA) are among the myriad possible hosts of an embedded system. Embedded systems

that are programmable are provided with a programming interface, and embedded systems

programming is a specialized occupation.

An embedded system is a special-purpose computer system designed to perform one

or a few dedicated functions [1], often with real-time computing constraints. It is usually

embedded as part of a complete device including hardware and mechanical parts. In contrast,

a general-purpose computer, such as a personal computer, can do many different tasks

depending on programming. Embedded systems have become very important today as they

control many of the common devices we use.

Since the embedded system is dedicated to specific tasks, design engineers can optimize it,

reducing the size and cost of the product, or increasing the reliability and performance. Some

embedded systems are mass-produced, benefiting from economies of scale.

INTRODUCTION ABOUT LABThere are 30 systems (Wipro) installed in this Lab. Their configurations are as

follows :Processor :

RAM : Hard Disk : Mouse : Network Interface card : Software

1. All systems are configured in DUAL BOOT mode i.e, Students can boot from Windows XP or Linux as per their lab requirement. This is very useful for students because they are familiar with different Operating Systems so that they can execute their programs in different programming environments.

2. Each student has a separate login for database access3. Keil is a German based Software development company. It provides several development

tools likeIDE (Integrated Development environment)Project ManagerSimulatorDebuggerC Cross Compiler , Cross Assembler, Locator/Linker

4. Keil Software provides you with software development tools for the 8051 family of microcontrollers. With these tools, you can generate embedded applications for the multitude of 8051 derivatives. Keil provides following tools for 8051 development

C51 Optimizing C Cross Compiler,A51 Macro Assembler,8051 Utilities (linker, object file converter, library manager),Source-Level Debugger/Simulator,µVision for Windows Integrated Development Environment.

5. Systems are assigned numbers and same system is allotted for students when they do the lab.

LAB CODE

1. Students should report to the concerned labs as per time table schedule.

2. Students who turn up late to the labs will in no case be permitted to do the program scheduled

for the day.

3. After completion of the program, certification of the concerned staff in-charge in the

observation book is necessary.

4. Students should bring a notebook of about 100 pages and should enter the

reading/observations into the notebook while performing the experiment.

5. The record of observations along with the detailed experimental procedure of the experiment

performed in the immediate last session should be submitted and certified by the staff ember

in-charge.

6. Not more than three students in a group are permitted to perform the experiment on a setup.

7. The group-wise division made in the beginning should be adhered to and no mix up student

among different groups will be permitted later.

8. The components required pertaining to the experiment should be collected from stores in-

charge after duly filling in the requisition form.

9. When the experiment is completed, students should disconnect the setup made by them, and

should return all the components/instruments taken for the purpose.

10. Any damage of the equipment or burn-out of components will be viewed seriously either by

putting penalty or by dismissing the total group of students from the lab for the semester/year.

11. Students should be present in the labs for the total scheduled duration.

12. Students are required to prepare thoroughly to perform the experiment before coming to

Laboratory.

13. Procedure sheets/data sheets provided to the student’s groups should be maintained neatly

and to be returned after the experiment.

List of Lab Exercises

EMBEDDED SYSTEMS – Lab Programs List

Submission – 1

Week – 1 CYCLE I Relay, Buzzer, keypad

Week – 2 CYCLE I Mode 4 Counter, Mode 8 Counter, Mode 10 Counter

Week – 3 CYCLE I 8 Bit Binary Up Counter, 8 Bit Binary Down Counter ,External Interrupt

Week – 4 CYCLE I Binary Up counter 7 Segment, Binary down Counter 7 segment

Week -5 CYCLE I Single Line Display, Double Line Display using LCD, LCD using 2129, EEPROM using 2129

Submission – 2

Week – 1 CYCLE I Develop control application as Traffic controller, stepper motor, elevator,

Week – 2 CYCLE II 4 bit ALU, PRGEN using LFSR

Week – 3 CYCLE III Timing, Semaphore, signal,

Week – 4 CYCLE III Round Robin Task Scheduling, Priority Inversion

Week -5 CYCLE III Message Queues ,Primitive Priority Based Task Scheduling

MICROCONTROLLER

When starting a new project, simply select the microcontroller use from the Device Database and the µVision 2 IDE sets all compiler, assembler, linker, and memory options This every think is done on cycle 1 for all the programs

MICROPROCESSOR

When starting a new project, simply select the family of microprocessor(CPLD Runner cooler) use from the Device Database and the Xilinx sets all check syntax, implementation design , test bench form. This every think is done on cycle 2 for all the programs

RTOS

When starting a new project, simply select the family of ARM (LPC 2148) use from the device database and the µVision 3 IDE sets all compilers, assembler, linker, and memory options in the RTX kernel. This every think is done on cycle 3 for all the programs

Lab Programs List

S.NO PROGRAM NAME PAGE NO CYCLE-1

A. Use of 8-Bit &32-Bit Micro Controller(8051) using C Compiler Interface I/O And Other UnitRelayKeypadBuzzerMod 4 CounterMod 8 CounterMod 10 Counter8-Bit Binary Up-Counter8-Bit Binary Down CounterExternal Interrupt7-Segment(3 SEG)Single Line DisplayAscending and Descending order ledsAlternate glowing leds

Develop Control Application As Traffic ControllerDevelop control Application As Stepper MotorDevelop Control Application As Elevator

CYCLE-IIB. Development Of Embedded Application Using FPGA &

CPLD With Xilinx Programmable Logic Design4 Bit ALUPseudo Random Number Generator (left shift or right shift) CYCLE-III

C. Understanding Real Time Concept Using Any RTOS Through Demonstration of:Timing.SignalSemaphoreRound Robin Task SchedulingPriority Inversion Message Queue

Primitive Priority Based Task Scheduling

CYCLE-1

Description about ES Concepts:

Embedded systems are designed to do some specific task, rather than be a general-

purpose computer for multiple tasks. Some also have real-time performance constraints that

must be met, for reason such as safety and usability; others may have low or no performance

requirements, allowing the system hardware to be simplified to reduce costs.

Embedded systems are not always separate devices. Most often they are physically built-

in to the devices they control.

The software written for embedded systems is often called firmware, and is stored in

read-only memory or Flash memory chips rather than a disk drive. It often runs with limited

computer hardware resources: small or no keyboard, screen, and little memory.

Embedded systems range from no user interface at all — dedicated only to one task to full

user interfaces similar to desktop operating systems in devices such as PDAs.

Simple embedded devices use buttons, LEDs, and small character- or digit-only displays,

often with a simple menu system.

AT89C51 MICROCONTROLLER FEATURES

80C51 based architecture

4-Kbytes of on-chip Reprogrammable Flash Memory

128 x 8 RAM

Two 16-bit Timer/Counters

Full duplex serial channel

Boolean processor

Four 8-bit I/O ports, 32 I/O lines

Memory addressing capability

– 64K ROM and 64K RAM

Power save modes:

– Idle and power-down

Six interrupt sources

Most instructions execute in 0.3 us

CMOS and TTL compatible

Maximum speed: 40 MHz @ Vcc = 5V

Industrial temperature available

Packages available:

– 40-pin DIP

– 44-pin PLCC

– 44-pin PQFP

GENERAL DESCRIPTION:

THE MICROCONTROLLER:A microcontroller is a general purpose device, but that is meant to read data, perform

limited calculations on that data and control its environment based on those calculations. The

prime use of a microcontroller is to control the operation of a machine using a fixed program

that is stored in ROM and that does not change over the lifetime of the system.

The microcontroller design uses a much more limited set of single and double byte

instructions that are used to move data and code from internal memory to the ALU. The

microcontroller is concerned with getting data from and to its own pins; the architecture and

instruction set are optimized to handle data in bit and byte size.

The AT89C51 is a low-power, high-performance CMOS 8-bit microcontroller with

4k bytes of Flash Programmable and erasable read only memory (EROM). The device is

manufactured using Atmel’s high-density nonvolatile memory technology and is functionally

compatible with the industry-standard 80C51 microcontroller instruction set and pin out. By

combining versatile 8-bit CPU with Flash on a monolithic chip, the Atmel’s AT89c51 is a

powerful microcomputer, which provides a high flexible and cost- effective solution to many

embedded control applications.

Pin configuration of AT89c51 Microcontroller

AT89C51 Block Diagram

PIN DESCRIPTION:VCC Supply voltage

GND

Ground

Port 0Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight

TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance

inputs.

Port 0 can also be configured to be the multiplexed low order address/data bus during

access to external program and data memory. In this mode, P 0 has internal pull-ups. Port 0

also receives the code bytes during Flash programming and outputs the code bytes during

program verification. External pull-ups are required during program verification.

Port 1Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The port 1output

buffers can sink/source four TTL inputs. When 1s are written to port 1 pins, they are pulled

high by the internal pull-ups can be used as inputs. As inputs, Port 1 pins that are externally

being pulled low will source current (1) because of the internal pull-ups.

Port 2Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The port 2 output



being pulled low will source current because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program

memory and during access to DPTR. In this application Port 2 uses strong internal pull-ups

when emitting 1s. During accesses to external data memory that use 8-bit data address

(MOVX@R1), Port 2 emits the contents of the P2 Special Function Register. Port 2 also

receives the high-order address bits and some control signals during Flash programming and

verification.

Port 3Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The port 3 output



being pulled low will source current because of the internal pull-ups.

Port 3 also receives some control signals for Flash Programming and verification.

Port pin Alternate Functions

P3.0 RXD(serial input port)

P3.1 TXD(serial input port)

P3.2 INT0(external interrupt 0)

P3.3 INT1(external interrupt 1)

P3.4 T0(timer 0 external input)

P3.5 T1(timer 1 external input)

P3.6 WR(external data memory write strobe)

P3.7 RD(external data memory read strobe)

RSTRest input A on this pin for two machine cycles while the oscillator is running resets the

device.

ALE/PROG:

Address Latch Enable is an output pulse for latching the low byte of the address

during access to external memory. This pin is also the program pulse input (PROG) during

Flash programming.

In normal operation ALE is emitted at a constant rate of 1/16 the oscillator frequency

and may be used for external timing or clocking purpose. Note, however, that one ALE pulse

is skipped during each access to external Data memory.

_____

PSEN

Program Store Enable is the read strobe to external program memory when the

AT89c51 is executing code from external program memory PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to external

data memory.

__EA /VPP

External Access Enable (EA) must be strapped to GND in order to enable the device

to fetch code from external program memory locations starting at 0000h up to FFFFH. Note,

however, that if lock bit 1 is programmed EA will be internally latched on reset. EA should

be strapped to Vcc for internal program executions. This pin also receives the 12-volt

programming enable voltage (Vpp) during Flash programming when 12-volt programming is

selected.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL 2

Output from the inverting oscillator amplifier.

OPERATING DESCRIPTION

The detail description of the AT89C51 included in this description is:

• Memory Map and Registers

• Timer/Counters

• Interrupt System

MEMORY MAP AND REGISTERS

Memory

The AT89C51 has separate address spaces for program and data memory. The

program and data memory can be up to 64K bytes long. The lower 4K program memory can

reside on-chip. The AT89C51 has 128 bytes of on-chip RAM.

The lower 128 bytes can be accessed either by direct addressing or by indirect

addressing. The lower 128 bytes of RAM can be divided into 3 segments as listed below

1. Register Banks 0-3: locations 00H through 1FH (32 bytes). The device after reset defaults

to register bank 0. To use the other register banks, the user must select them in software. Each

register bank contains eight 1-byte registers R0-R7. Reset initializes the stack point to

location 07H, and is incremented once to start from 08H, which is the first register of the

second register bank.

2. Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH. Each one

of the 128 bits of this segment can be directly addressed (0-7FH). Each of the 16 bytes in this

segment can also be addressed as a byte.

3. Scratch Pad Area: 30H-7FH are available to the user as data RAM. However, if the data

pointer has been initialized to this area, enough bytes should be left aside to prevent SP data

destruction.

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFR's) are located in upper 128 Bytes direct

addressing area. The SFR Memory Map in shows that.

Not all of the addresses are occupied. Unoccupied addresses are not implemented on

the chip. Read accesses to these addresses in general return random data, and write accesses

have no effect. User software should not write 1s to these unimplemented locations, since

they may be used in future microcontrollers to invoke new features. In that case, the reset or

inactive values of the new bits will always be 0, and their active values will be 1.

The functions of the SFR’s are outlined in the following sections.

Accumulator (ACC)

ACC is the Accumulator register. The mnemonics for Accumulator-specific instructions,

however, refer to the Accumulator simply as A.

B Register (B)

The B register is used during multiply and divide operations. For other instructions it can be

treated as another scratch pad register.

Program Status Word (PSW)

The PSW register contains program status information.

Stack Pointer (SP)

The Stack Pointer Register is eight bits wide. It is incremented before data is stored during

PUSH and CALL executions. While the stack may reside anywhere in on chip RAM, the

Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H.

Data Pointer (DPTR)

The Data Pointer consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a

16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit

registers.

Serial Data Buffer (SBUF)

The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive

buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held

for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is

moved from SBUF, it comes from the receive buffer.

Timer Registers

Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit Counter registers for

Timer/Counters 0 and 1, respectively.

Control Registers

Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and

status bits for the interrupt system, the Timer/Counters, and the serial port.

TIMER/COUNTERS

The IS89C51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. All two

can be configured to operate either as Timers or event counters. As a Timer, the register is

incremented every machine cycle. Thus, the register counts machine cycles. Since a machine

cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

As a Counter, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 and T1. The external input is sampled during S5P2 of

every machine cycle. When the samples show a high in one cycle and a low in the next

cycle, the count is incremented. The new count value appears in the register during S3P1 of

the cycle following the one in which the transition was detected. Since two machine cycles

(24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate

is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external

input signal, but it should be held for at least one full machine cycle to ensure that a given

level is sampled at least once before it changes.

In addition to the Timer or Counter functions, Timer 0 and Timer 1 have four operating

modes: 13-bit timer, 16-bit timer, 8-bit auto-reload, split timer.

TIMERS:

SFR’S USED IN TIMERS

The special function registers used in timers are,

TMOD Register

TCON Register

Timer(T0) & timer(T1) Registers

(i) TMOD Register:

TMOD is dedicated solely to the two timers (T0 & T1).

The timer mode SFR is used to configure the mode of operation of each of the two

timers. Using this SFR your program may configure each timer to be a 16-bit timer, or

13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may

configure the timers to only count when an external pin is activated or to count

“events” that are indicated on an external pin.

It can consider as two duplicate 4-bit registers, each of which controls the action of

one of the timers.

(ii) TCON Register:

The timer control SFR is used to configure and modify the way in which the 8051’s

two timers operate. This SFR controls whether each of the two timers is running or

stopped and contains a flag to indicate that each timer has overflowed. Additionally,

some non-timer related bits are located in TCON SFR.

These bits are used to configure the way in which the external interrupt flags are

activated, which are set when an external interrupt occurs.

(iii) TIMER 0 (T0): TO (Timer 0 low/high, address 8A/8C h)

These two SFR’s taken together represent timer 0. Their exact behavior

depends on how the timer is configured in the TMOD SFR; however, these timers

always count up. What is configurable is how and when they increment in value.

(iv) TIMER 1 (T1):

T1 (Timer 1 Low/High, address 8B/ 8D h)

These two SFR’s, taken together, represent timer 1. Their exact behavior depends on how the

timer is configured in the TMOD SFR; however, these timers always count up. What is

Configurable is how and when they increment in value.

The Timer or Counter function is selected by control bits C/T in the Special Function

Register TMOD. These two Timer/Counters have four operating modes, which are selected

by bit pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timer/Counters,

but Mode 3 is different.

The four modes are described in the following sections.

Mode 0:

Both Timers in Mode 0 are 8-bit Counters with a divide-by-32 pre scalar. Figure 8

shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is

configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer

interrupt flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE

= 0 or INT1 = 1. Setting GATE = 1 allows the Timer to be controlled by external input INT1,

to facilitate pulse width measurements. TR1 is a control bit in the Special Function Register

TCON. Gate is in TMOD.

The 13-bit register consists of all eight bits of TH1 and the lower five bits of

TL1. The upper three bits of TL1 are indeterminate and should be ignored. Setting the run

flag (TR1) does not clear the registers.

Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and

INT0 replace the corresponding Timer 1 signals. There are two different GATE bits, one for

Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Mode 1

Mode 1 is the same as Mode 0, except that the Timer register is run with all 16 bits.

The clock is applied to the combined high and low timer registers (TL1/TH1). As clock

pulses are received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on

the FFFFH-to-0000H overflow flag. The timer continues to count. The overflow flag is the

TF1 bit in TCON that is read or written by software

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic

reload, as shown in Figure 10. Overflow from TL1 not only sets TF1, but also reloads TL1

with the contents of TH1, which is preset by software. The reload leaves the TH1 unchanged.

Mode 2 operation is the same for Timer/Counter 0.

Mode 3

Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0and TH0 as two separate counters. The logic for Mode 3

on Timer 0 is shown in Figure 11. TL0 uses the Timer 0 control bits: C/T, GATE, TR0,

INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and over the

use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt.

Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in

Mode 3, the AT89C51 can appear to have three Timer/Counters. When Timer 0 is in Mode 3,

Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case,

Timer 1 can still be used by the serial port as a baud rate generator or in any application not

requiring an interrupt.

INTERRUPT SYSTEM

An interrupt is an external or internal event that suspends the operation of micro

controller to inform it that a device needs its service. In interrupt method, whenever any

device needs its service, the device notifies the micro controller by sending it an interrupt

signal. Upon receiving an interrupt signal, the micro controller interrupts whatever it is doing

and serves the device. The program associated with interrupt is called as interrupt service

subroutine (ISR).Main advantage with interrupts is that the micro controller can serve many

devices.

Baud Rate

The baud rate in Mode 0 is fixed as shown in the following equation. Mode 0 Baud

Rate = Oscillator Frequency /12 the baud rate in Mode 2 depends on the value of the SMOD

bit in Special Function Register PCON. If SMOD = 0 the baud rate is 1/64 of the oscillator

frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency.

Mode 2 Baud Rate = 2SMODx (Oscillator Frequency)/64.

In the IS89C51, the Timer 1 overflow rate determines the baud rates in Modes 1 and 3.

NUMBER OF INTERRUPTS IN 89C51:

There are basically five interrupts available to the user. Reset is also considered as an

interrupt. There are two interrupts for timer, two interrupts for external hardware interrupt

and one interrupt for serial communication.

Memory location Interrupt name

0000H Reset

0003H External interrupt 0

000BH Timer interrupt 0

0013H External interrupt 1

001BH Timer interrupt 1

0023H Serial COM interrupt

Lower the vector, higher the priority. The External Interrupts INT0 and INT1 can

each be either level-activated or transition-activated, depending on bits IT0 and IT1 in

Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in

TCON. When the service routine is vectored, hardware clears the flag that generated an

external interrupt only if the interrupt was transition-activated. If the interrupt was level-

activated, then the external requesting source (rather than the on-chip hardware) controls the

request flag. The Timer 0 and Timer 1 Interrupts are generated by TF0and TF1, which are set

by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode

3).When a timer interrupt is generated, the on-chip hardware clears the flag that is generated.

The Serial Port Interrupt is generated by the logical OR of RI and TI. The service

routine normally must determine whether RI or TI generated the interrupt, and the bit must be

cleared in software.

All of the bits that generate interrupts can be set or cleared by software, with the same

result as though they had been set or cleared by hardware. That is, interrupts can be generated

and pending interrupts can be canceled in software.

Each of these interrupt sources can be individually enabled or disabled by setting or

clearing a bit in Special Function Register IE (interrupt enable) at address 0A8H. There is a

global enable/disable bit that is cleared to disable all interrupts or to set the interrupts.

IE (Interrupt enable register) :

Steps in enabling an interrupt:

Bit D7 of the IE register must be set to high to allow the rest of register to take effect.

If EA=1, interrupts are enabled and will be responded to if their corresponding bits in IE are

high. If EA=0, no interrupt will be responded to even if the associated bit in the IE register is

high.

Description of each bit in IE register:

D7 bit: Disables all interrupts. If EA =0, no interrupt is acknowledged, if EA=1 each

interrupt source is individually enabled or disabled by setting or clearing its enable bit.

D6 bit: Reserved.

D5 bit: Enables or disables timer 2 over flow interrupt (in 8052).

D4 bit: Enables or disables serial port interrupt.

D3 bit: Enables or disables timer 1 over flow interrupt.

D2 bit: Enables or disables external interrupt 1.

D1 bit: Enables or disables timer 0 over flow interrupt.

D0 bit: Enables or disables external interrupt 0.

Interrupt priority in 89C51:

There is one more SRF to assign priority to the interrupts which is named as interrupt

priority (IP). User has given the provision to assign priority to one interrupt. Writing one to

that particular bit in the IP register fulfils the task of assigning the priority.

Description of each bit in IP register:

D7 bit: Reserved.

D6 bit: Reserved.

D5 bit: Timer 2 interrupt priority bit (in 8052).

D4 bit: Serial port interrupt priority bit.

D3 bit: Timer 1 interrupt priority bit.

D2 bit: External interrupt 1 priority bit.

D1 bit: Timer 0 interrupt priority bit.

D0 bit: External interrupt 0 priority bit.

1. PROGRAM TO DEMONSTRATE SWITCH & LED#include<at89x51.h> // Includes definition of 8051 //DEFINE CONSTANT

#define LED_PIN P1_0 // define port P1_0 as LED #define SWITCH_PIN P1_1 // define port P1_1 as switch#define INPUT_PIN 1 // define 1 as INPUT_PIN #define PRESSED 0//DEFINE MACROS#define LEDOn() LED_PIN = 0#define LEDOff() LED_PIN = 1//FUNCTION DEFINESvoid main(void) // main function begins{

bit SwitchState; //Declare a bit "SwitchState" to store the value of switch

LED_PIN = INPUT_PIN; //LED acts as input pinSWITCH_PIN = INPUT_PIN; //Switch acts as input pin for(;;) { //loop forever SwitchState = SWITCH_PIN; //copies value of switch to bit SwitchState

if(SwitchState == PRESSED) //check if it is pressedLEDOn(); // if yes , led on

elseLEDOff(); // if no , led off

}} //end of main function

2. PROGRAM TO DEMONSTRATE RELAY//INCLUDES DEFINITION OF 89C51 #include <REGX51.H> //CONSTANT DEFINES #define INPUT_PIN 1 // define 1 as INPUT_PIN #define LOW 0#define HIGH 1//PINS DEFINE #define RELAY_PIN P1_0 // define port P1_0 as LED i.e connect LED to P1_0//DEFINE MACROS#define RELAYOn() RELAY_PIN = LOW#define RELAYOff() RELAY_PIN = HIGH//FUNCTIONS PROTOYPESvoid main(void);void Delay(unsigned int time);//main function beginsvoid main(void) {

RELAY_PIN = INPUT_PIN; // LED acts as input for(;;) // loop forever{

RELAYOn(); // Turn on ledDelay(1000); // delay for 500msec = 0.5 secRELAYOff(); // Turn off ledDelay(1000); // delay for 500msec = 0.5 sec

} // end of while loop} // end of main function// PROGRAM ROUTINESvoid Delay(unsigned int time){

unsigned char pause; // Declare variable pause as unsigned charwhile( time > 0) // loop until time is greater than zero{

pause = 150; // Initialize pause to 150 (decimal value)while(pause--); // Decrement pause until it becomes zerotime--; // Decrement time and loop back until time

} // value becomes zero} // End of Delay function

3. PROGRAM TO DEMONSTRATE BUZZER//INCLUDES DEFINITION OF 89C51 #include <REGX51.H> //CONSTANT DEFINES #define INPUT_PIN 1 // define 1 as INPUT_PIN #define LOW 0#define HIGH 1//PINS DEFINE #define BUZZER_PIN P1_0 // define port P1_0 as SWITCH i.e connect LED to P1_0//DEFINE MACROS#define BUZZEROn() BUZZER_PIN = LOW#define BUZZEROff() BUZZER_PIN = HIGH//FUNCTIONS PROTOYPESvoid main(void);void Delay(unsigned int time);//main function beginsvoid main(void) {

BUZZER_PIN = INPUT_PIN; // SWITCH acts as input for(;;) // loop forever{

BUZZEROn(); //BUZZER SOUND Turn on Delay(1000); // delay for 500msec = 0.5 secBUZZEROff(); // BUZZER SOUND Turn offDelay(1000); // delay for 500msec = 0.5 sec

} // end of while loop} // end of main function// PROGRAM ROUTINESvoid Delay(unsigned int time){

unsigned char pause; // Declare variable pause as unsigned charwhile( time > 0) // loop until time is greater than zero{

pause = 150; // Initialize pause to 150 (decimal value)while(pause--); // Decrement pause until it becomes zerotime--; // Decrement time and loop back until time

} // value becomes zero} // End of Delay function

4. PROGRAM TO DEMONSTRATE LCD USING ARM PROCESSOR (KIT NO:4 2148)#include<lpc214x.h>/* Configure the data bus and Control bus as per the hardware connection */#define LcdDataBusPort IO1PIN#define LcdControlBusPort IO1PIN#define LcdDataBusDirnReg IO1DIR#define LcdCtrlBusDirnReg IO1DIR#define LCD_RS 16#define LCD_RW 0#define LCD_EN 17#define LCD_D4 18#define LCD_D5 19#define LCD_D6 20#define LCD_D7 21 /* Masks for configuring the DataBus and Control Bus direction */#define LCD_ctrlBusMask ((1<<LCD_RS)|(1<<LCD_RW)|(1<<LCD_EN))#define LCD_dataBusMask ((1<<LCD_D4)|(1<<LCD_D5)|(1<<LCD_D6)|(1<<LCD_D7))/* local function to generate some delay */void delay(int cnt){ int i,j; for(i=0;i<cnt;i++)

for(j=0;j<10;j++);}

/* Function send the a nibble on the Data bus (LCD_D4 to LCD_D7) */void sendNibble(char nibble){ LcdDataBusPort &= ~(LCD_dataBusMask); // Clear previous data LcdDataBusPort|= (((nibble >>0x00) & 0x01) << LCD_D4); LcdDataBusPort|= (((nibble >>0x01) & 0x01) << LCD_D5); LcdDataBusPort|= (((nibble >>0x02) & 0x01) << LCD_D6); LcdDataBusPort|= (((nibble >>0x03) & 0x01) << LCD_D7);}/* Function to send the command to LCD. As it is 4bit mode, a byte of data is sent in two 4-bit nibbles */void Lcd_CmdWrite(char cmd){ sendNibble((cmd >> 0x04) & 0x0F); //Send higher nibble LcdControlBusPort &= ~(1<<LCD_RS); // Send LOW pulse on RS pin for selecting Command register

LcdControlBusPort &= ~(1<<LCD_RW); // Send LOW pulse on RW pin for Write operation LcdControlBusPort |= (1<<LCD_EN); // Generate a High-to-low pulse on EN pin delay(1000); LcdControlBusPort &= ~(1<<LCD_EN); delay(1000); sendNibble(cmd & 0x0F); //Send Lower nibble LcdControlBusPort &= ~(1<<LCD_RS); // Send LOW pulse on RS pin for selecting Command register LcdControlBusPort &= ~(1<<LCD_RW); // Send LOW pulse on RW pin for Write operation LcdControlBusPort |= (1<<LCD_EN); // Generate a High-to-low pulse on EN pin delay(1000); LcdControlBusPort &= ~(1<<LCD_EN); delay(1000);}void Lcd_DataWrite(char dat){ sendNibble((dat >> 0x04) & 0x0F); //Send higher nibble LcdControlBusPort |= (1<<LCD_RS); // Send HIGH pulse on RS pin for selecting data register LcdControlBusPort &= ~(1<<LCD_RW); // Send LOW pulse on RW pin for Write operation LcdControlBusPort |= (1<<LCD_EN); // Generate a High-to-low pulse on EN pin delay(1000); LcdControlBusPort &= ~(1<<LCD_EN); delay(1000); sendNibble(dat & 0x0F); //Send higher nibble LcdControlBusPort |= (1<<LCD_RS); // Send HIGH pulse on RS pin for selecting data register LcdControlBusPort &= ~(1<<LCD_RW); // Send LOW pulse on RW pin for Write operation LcdControlBusPort |= (1<<LCD_EN); // Generate a High-to-low pulse on EN pin delay(1000); LcdControlBusPort &= ~(1<<LCD_EN); delay(1000);}

int main(){ char i,a[]={"DONE HERE!"}; LcdDataBusDirnReg |= LCD_dataBusMask; // Configure all the LCD pins as output

LcdCtrlBusDirnReg |= LCD_ctrlBusMask; Lcd_CmdWrite(0x02); // Initialize Lcd in 4-bit mode Lcd_CmdWrite(0x28); // enable 5x7 mode for chars Lcd_CmdWrite(0x0E); // Display OFF, Cursor ON Lcd_CmdWrite(0x01); // Clear Display Lcd_CmdWrite(0x80); // Move the cursor to beginning of first line Lcd_DataWrite('H'); Lcd_DataWrite('I'); // Lcd_DataWrite('l'); // Lcd_DataWrite('l'); //Lcd_DataWrite('o'); Lcd_CmdWrite(0xc0); for(i=0;a[i]!=0;i++) { Lcd_DataWrite(a[i]); } while(1);}

5. CODE FOR 7 SEGMENT DISPLAY INTERFACING WITH 8051 MICROCONTROLLER (AT89S52)

#include<REGX52.h>void msdelay(unsigned int time) // Function for creating delay in milliseconds.{ unsigned i,j ; for(i=0;i<time;i++) for(j=0;j<1275;j++);}void main(){ unsigned char no_code[]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90}; //Array for hex values (0-9) for common anode 7 segment int k; while(1) { for(k=0;k<10;k++) { P1=no_code[k]; msdelay(200); } }}

6.Implementation of program for alternate LEDs#include<reg51.h>#define LED P2void delay(unsigned int d);int main(void){while(1){unsigned int i;LED=0x55;for(i=0;i<=7;i++){delay(10000);LED=LED<<0x55;}LED=0xAA;for(i=0;i<=7;i++){delay(10000);LED=LED>>0xAA;}}}void delay (unsigned int d){unsigned int a,b;for(a=0;a<d;a++);for(b=0;b<101;b++);}

7. Implementation of program for ascending order leds

#include <reg51.h>#define LED P2void delay(unsigned int d);main(){while(1){int i;LED=0x00;for(i=0;i<=15;i++){delay(10000);LED=LED-1;}}}void delay(unsigned int d){int i,j;for(i=0;i<d;i++);for(j=0;j<101;j++);}

8.Implementation of descending order leds

#include <reg51.h>#define LED P2void delay(unsigned int d);main(){while(1){int i;LED=0x0F;for(i=15;i>=0;i--){delay(10000);LED=LED-1;}}}void delay(unsigned int d){int i,j;for(i=0;i<d;i++);for(j=0;j<101;j++);}

9.Implementation of program for mod 4#include<regx51.h>#define SEG1{P3_3=1;P3_4=0;P3_5=0;}#define NULL{P3_3=1;P3_4=0;P3_5=0;}void delay(unsigned int d);code unsigned char;seg[10]={0xc0,0xf9,0x94,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};int main(void){int a=0,b=8,c;while(1){NULLSEG1c=a%b;P0=seg[c];a++;delay(10000);}}void delay(unsigned int d){unsigned int i,j;for(i=0;i<d;i++);for(j=0;j<101;j++);}

10.Implementation of binary counter of 32 bit interfacing with LEDS

#include<reg51.h>#define LED P2void delay(unsigned int d);main(){while(1){

int i;LED=0x00;

for(i=0;i<=32;i++){

delay(10000);LED=LED+1;}}}void delay(unsigned int d){unsigned int i,j;for(i=0;i<d;i++);for(j=0;j<101;j++);}

11. Implementation of stepper motor

#include<reg51.h>#define LED P2void delay(unsigned int d);main(){while(1){P2=0x01;

delay(1000);P2=0x02;delay(1000);P2=0x04;delay(1000);P2=0x08;delay(1000);

}}void delay(unsigned int d){unsigned int i,j;for(i=0;i<d;i++);for(j=0;j<101;j++);}

12. Implementation of program for Elevetor #include<reg51.h>#define LED P2#define LED P3#define LED P1void delay(unsigned int d);code unsigned char seg7[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};code unsigned char motor4[8]={0x01,0x03,0x02,0x06,0x04,0x0C,0x08,0x09};code unsigned char motord[8]={0x09,0x08,0x0C,0x04,0x06,0x02,0x03,0x01};

#define SEG7{P3_5=1};int main(void)

{unsigned char loc, pre=0x01,seg=0,i,j;loc=pre;//P3_5=1;P2=pre;P1=0xFF;P0=seg7[seg];while(1)

{P1=0xFF;

while(P1==0xFF)loc=~P1;

if(loc<pre){

while(loc!=pre){

pre=pre>>1;seg--;for(j=0;j<4;j++)for(i=0;i<8;i++){

P2=motor4[i];delay(50);

}P0=seg7[seg];

}}else if(loc>pre){

while(loc!=pre){

pre=pre<<1;seg++;for(j=0;i<4;j++)

for(i=0;i<8;i++){

P2=motord[i];delay(50);

}P0=seg7[seg];

}

}

}

}

void delay(unsigned int d)

{

unsigned int i,j;

for(i=0;i<d;i++);

for(j=0;j<101;j++);

}

13. Implementation of External Interrupts

#include<reg51.h>

sbit led1= P2^0;

sbit led2= P2^1;

sbit led3= P2^2;

sbit led4= P2^3;

void ISR_ex0(void);

void Delay();

void main()

{

P0 = 0x00; // Make all pins zero



P3 = 0x04; // making Port3 pin 2 high

IE=0x81; // Enable INT0

IT0=1; // Set Falling Edge Trigger for INT0

while(1)

{

led1= 0;

led2= 1;

led3= 0;

led4= 0;

}

}

void ISR_ex0(void) interrupt 0 // ISR for external interrupt INT0

{

led1=~led1;

led2=~led2;

led3=~led3;

led4=~led4;

Delay();

}

void Delay()

{

int i;

TMOD = 0x01; // Timer0 mode1

for(i=0;i<200;i++)

{

TH0=0xF8; //initial values for 1sec delay

TL0=0xCC;

TR0 = 1; // timer0 start

while (TF0 == 0); // check overflow condition

TR0 = 0; // Stop Timer

TF0 = 0; // Clear flag

}

}

14. Implementation for Keypad

#include<reg51.h>#define display_port P2 //Data pins connected to port 2 on microcontrollersbit rs = P3^2; //RS pin connected to pin 2 of port 3sbit rw = P3^3; // RW pin connected to pin 3 of port 3sbit e = P3^4; //E pin connected to pin 4 of port 3

sbit C4 = P1^0; // Connecting keypad to Port 1sbit C3 = P1^1;sbit C2 = P1^2;sbit C1 = P1^3;sbit R4 = P1^4;sbit R3 = P1^5;sbit R2 = P1^6;sbit R1 = P1^7;

void msdelay(unsigned int time) // Function for creating delay in milliseconds.{ unsigned i,j ; for(i=0;i<time;i++) for(j=0;j<1275;j++);}void lcd_cmd(unsigned char command) //Function to send command instruction to LCD{ display_port = command; rs= 0; rw=0; e=1; msdelay(1); e=0;}

void lcd_data(unsigned char disp_data) //Function to send display data to LCD{ display_port = disp_data; rs= 1; rw=0; e=1; msdelay(1); e=0;}

void lcd_init() //Function to prepare the LCD and get it ready{ lcd_cmd(0x38); // for using 2 lines and 5X7 matrix of LCD msdelay(10); lcd_cmd(0x0F); // turn display ON, cursor blinking msdelay(10); lcd_cmd(0x01); //clear screen

msdelay(10); lcd_cmd(0x81); // bring cursor to position 1 of line 1 msdelay(10);}

void row_finder1() //Function for finding the row for column 1{R1=R2=R3=R4=1;C1=C2=C3=C4=0;

if(R1==0)lcd_data('1');if(R2==0)lcd_data('4');if(R3==0)lcd_data('7');if(R4==0)lcd_data('*');}


if(R1==0)lcd_data('2');if(R2==0)lcd_data('5');if(R3==0)lcd_data('8');if(R4==0)lcd_data('0');}


if(R1==0)lcd_data('3');if(R2==0)lcd_data('6');if(R3==0)lcd_data('9');if(R4==0)lcd_data('#');}


if(R1==0)lcd_data('A');if(R2==0)lcd_data('B');if(R3==0)lcd_data('C');if(R4==0)lcd_data('D');}

void main(){ lcd_init(); while(1) { msdelay(30); C1=C2=C3=C4=1; R1=R2=R3=R4=0; if(C1==0) row_finder1(); else if(C2==0) row_finder2(); else if(C3==0) row_finder3(); else if(C4==0) row_finder4(); }

}

15. Program for ADC INTERFACING#include<reg52.h>#include<stdio.h>/* Configure the data bus and Control pins as per the hardware connection Databus is connected to P2_0:P2_7 and control bus P0_0:P0_2*/#define LcdDataBus P2sbit LCD_RS = P0^0;sbit LCD_RW = P0^1;sbit LCD_EN = P0^2;

sbit ale=P3^3; sbit oe=P3^6; sbit sc=P3^4; sbit eoc=P3^5; sbit clk=P3^7; sbit ADDA=P3^0; //Address pins for selecting input channels.sbit ADDB=P3^1;sbit ADDC=P3^2;

#define input_port P1 //ADCint result[3],number;

void Lcd_CmdWrite( char);void Lcd_DataWrite( char );void lcdprint(unsigned char *);

void timer0() interrupt 1 // Function to generate clock of frequency 500KHZ using Timer 0 interrupt.{clk=~clk;}

void delay(unsigned int count) {int i,j;for(i=0;i<count;i++) for(j=0;j<100;j++);}

void lcd_ini() //Function to inisialize the LCD{ Lcd_CmdWrite(0x38); // enable 5x7 mode for chars Lcd_CmdWrite(0x0E); // Display OFF, Cursor ON Lcd_CmdWrite(0x01); // Clear Display Lcd_CmdWrite(0x80); // Move the cursor to beginning of first line}

void show(){ sprintf(result,"%d",number);

lcdprint(result); lcdprint(" ");}

void read_adc(){ number=0; ale=1; sc=1; delay(1); ale=0; sc=0; while(eoc==1); while(eoc==0); oe=1; number=input_port; delay(1); oe=0;}

void adc(int i) //Function to drive ADC{switch(i) { case 0: ADDC=0; // Selecting input channel IN0 using address lines ADDB=0; ADDA=0; Lcd_CmdWrite(0xc0); read_adc(); show(); break;

case 1: ADDC=0; // Selecting input channel IN1 using address lines ADDB=0; ADDA=1; Lcd_CmdWrite(0xc6); read_adc(); show(); break;

case 2: ADDC=0; // Selecting input channel IN2 using address lines ADDB=1; ADDA=0; Lcd_CmdWrite(0xcc); read_adc(); show(); break;

}}void lcdprint(unsigned char *str) //Function to send string data to LCD.{ while(*str) { Lcd_DataWrite(*str); str++; }}

int main(){ int i=0; eoc=1; ale=0; oe=0; sc=0; TMOD=0x02; TH0=0xFD;lcd_ini();

lcdprint(" ADC Interfacing");delay(500);Lcd_CmdWrite(1);lcdprint("Ambedsys ");Lcd_CmdWrite(192);lcdprint("System Ready... ");delay(500);Lcd_CmdWrite(1);lcdprint("Ch1"); IE=0x82; TR0=1;while(1){

//adc(0);//number=0;

//} for(i=0;i<2;i++) { adc(i); number=0; } }}

/* local function to generate delay */void delay_us(int cnt){ int i;

for(i=0;i<cnt;i++);}

/* Function to send the command to LCD */void Lcd_CmdWrite( char cmd){ LcdDataBus=cmd; // Send the command to LCD LCD_RS=0; // Select the Command Register by pulling RS LOW LCD_RW=0; // Select the Write Operation by pulling RW LOW LCD_EN=1; // Send a High-to-Low Pusle at Enable Pin delay_us(10); LCD_EN=0; delay_us(1000);}

/* Function to send the Data to LCD */void Lcd_DataWrite( char dat){ LcdDataBus=dat; // Send the data to LCD LCD_RS=1; // Select the Data Register by pulling RS HIGH LCD_RW=0; // Select the Write Operation by pulling RW LOW LCD_EN=1; // Send a High-to-Low Pusle at Enable Pin delay_us(10); LCD_EN=0; delay_us(1000);}

16. DEVELOP CONTROL APPLICATION AS TRAFFIC CONTROLLER

#include<regx51.h>// Define 8051 Registers#include <stdio.h>//Define I/O Functionsvoid delay(unsigned int d); //Delay Function

unsigned char code str[6]={0x18,0x08,0xb5,0x66,0x18,0xe5};/********************* Main Function ****************************/void main (){unsigned int i=0;int k,count=3;P0=0x00;//Port 0 is assign for red lightP1=0x00;//port1 is assign for green lightP2=0x00;//port2 is assign for yellow lightfor(k=0;k<6;k++){for(i=0;i<count;i++){P0=str[i];delay(10);i++;P1=str[i];delay(10);i++;P2=str[i];delay(10);delay(10);}count=count+3;delay(20);}}/******************** Delay Subroutine ****************************/void delay(unsigned int d){

unsigned int k,j;for(k=0;k<100;k++);for(j=0;j<100;j++);

}

ALU’s comprise the combinational logic that implements logic operations such as AND, OR, NOT gate and arithmetic operations, such as Adder, Subtractor.

Functional Description of 4-bit Arithmetic Logic Unit

Controlled by the three function select inputs (sel 2 to 0), ALU can perform all the 8 possible logic operations

1. Implementation of ALU using VHDL code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity alu is

Port ( inp_a : in signed(3 downto 0);

inp_b : in signed(3 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

out_alu : out signed(3 downto 0));

end alu;

architecture Behavioral of alu is

begin

process(inp_a, inp_b, sel)

begin

case sel is

when "000" =>

out_alu<= inp_a + inp_b; --addition

when "001" =>

out_alu<= inp_a - inp_b; --subtraction

when "010" =>

out_alu<= inp_a - 1; --sub 1

when "011" =>

out_alu<= inp_a + 1; --add 1

when "100" =>

out_alu<= inp_a and inp_b; --AND gate

when "101" =>

out_alu<= inp_a or inp_b; --OR gate

when "110" =>

out_alu<= not inp_a ; --NOT gate

when "111" =>

out_alu<= inp_a xor inp_b; --XOR gate

when others =>

NULL;

end case;

end process;

UUT TEST BENCH VHDL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY tb_alu IS

END tb_alu;

ARCHITECTURE behavior OF tb_alu IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT alu

PORT(

inp_a : IN signed(3 downto 0);

inp_b : IN signed(3 downto 0);

sel : IN std_logic_vector(2 downto 0);

out_alu : OUT signed(3 downto 0)

);

END COMPONENT;

--Inputs

signal inp_a : signed(3 downto 0) := (others => '0');

signal inp_b : signed(3 downto 0) := (others => '0');

signal sel : std_logic_vector(2 downto 0) := (others => '0');

--Outputs

signal out_alu : signed(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: alu PORT MAP (

inp_a => inp_a,

inp_b => inp_b,

sel => sel,

out_alu => out_alu

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 n

wait for 100 ns;

-- insert stimulus here

inp_a <= "1001";

inp_b <= "1111";

sel <= "000";

wait for 100 ns;

sel <= "001";

wait for 100 ns;

sel <= "010";

wait for 100 ns;

sel <= "011";

wait for 100 ns;

sel <= "100";

wait for 100 ns;

sel <= "101";

wait for 100 ns;

sel <= "110";

wait for 100 ns;

sel <= "111";

end process;

END;

2. Implementation of vhdl LFSR PRGlibrary ieee; use ieee.std_logic_1164.all;

entity lfsr_bit is port ( reset : in std_logic; clk : in std_logic; rbit_out : out std_logic ); end entity architecture rtl of lfsr_bit is signal lfsr : std_logic_vector (3 downto 0); signal feedback : std_logic; begin -- option for LFSR size 4 feedback <= not(lfsr(3) xor lfsr(2)); sr_pr : process (clk) begin if (rising_edge(clk)) then if (reset = '1') then

lfsr <= (others => '0'); else lfsr <= lfsr(2 downto 0) & feedback; end if; end if; end process sr_pr; rbit_out <= lfsr(3); end architecture;

UUT TEST BENCH VHDL

library ieee; use ieee.std_logic_1164.all; entity tb_lfsr_bit is end entity; architecture test of tb_lfsr_bit is constant PERIOD : time := 10 ns; signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal endSim : boolean := false; component lfsr_bit is port ( reset : in std_logic; clk : in std_logic; rbit_out : out std_logic ); end component; begin clk <= not clk after PERIOD/2; reset <= '0' after PERIOD*10; -- Main simulation process main_pr : process begin wait until (reset = '0'); for i in 0 to 31 loop wait until (clk = '1'); end loop; endSim <= true; end process main_pr; -- End the simulation stop_pr : process begin if (endSim) then

assert false report "End of simulation." severity failure; end if; wait until (clk = '1'); end process stop_pr; DUT : lfsr_bit port map ( clk => clk, reset => reset, rbit_out => open );

CYCLE-IIVHDL (Very High Speed IC Hardware description Language) is one of the standard

hardware description language used to design digital systems. VHDL can be used to design the lowest level (gate level) of a digital system to the highest level (VLSI module). VHDL though being a rigid language with a standard set of rules allows the designer to use different methods of design giving different perspectives to the digital system. description languages available in the market for the digital designers such as Verilog, ABEL, PALASM, CUPL, and etc but VHDL and Verilog are the most widely used Other than VHDL there are many hardware HDLs. The major difference between hardware description programming languages and others is the integration of time. Timing specifications are used to incorporate propagation delays present in the system. Types of Representation:VHDL representation can be seen as text file describing a digital system. The Digital system can be represented in different forms such as a behavioral model or a Structural model. Most commonly known as levels of abstraction, these levels help the designer to develop complex systems efficiently.

Register Transfer Level: RTL typically represents data flow within the systems like data flow between registers. RTL is mostly used for design of combinational logics. Algorithmic Level: In this method, specific instruction set of statements define the sequence of operations in the system. Algorithmic level is mostly used for design of sequential logics. Structural Model:Structural level describes the systems as gates or component block interconnected to perform the desired operations. Structural level is primarily the graphical representation of the digital system and so it is closer to the actual physical representation of the system.VHDL Programming Structure:Entity and Architecture are the two main basic programming structures in VHDL. Entity Entity can be seen as the black box view of the system. We define the inputs and outputs of the system which we need to interface.Entity ANDGATE isPort (A: in std_logic; B: in std_logic; Y: out std_logic); End entity ANDGATE; Entity name ANDGATE is given by the programmer, each entity must have a name.

Architecture: Architecture defines what is in our black box that we described using ENTITY. We can use either behavioral or structural models to describe our system in the architecture. In Architecture we will have interconnections, processes, components, etcArchitecture AND1 of ANDGATE is --declarations Begin--statementsY <= A AND B;End architecture AND1;Entity name or architecture name is user defined. Identifiers can have uppercase alphabets, lowercase alphabets, and numbers and underscore (_).First letter of identifier must be an

alphabet and identifier cannot end with an underscore. In VHDL, keywords and user identifiers are case insensitive. 1. Program for creating a 4 bit ALU using VHDL

ALU (Arithmetic and Logic unit) is a digital circuit that performs logical and arithmetic operations.ALU is found inside every microprocessor or microcontroller in order to perform logical and arithmetic operations. Logical operation involves all logical functions like ANDing two or more inputs, OR, NOT, NOR etc. Arithmetic operation involves function like addition, subtraction etc, Now 4 bits ALU means it will process a 4 bit data and provide output of also 4 bits. So in the entity section a and b are two inputs of 4 bits and y is the out of also 4 bits. sel is a selection line of three bit which is required to perform various function on the inputs a and b. So for different value of s different operations are performed on the two inputs like when sel="111” a and b are passed through an OR gate and an output is generated on y. In the architecture case statement is used in which according to changing value sel different operations are performed on inputs a and b.

ALU’s comprise the combinational logic that implements logic operations such as AND, OR, NOT gate and arithmetic operations, such as Adder, Subtractor.

Functional Description of 4-bit Arithmetic Logic Unit

Controlled by the three function select inputs (sel 2 to 0), ALU can perform all the 8 possible logic operations

1. Implementation of ALU using VHDL code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity alu is

Port ( inp_a : in signed(3 downto 0);

inp_b : in signed(3 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

out_alu : out signed(3 downto 0));

end alu;

architecture Behavioral of alu is

begin

process(inp_a, inp_b, sel)

begin

case sel is

when "000" =>

out_alu<= inp_a + inp_b; --addition

when "001" =>

out_alu<= inp_a - inp_b; --subtraction

when "010" =>

out_alu<= inp_a - 1; --sub 1

when "011" =>

out_alu<= inp_a + 1; --add 1

when "100" =>

out_alu<= inp_a and inp_b; --AND gate

when "101" =>

out_alu<= inp_a or inp_b; --OR gate

when "110" =>

out_alu<= not inp_a ; --NOT gate

when "111" =>

out_alu<= inp_a xor inp_b; --XOR gate

when others =>

NULL;

end case;

end process;

// UUT TEST BENCH VHDL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY tb_alu IS

END tb_alu;

ARCHITECTURE behavior OF tb_alu IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT alu

PORT(

inp_a : IN signed(3 downto 0);

inp_b : IN signed(3 downto 0);

sel : IN std_logic_vector(2 downto 0);

out_alu : OUT signed(3 downto 0)

);

END COMPONENT;

--Inputs

signal inp_a : signed(3 downto 0) := (others => '0');

signal inp_b : signed(3 downto 0) := (others => '0');

signal sel : std_logic_vector(2 downto 0) := (others => '0');

--Outputs

signal out_alu : signed(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: alu PORT MAP (

inp_a => inp_a,

inp_b => inp_b,

sel => sel,

out_alu => out_alu

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 n

wait for 100 ns;

-- insert stimulus here

inp_a <= "1001";

inp_b <= "1111";

sel <= "000";

wait for 100 ns;

sel <= "001";

wait for 100 ns;

sel <= "010";

wait for 100 ns;

sel <= "011";

wait for 100 ns;

sel <= "100";

wait for 100 ns;

sel <= "101";

wait for 100 ns;

sel <= "110";

wait for 100 ns;

sel <= "111";

end process;

END;

2. Program for creating pseudo random numbers using a LFSR

A shift register when clocked, advances the signal through the register from one bit to the next most-significant bit.Linear feedback shift register (LFSR)

A linear feedback shift register can be formed by performing XOR on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip-flops.

Pseudorandom Pattern Generation

Linear feedback shift registers make extremely good pseudorandom pattern generators.

When the outputs of the flip-flops are loaded with a seed value (anything except all 0s, which would cause the LFSR to produce all 0 patterns) and when the LFSR is clocked, it will generate a pseudorandom pattern of 1s and 0s.

Note that the only signal necessary to generate the test patterns is the clock.

Maximal-length LFSR A maximal-length LFSR produces the maximum number of PRPG patterns possible and has a pattern count equal to 2n – 1, where n is the number of register elements in the LFSR. It produces patterns that have an approximately equal number of 1s and 0s and have an equal number of runs of 1s and 0s.

4-bit Maximal-Length LFSR Maximal length LFSR

Because there is no way to predict mathematically if an LFSR will be maximal length, Peterson and Weldon2 have compiled tables of maximal-length LFSRs to which designers may refer.16 bit Maximal LFSR

library ieee; use ieee.std_logic_1164.all; entity lfsr_bit is port ( reset : in std_logic; clk : in std_logic; rbit_out : out std_logic ); end entity architecture rtl of lfsr_bit is signal lfsr : std_logic_vector (3 downto 0); signal feedback : std_logic; begin feedback <= not(lfsr(3) xor lfsr(2)); sr_pr : process (clk) begin if (rising_edge(clk)) then if (reset = '1') then lfsr <= (others => '0'); else lfsr <= lfsr(2 downto 0) & feedback; end if; end if; end process sr_pr; rbit_out <= lfsr(3); end architecture;///UUT TEST BENCH VHDL

library ieee; use ieee.std_logic_1164.all; entity tb_lfsr_bit is end entity; architecture test of tb_lfsr_bit is constant PERIOD : time := 10 ns; signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal endSim : boolean := false; component lfsr_bit is port ( reset : in std_logic; clk : in std_logic; rbit_out : out std_logic ); end component; begin

clk <= not clk after PERIOD/2; reset <= '0' after PERIOD*10; -- Main simulation process main_pr : process begin wait until (reset = '0'); for i in 0 to 31 loop wait until (clk = '1'); end loop; endSim <= true; end process main_pr; -- End the simulation stop_pr : process begin if (endSim) then assert false report "End of simulation." severity failure; end if; wait until (clk = '1'); end process stop_pr; DUT : lfsr_bit port map ( clk => clk, reset => reset, rbit_out => open );

CYCLE-III

Real-time systems have been defined as: "those systems in which the correctness of the system depends not only on the logical result of the computation, but also on the time at which the results are produced". Real-time system is a mapping of a set of inputs to a set of outputs according to given time constraints– In most applications, a Real-time system never terminates, it runs «for ever». However, the type and amount of input data, the algorithms, then umber of processes, inter process communication, interrupt frequency etc are numerous. This makes a realistic analysis of a Real-time system very difficult. A Sample Real Time System (1)

RTOS Kernel

RTOS Kernel provides an Abstraction layer that hides from application software the hardware details of the processor / set of processors upon which the application software shall run.

RTOS Kernel Functions

The time between the presentation of a set of inputs to a system (stimulus) and the realization of the required behaviour (response), including the availability of all associated outputs, is called the response time of the system. A Real-time system is a system that must satisfy explicit (bounded) response-time constraints or risk severe consequences, including failure. A failed system is a system that can not satisfy one or more of the requirements stipulated in

Application SoftwareRTOS

Hardware

the formal system specification. A Real-time system is one whose logical correctness is based on both the correctness of the outputs and their timeliness.Timing constraint: constraint imposed on timing behavior of a job: hard or soft. Release Time: Instant of time job becomes available for execution. If all jobs are released when the system begins execution, then there is said to be no release time Deadline: Instant of time a job's execution is required to be completed. If deadline is infinity, then job has no deadline. Absolute deadline is equal to release time plus relative deadline Real-time systems are typically characterized as hard, firm and soft. A hard Real-time system is one in which failure to meet a single deadline may lead to complete and catastrophic system failure. Every resource management system must work in the correct order to meet time constraints. No deadline miss is allowed.

DisadvantageLow utilizationA firm Real-time system is one in which a few missed deadlines will not lead to total failure, but missing more than a few may lead to complete and catastrophic system failure.A soft Real-time system is one in which performance is degraded but not destroyed by failure to meet response time constraints.It is similar to hard real-time systems. But it is not necessary that every time constraint be met. Some deadline miss is tolerated.

AdvantageHigh utilizationReliability, availability, safety and securityReliability, availability, safety and security are other important characteristics of Real-

time systems. In particular, for hard Real-time systems, one must guaranteehigh to extreme reliability.Safe– An absolute requirement where life or environment may be endangered (but still such systems fails from time to time…). However, a 100% safe aeroplane is the one which never flies!Periodic Task ModelJobs repeated at regular or semi-regular intervals modeled as periodic. Task Ti is a serious of periodic Jobs Jij.pi - period, minimum interrelease interval between jobs in Task T i. Must be bounded from below.ei - maximum execution time for jobs in task Ti.rij - release time of the jth Job in Task i (Jij in Ti).ji - phase of Task Ti, equal to ri1. H - Hyperperiod = Least Common Multiple of pi for all i: H = lcm(pi), for all i. ui - utilization of Task Ti.U - Total utilization = Sum over all ui.Aperiodic and Sporadic Tasks

A periodic or Sporadic task is a stream of aperiodic or sporadic jobs.Jobs with a task have similar statistical behavior and timing requirementsAssumed system is stationary within the hyperperiod Aperiodic: jobs have soft or no deadlines. Want responsiveness.Sporadic: jobs have hard deadlines Jobs scheduled and allocated resources based on a set of scheduling algorithms and access control protocols.Schedules and Scheduling

Scheduler: Module implementing scheduling algorithmsSchedule: assignment of all jobs to available processors, produced by scheduler.Valid schedule:

every processor assigned to at most one job at a time every job assigned to at most one processor at a time no job scheduled before its release time Total amount of processor time assigned to every job is equal to its maximum or actual

execution time Non-preemptive scheduling is more efficient than preemptive scheduling since preemption incurs context switching overhead which can be significant in fine-grained multithreading systems.

Feasible schedule: Every job starts at or after release time and completes by deadline Schedulable: set of jobs schedulable according to an algorithm it always produces a feasible

schedule. Optimal: Scheduling algorithm optimal if it always produces a feasible schedule if such a

schedule exists Tardiness: Zero if completion time <= deadline, otherwise > 0 (complete - deadline). Lateness: difference between completion time and deadline, can be negative if early. Miss rate: percentage of jobs executed but completed late Loss rate: percentage of jobs discarded Invalid rate: sum of miss and loss rate. makespan : If all jobs have same release time and deadline, then makespan = response time

of the last job to execute. Max or average response times Max or average tardiness/lateness

Task ManagementSet of services used to allow application software developers to design their software

as a number of separate chunks of software each handling a distinct topic, a distinct goal, and sometimes its own real-time deadline. Main service offered is Task Scheduling controls the execution of application software tasks can make them run in a very timely and responsive fashion.

Task SchedulingNon Real -time systems usually use Non-preemptive Scheduling. Once a task starts executing, it completes its full execution.

Most RTOS perform priority-based preemptive task scheduling. Basic rules for priority based preemptive task scheduling. The Highest Priority Task that is Ready to Run, will be the Task that Must be Running.

Priority based Preemptive Task Scheduling Every Task in a software application is assigned a priority. Higher Priority = Higher Need for Quick Response. Follows nested preemption

Nested Preemption

Task Switch (1)Each time the priority-based preemptive scheduler is alerted by an External world trigger / Software trigger it shall go through the following steps that constitute a Task Switch: Determine whether the currently running task should continue to run. Determine which task should run next.Save the environment of the task that was stopped (so it can continue later).Set up the running environment of the task that will run next. Allow the selected task to run.

Task Switch (2)A Non Real time operating system might do task switching only at timer tick times. Even with preemptive schedulers a large array of tasks is searched before a task switch. A Real time OS shall use Incrementally arranged tables to save on time.

Task Switching Timing

Message passing in OS

Most General Purpose OS actually copy messages twice as they transfer them from task to task Via a message queue.

Timeline for Priority-based Preemptive Scheduling

.

D ynamic M emory A llocation in General Purpose OS

Non-real-time operating systems offer memory allocation services from what is termed a Heap.

Heaps suffer from a phenomenon called External Memory Fragmentation. Fragmentation problem is solved by Garbage collection / Defragmentation. Garbage collection algorithms are often wildly non-deterministic.

D ynamic M emory A llocation in RTOS RTOS does it by a mechanism known as Pools. Pools memory allocation mechanism allows application software to allocate chunks of

memory of 4 to 8 different buffer sizes per pool. Pools avoid external memory fragmentation, by not permitting a buffer that is returned to the

pool to be broken into smaller buffers in the future. When a buffer is returned the pool, it is put onto a free buffer list of buffers of its own size

that are available for future re-use at their original buffer size

. PROGRAM FOR TIMING USING RTOS#include <RTL.h> /* RTX kernel functions & defines */#include <LPC214X.H>/* id1, id2 will contain task identifications at run-time */OS_TID id1, id2,id3,id4,id5,id6,id7,id8;/* Forward reference */__task void task1 (void);__task void task2 (void);__task void task3 (void);__task void task4 (void);__task void task5 (void);__task void task6 (void);__task void task7 (void);__task void task8 (void);/*---------------------------------------------------------------------------- Task 1: RTX Kernel starts this task with os_sys_init (task1)

Message Sender Task RAM

MessageRAM Message Receiver Task

Message

*---------------------------------------------------------------------------*/__task void task1 (void) {

unsigned int count=0;IO1DIR=0x40ff0000;IO1SET=1<<30;

IO1CLR=0x00ff0000; id1 = os_tsk_self (); /* Obtain own system task identification number */ os_tsk_prio_self (1);

id2 = os_tsk_create (task2, 1);/* Assign system identification number of task2 to id2 */id3 = os_tsk_create (task3, 1);/* Assign system identification number of task2 to id3 */id4 = os_tsk_create (task4, 1);/* Assign system identification number of task2 to id4 */id5 = os_tsk_create (task5, 1);/* Assign system identification number of task2 to id5 */id6 = os_tsk_create (task6, 1);/* Assign system identification number of task2 to id6 */id7 = os_tsk_create (task7, 1);/* Assign system identification number of task2 to id7 */id8 = os_tsk_create (task8, 1);/* Assign system identification number of task2 to id8 */

while (1){

if(count%2==1) IO1SET=0x00010000;

elseIO1CLR=0x00010000;count++;

os_dly_wait (100); /* Wait now for 50 ms */ }

}

/*---------------------------------------------------------------------------- * Task 2: RTX Kernel starts this task with os_tsk_create (task2, 1)


unsigned int count;while (1)

{if(count%2==1)

IO1SET=0x00020000;elseIO1CLR=0x00020000;count++;

os_dly_wait (20); /* Pause for 20 ms until signaling event to task1 */ }}/*---------------------------------------------------------------------------- * Task 3: RTX Kernel starts this task with os_tsk_create (task2, 1)

*---------------------------------------------------------------------------*/__task void task3 (void) {unsigned int count;

while (1){if(count%2==1)

IO1SET=0x00040000;elseIO1CLR=0x00040000;count++;

os_dly_wait (80); /* Pause for 20 ms until signaling event to task1 */ }}/*---------------------------------------------------------------------------- * Task 4: RTX Kernel starts this task with os_tsk_create (task2, 1)


unsigned int count;while (1)

{if(count%2==1) IO1SET=0x00080000;elseIO1CLR=0x00080000;count++;

os_dly_wait (90) /* Pause for 20 ms until signaling event to task1 */ }}/*---------------------------------------------------------------------------- * Task 5: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task5 (void) {

unsigned int count;while (1){

if(count%2==1) IO1SET=0x00100000;elseIO1CLR=0x00100000;count++;

os_dly_wait (100); /* Pause for 20 ms until signaling event to task1 */ }}

/*----------------------------------------------------------------------------

* Task 6: RTX Kernel starts this task with os_tsk_create (task2, 1)*---------------------------------------------------------------------------*/__task void task6 (void) {unsigned int count;

while (1){


os_dly_wait (120); /* Pause for 20 ms until signaling event to task1 */ }}/*---------------------------------------------------------------------------- * Task 7: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task7 (void) {unsigned int count;

while (1){



while (1){if(count%2==1)

IO1SET=0x00800000;else

IO1CLR=0x00800000;count++;


/*---------------------------------------------------------------------------- * Main: Initialize and start RTX Kernel

*---------------------------------------------------------------------------*/int main (void) { os_sys_init (task1);}

/*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/

2. PROGRAM FOR SIGNALS USING RTOS#include <RTL.h> /* RTX kernel functions & defines */#include <LPC214X.H>/* id1, id2 will contain task identifications at run-time */

OS_TID id1, id2;/* Forward reference */__task void task1 (void);__task void task2 (void);/*---------------------------------------------------------------------------- * Task 1: RTX Kernel starts this task with os_sys_init (task1) *---------------------------------------------------------------------------*/__task void task1 (void) {

IO1DIR=0x40ff0000;IO1SET=1<<30;IO1CLR=0x00ff0000;

id1 = os_tsk_self (); /* Obtain own system task identification number */ id2 = os_tsk_create (task2, 1);/* Assign system identification number of task2 to id2 */

while(1) { os_evt_set (0x0004, id2); /* Indicate to task2 completion of do-this */ IOSET1=0x000F0000; os_evt_wait_or (0x0004, 0xffff);/* Wait for completion of do-that (0xffff means no time-out)*/ IOCLR1=0x000F0000;

os_dly_wait (5); /* Wait now for 50 ms */ }}/*---------------------------------------------------------------------------- * Task 2: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task2 (void) {

while(1) { IOSET1=0x00F00000; os_evt_wait_or (0x0004, 0xffff); /* Wait for completion of do-this (0xffff means no time-out) */ IOCLR1=0x00F00000; os_dly_wait (2); /* Pause for 20 ms until signaling event to task1 */ os_evt_set (0x0004, id1); /* Indicate to task1 completion of do-that */ }}

/*---------------------------------------------------------------------------- * Main: Initialize and start RTX Kernel *---------------------------------------------------------------------------*/int main (void) { os_sys_init (task1);}/*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/

3. PROGRAM FOR SEMAPHORE USING RTOS

#include <RTL.h> /* RTX kernel functions & defines */#include <LPC214X.H>#include "serial0.h"extern void init_serial (void); /* Initialize Serial Interface */OS_TID tsk1, tsk2;OS_SEM semaphore1;/*---------------------------------------------------------------------------- * Task 1 - High Priority - Active every 3 ticks *---------------------------------------------------------------------------*/__task void task1 (void) { OS_RESULT ret; while (1) { /* Pass control to other tasks for 3 OS ticks */ os_dly_wait(3); /* Wait 1 ticks for the free semaphore */ ret = os_sem_wait (semaphore1, 1);

if (ret != OS_R_TMO) { /* If there was no time-out the semaphore was aquired */ putStrS0 ("\n\rTask 1"); /* Return a token back to a semaphore */ os_sem_send (semaphore1); } }}

/*---------------------------------------------------------------------------- * Task 2 - Low Priority - looks for a free semaphore and uses the resource * whenever it is available *---------------------------------------------------------------------------*/__task void task2 (void) { while (1) { /* Wait indefinetly for a free semaphore */ os_sem_wait (semaphore1, 0xFFFF); /* OK, the serial interface is free now, use it. */ putStrS0 ("\n\rTask 2"); /* Return a token back to a semaphore. */ os_sem_send (semaphore1); }}/*---------------------------------------------------------------------------- * Task 3 'init' *---------------------------------------------------------------------------*/__task void init (void) { // setClock(); /* Initialize the UART */ InitSerial0 (9600); /* Initialize the Semaphore before the first use */ os_sem_init (semaphore1, 1); /* Create an instance of task1 with priority 10 */ //tsk1 = os_tsk_create (task1, 10); tsk1 = os_tsk_create (task1, 10); /* Create an instance of task2 with default priority 1 */ tsk2 = os_tsk_create (task2, 1); /* Delete the init task */ os_tsk_delete_self ();}

/*---------------------------------------------------------------------------- * Main: Initialize and start RTX Kernel *---------------------------------------------------------------------------*/

int main (void) { /* Initialize RTX and start init */ os_sys_init (init);}

/*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/

4. PROGRAM FOR ROUND ROBIN USING RTOS

#include <RTL.h> /* RTX kernel functions & defines */#include <LPC214X.H>/* id1, id2, id3, id4 will contain task identifications at run-time */OS_TID id1, id2,id3,id4,id5,id6,id7,id8;/* Function prototypes */__task void task1 (void);__task void task2 (void);__task void task3 (void);__task void task4 (void);__task void task5 (void);__task void task6 (void);__task void task7 (void);__task void task8 (void);/*---------------------------------------------------------------------------- * Task 1: RTX Kernel starts this task with os_sys_init (task1) *---------------------------------------------------------------------------*/__task void task1 (void) { /* Obtain own system task identification number */ unsigned int count; IO1DIR=0x40ff0000; IO1SET=1<<30; IO1CLR=0x00ff0000; id1 = os_tsk_self (); os_tsk_prio_self (2); /* Assign system identification numbers of task2, task3 and task4 */ id2 = os_tsk_create (task2, 2);/* Assign system identification number of task2 to id2 */id3 = os_tsk_create (task3, 2);/* Assign system identification number of task2 to id3 */id4 = os_tsk_create (task4, 2);/* Assign system identification number of task2 to id4 */id5 = os_tsk_create (task5, 2);/* Assign system identification number of task2 to id5 */id6 = os_tsk_create (task6, 2);/* Assign system identification number of task2 to id6 */id7 = os_tsk_create (task7, 2);/* Assign system identification number of task2 to id7 */id8 = os_tsk_create (task8, 2);/* Assign system identification number of task2 to id8 */

while (1){


}}

/*---------------------------------------------------------------------------- * Task 2: RTX Kernel starts this task with os_tsk_create (task2,2) *---------------------------------------------------------------------------*/__task void task2 (void) {unsigned int count; while (1)


}}/*---------------------------------------------------------------------------- * Task 3: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task3 (void) {unsigned int count;

while (1){

if(count%2==1) IO1SET=0x00040000;elseIO1CLR=0x00040000;

count++; }}/*---------------------------------------------------------------------------- * Task 4: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task4 (void) {unsigned int count;

while (1){


}}

/*---------------------------------------------------------------------------- * Task 5: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task5 (void) {unsigned int count;

while (1){



while (1){



while (1){


}}

/*---------------------------------------------------------------------------- * Task 8: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task8 (void) {unsigned int count;

while (1){


}}/*---------------------------------------------------------------------------- * Main: Initialize and start RTX Kernel *---------------------------------------------------------------------------*/int main (void) { os_sys_init (task1);}

/*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/

5. PROGRAM FOR PRIORITY INVERSION USING RTOS#include <RTL.h> /* RTX kernel functions & defines */#include <LPC214X.H>#include "serial0.h"extern void init_serial (void); /* Initialize Serial Interface */OS_TID tsk1, tsk2;OS_MUT mutex1;/*---------------------------------------------------------------------------- * Task 1 - High Priority *---------------------------------------------------------------------------*/__task void task1 (void) { OS_RESULT ret;

while (1) { putStrS0("\n\rTask 1"); os_dly_wait (100);

os_mut_wait (mutex1, 0xffff); os_mut_release (mutex1); } }/*---------------------------------------------------------------------------- * Task 2 - Low Priority *---------------------------------------------------------------------------*/__task void task2 (void) { while (1) { os_mut_wait (mutex1, 0xffff); /* Wait indefinetly for a free mutex */ putStrS0 ("\n\rTask 2") /* OK, the serial interface is free now, use it. */ getCharS0(); os_mut_release (mutex1); /* Release the Mutex */ }}

/*---------------------------------------------------------------------------- * Task 3 'init' *---------------------------------------------------------------------------*/

__task void init (void) { InitSerial0 (9600); /* Initialize the UART */ os_mut_init (mutex1); /* Initialize the mutex before the first use */

tsk1 = os_tsk_create (task1, 10); /* Create an instance of task1 with priority 10 */ tsk2 = os_tsk_create (task2, 1);/* Create an instance of task2 with default priority 1 */

os_tsk_delete_self (); /* Delete the init task */}

/*---------------------------------------------------------------------------- * Main: Initialize and start RTX Kernel *---------------------------------------------------------------------------*/int main (void) { os_sys_init (init); /* Initialize RTX and start init */}

/*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/

6. PROGRAM FOR MESSAGE QUEUE USING RTOS

#include <RTL.h> /* RTX kernel functions & defines */#include <LPC214X.H> /* LPC21xx definitions */#include "serial0.h"#include "lcd.h"OS_TID tsk1; /* assigned identification for task 1 */OS_TID tsk2; /* assigned identification for task 2 */

unsigned char MSG[16];

os_mbx_declare (MsgBox,16); /* Declare an RTX mailbox */_declare_box (mpool,sizeof(MSG),16);/* Dynamic memory pool */__task void send_task (void);__task void rec_task (void);/*---------------------------------------------------------------------------- * Task 1: RTX Kernel starts this task with os_sys_init (send_task) *---------------------------------------------------------------------------*/__task void send_task (void) {

tsk1 = os_tsk_self (); /* get own task identification number */

tsk2 = os_tsk_create (rec_task, 0); /* start task 2 */ os_mbx_init (MsgBox, sizeof(MsgBox));/* initialize the mailbox */ os_dly_wait (5); /* Startup delay for MCB21xx */while(1){ putStrS0("\n\rENTER the MSG: "); getStrS0(MSG); os_mbx_send (MsgBox, MSG, 0xffff); /* Send the message to the mailbox */ putStrS0("\n\rSending MSG...."); os_dly_wait (100); } // os_tsk_delete_self (); /* We are done here, delete this task */}

/*---------------------------------------------------------------------------- * Task 2: RTX Kernel starts this task with os_tsk_create (rec_task, 0) *---------------------------------------------------------------------------*/__task void rec_task (void) { unsigned char *rptr;

while(1) { os_mbx_wait (MsgBox,(void **)&rptr, 0xffff); /* wait for the message */ putStrL("Receaved MSG: ",0x01);

putStrL(rptr,0xC0);_free_box (mpool, rptr); /* free memory allocated for message */}

}

/*----------------------------------------------------------------------------Main: Initialize and start RTX Kernel*---------------------------------------------------------------------------*/int main (void) { /* program execution starts here */

InitSerial0 (9600); /* initialize the serial interface */lcdInit();putCharS0(0x0C);_init_box (mpool, sizeof(mpool), /* initialize the 'mpool' memory for */

sizeof(MSG)); /* the membox dynamic allocation */os_sys_init (send_task); /* initialize and start task 1 */

}

/*----------------------------------------------------------------------------end of file

*---------------------------------------------------------------------------*/

7. PROGRAM FOR PREEMPTIVE SCHEDULING USING RTOS

#include <RTL.h> /* RTX kernel functions & defines */#include <LPC214X.H>/* id1, id2 will contain task identifications at run-time */OS_TID id1, id2,id3,id4,id5,id6,id7,id8;/* Forward reference */__task void task1 (void);__task void task2 (void);__task void task3 (void);__task void task4 (void);__task void task5 (void);__task void task6 (void);__task void task7 (void);__task void task8 (void);/*---------------------------------------------------------------------------- * Task 1: RTX Kernel starts this task with os_sys_init (task1) *---------------------------------------------------------------------------*/__task void task1 (void) {

unsigned int count=0;IO1DIR=0x40ff0000;IO1SET=1<<30;IO1CLR=0x00ff0000;

id1 = os_tsk_self (); /* Obtain own system task identification number */ os_tsk_prio_self (1);id2 = os_tsk_create (task2, 2);/* Assign system identification number of task2 to id2 */id3 = os_tsk_create (task3, 3);/* Assign system identification number of task2 to id3 */id4 = os_tsk_create (task4, 4);/* Assign system identification number of task2 to id4 */id5 = os_tsk_create (task5, 5);/* Assign system identification number of task2 to id5 */id6 = os_tsk_create (task6, 6);/* Assign system identification number of task2 to id6 */id7 = os_tsk_create (task7, 7);/* Assign system identification number of task2 to id7 */id8 = os_tsk_create (task8, 8);/* Assign system identification number of task2 to id8 */ while (1)


os_dly_wait (100); /* Wait now for 50 ms */ }}

/*---------------------------------------------------------------------------- * Task 2: RTX Kernel starts this task with os_tsk_create (task2, 1) *---------------------------------------------------------------------------*/__task void task2 (void) {unsigned int count; while (1)



while (1){



while (1){

if(count%2==1) IO1SET=0x00080000;else

IO1CLR=0x00080000;count++;


while (1){



while (1){



while (1){

if(count%2==1) IO1SET=0x00400000;

elseIO1CLR=0x00400000;count++;


while (1){



/*---------------------------------------------------------------------------- * Main: Initialize and start RTX Kernel *---------------------------------------------------------------------------*/int main (void) { os_sys_init (task1);}

/*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/

Viva question and answers

The Operating SystemDevelopers need special tools (like the compilers and command lines found in GNU) to write applications that can talk to the kernel. They also need tools and applications to make it easy for outside applications to access the kernel after the application is written and installed. This collective set of tools, combined with a kernel, is known as the operating system. It is generally the lowest layer of the computer's software that is accessible by the average user. General users get to the operating system when they access the command line. Linux provides powerful tools with which to write their applications: developer environments, editors, and compilers are designed to take a developer's code and convert it to something that can access the kernel and get tasks done. Like the kernel, the Linux operating system is also modular. Developers can pick and choose the operating tools to provide users and developers with a new flavor of Linux designed to meet specific tasks.

How to create a child process in linux?

Prototype of the function used to create a child process is pid_t fork(void);Fork is the system call that is used to create a child process. It takes no arguments and returns a value of type pid_t. If the function succeeds it returns the pid of the child process created to its parent and child receives a zero value indicating its successful creation. On failure, a -1 will be returned in the parent's context, no child process will be created, and errno will be set The child process normally performs all its operations in its parents context but each process independently of one another and also inherits some of the important attributes from it such as UID, current directory, root directory and so on.

Differentiate between mutexes vs semaphores

-Semaphores is a synchronisation tool to overcome the critical section problem.- A semaphore S is basically an integer variable that apart from initialisation is accesses only through atomic operations such as wait() and signal().- Semaphore object basically acts as a counter to monitor the number of threads accessing a resource.- Mutex is also a tool that is used to provide deadlock free mutual exclusion.It protects access to every critical data item.if the data is locked and is in use,it either waits for the thread to finish or awakened to release the lock from its inactive state.

What are the commonly found errors in Embedded Systems?

- Damage of memory devices due to transient current and static discharges.- Malfunctioning of address lines due to a short in the circuit- Malfunctioning of Data lines.- Some memory locations being inaccessible in storage due to garbage or errors.- Improper insertion of Memory devices into the memory slots- Faulty control signals.

What is an embedded system?An embedded system is a special purpose computer system which is completely encapsulated by device it control. It is a programmed hardware device in which the hardware chip is programmed with specific function. It is a combination of hardware and software.

What are the characteristics of embedded system?

The Characteristics of the embedded systems are as follows-

1. Sophisticated functionality

3. Low manufacturing cost

4. Low power consumption

5. User friendly

6. Small size

What are the types of embedded system?

They are of 4 types

1. General computing

2. Control System

3. Digital Signal Processing

4. Communication and network

What is digital signal controller ?

DSC is 16 bit RISC machine that combines control advantages of micro-controller and digital signal

processing to produce tightly coupled single chip-single instruction stream solution for embedded system

design.

What are the components of embedded system?

Microcontroller, microprocessor, DSC, DSP, busses, system clock, Read only Memory(ROM), RAM, Real

time clock these are the components of embedded system.

Why we use embedded systems?

Embedded systems avoid lots of electronic components and they have rich built in functionality. They reduces

the cost and maintenance cost and the probability of failure of embedded system is less so embedded system are

in very much use now a days.

What are the languages used in embedded system?

Assembly language and C are basically used for embedded system. Java and ADA are also preferred.

How does combination of functions reduce memory requirement in embedded system?

. By using functions the amount of code that has to be dealt with is reduced thus redundancy is eliminated for

everything common in function.

What is the significance of watchdog timer in ES?

It is a timing device which is set to predefined time interval and some task is to be performed at that time. It is

used to reset original state when an inappropriate event take place.It is usually operated by counter device.

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