8/3/2014 Embedded Systems and Linux Interview Questions: ARM Interview Questions

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Embedded Systems andLinux Interview Questions

Wednesday, January 16, 2013

ARM Interview Questions

What are the different modes in ARM?

There are 7 modes in ARM.

User usr

Fast interrupt fiq

Interrupt irq

Supervisor svc

Abort abt

System sys

Undefined und

The following two modes are newly added:

Monitor (mon) - With Security Extensions (Secure only)

Hyp (hyp) - With Virtualization Extensions (Non-secure only)

Explain about the different modes in ARM.

User mode

The only non-privileged mode.

System mode

The only privileged mode that is not entered by an exception. It can only be entered by

executing an instruction that explicitly writes to the mode bits of the CPSR.

Supervisor (svc) mode

A privileged mode entered whenever the CPU is reset or when a SWI instruction is executed.

Abort mode

A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.

Undefined mode

A privileged mode that is entered whenever an undefined instruction exception occurs.

Interrupt mode

A privileged mode that is entered whenever the processor accepts an IRQ interrupt.

Fast Interrupt mode

A privileged mode that is entered whenever the processor accepts an FIQ interrupt.

Hyp mode

A hypervisor mode introduced in armv-7a for cortex-A15 processor for providing hardware

virtualization support.

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Reference: http://en.wikipedia.org/wiki/ARM_architecture

Explain about the bits in CPSR register.

The individual bits represent the following:

N – Negative result from ALU.

Z – Zero result from ALU.

C – ALU operation Carry out.

V – ALU operation oVerflowed.

Q – cumulative saturation (also described as sticky).

J – indicates whether the processor is in Jazelle state.

GE[3:0] – used by some SIMD instructions.

IT [7:2] – If-Then conditional execution of Thumb-2 instruction groups.

E bit controls load/store endianness.

A bit disables asynchronous aborts.

I bit disables IRQ.

F bit disables FIQ.

T bit – indicates whether the processor is in Thumb state.

M[4:0] – specifies the processor mode

Reference: Cortex-A Series Programmer’s Guide

What are the differences between fiq and irq?

How are the arguements passed to sub-routines and how the return value is sent to caller?

Registers R0 to R3 are used to pass arguments to subroutines, and R0 is used to pass a result back

to the callers. A subroutine that needs more than 4 inputs uses the stack for the additional inputs.

Which ARM instruction is used to enter kernel mode from user mode in Linux?

SVC (formerly SWI)

How are the arguments and system call number passed while executing SVC instruction (for enter

kernel mode from user mode in Linux)?

What are the registers that are pushed onto stack before executing a subroutine and who will do that?

Sub-routine will do that. At the beginning of the sub-routine, the registers that are going to be modified

in the sub-routine code will be pushed on to stack and at the end of the subroutine, the registers that

were pushed on to the stack will be popped out.

e.g.

fillmem

STMFD sp!, {r0-r2,r4,lr}; save registers

<sub-routine code>

LDMFD sp!, {r0-r2,r4,pc}; restore registers

Also note that, the ARM subroutine call instruction (BL) copies the return address into r14 before

changing the program counter, so the subroutine return instruction moves r14 to pc (MOV pc,lr).

What are the different instructions provided by ARM which are used for performing atomic operations?

What are memory barriers?

ARM InterviewQuestions

8/3/2014 Embedded Systems and Linux Interview Questions: ARM Interview Questions

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Posted by Yogesh at 1:56 AM

What are the different memory barrier instructions provided by ARM?

What is the difference between ARM and Thumb mode?

How do you determine whether you are in ARM or Thumb mode?

What is the difference between Thumb and Thumb2?

What is the difference between dsb, isb and dmb instructions?

ARM Interview Questions:

http://linuxinterviewpreperation.blogspot.in/2013/01/arm-interview-questions.html

C Programming Interview Questions:

http://linuxinterviewpreperation.blogspot.in/2013/01/c-programming-interview-questions.html

Linux Device Driver Interview Questions:

http://linuxinterviewpreperation.blogspot.in/2013/01/linux-kernel-and-device-drivers.html

Microprocessor and Embedded Hardware Interview Questions:

http://linuxinterviewpreperation.blogspot.in/2013/02/microprocessor-and-embedded-hardware.html

Operating System Interview Questions:

http://linuxinterviewpreperation.blogspot.in/2013/02/operating-system-interview-questions.html

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5 comments:

VIJAY KULKARNI October 17, 2013 at 2:13 AM

What are the different instructions provided by ARM which are used for performing atomic

operations?

Ans :: The LDREX and STREX instructions split the operation of atomically updating memory into

two separate steps. Together, they provide atomic updates in conjunction with exclusive monitors

that track exclusive memory accesses, see Exclusive monitors. Load-Exclusive and Store-Exclusive

must only access memory regions marked as Normal.

LDREX

The LDREX instruction loads a word from memory, initializing the state of the exclusive monitor(s)

to track the synchronization operation. For example, LDREX R1, [R0] performs a Load-Exclusive

from the address in R0, places the value into R1 and updates the exclusive monitor(s).

STREX

The STREX instruction performs a conditional store of a word to memory. If the exclusive monitor(s)

permit the store, the operation updates the memory location and returns the value 0 in the

destination register, indicating that the operation succeeded. If the exclusive monitor(s) do not

permit the store, the operation does not update the memory location and returns the value 1 in the

destination register. This makes it possible to implement conditional execution paths based on the

success or failure of the memory operation. For example, STREX R2, R1, [R0] performs a Store-

Exclusive operation to the address in R0, conditionally storing the value from R1 and indicating

success or failure in R2.

Alternative exclusive access sizes

The ARMv6K architecture introduced byte, halfword and doubleword variants of LDREX and STREX:

LDREXB and STREXB

LDREXH and STREXH

LDREXD and STREXD.

The ARMv7 architecture added these to the Thumb instruction set in the A and R profiles. ARMv7-M

supports the byte and halfword but not the doubleword variants. ARMv6-M does not support

exclusive accesses.

The architecture requires that each Load-Exclusive instruction must be used only with the

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Replies

Reply

corresponding Store-Exclusive instruction, for example LDREXB must only be used with STREXB.

Reply

Nikhil Bansal January 31, 2014 at 6:59 AM

How are the arguments and system call number passed while executing SVC instruction (for enter

kernel mode from user mode in Linux)?

Ans. :

Simply entering kernel-space with the help of a system call alone is not sufficient because there are

multiple system calls, all of which enter the kernel in the same manner. Thus, the system call

number must be passed into the kernel. On x86, the syscall number is fed to the kernel via the eax

register. Before causing the trap into the kernel, user-space sticks in eax the number

corresponding to the desired system call. The system call handler then reads the value from eax.

Other architectures do something similar.

The system_call() function checks the validity of the given system call number by comparing it to

NR_syscalls. If it is larger than or equal to NR_syscalls, the function returns -ENOSYS. Otherwise,

the specified system call is invoked:

call *sys_call_table(,%eax,4)

In addition to the system call number, most syscalls require that one or more parameters be

passed to them. Somehow, user-space must relay the parameters to the kernel during the trap.

The easiest way to do this is via the same means that the syscall number is passed: The

parameters are stored in registers. On x86, the registers ebx, ecx, edx, esi, and edi contain, in order,

the first five arguments. In the unlikely case of six or more arguments, a single register is used to

hold a pointer to user-space where all the parameters are stored.

The return value is sent to user-space also via register. On x86, it is written into the eax register.

Reply

Nikhil Bansal January 31, 2014 at 7:01 AM

Refer: http://www.makelinux.com/books/lkd2/ch05lev1sec3

Nikhil Bansal January 31, 2014 at 7:58 AM

What are memory barriers?

Ans.:

Independent memory operations are effectively performed

in random order, but this can be a problem for CPU-CPU interaction and for I/O.

What is required is some way of intervening to instruct the compiler and the

CPU to restrict the order.

Memory barriers are such interventions. They impose a perceived partial

ordering over the memory operations on either side of the barrier.

Such enforcement is important because the CPUs and other devices in a system

can use a variety of tricks to improve performance, including reordering,

deferral and combination of memory operations; speculative loads; speculative

branch prediction and various types of caching. Memory barriers are used to

override or suppress these tricks, allowing the code to sanely control the

interaction of multiple CPUs and/or devices.

Refer: https://www.kernel.org/doc/Documentation/memory-barriers.txt

Reply

RR Satish June 4, 2014 at 5:28 AM

It's nice posting to embedded students to attend the interview .

Reply

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