embeddedsystems (1)

Embedded System Concepts

Contents

Embedded System Overview

Embedded System Building Blocks

Hardware

Microprocessor / Microcontroller

Microprocessor / Microcontroller Peripherals

Operating Modes

Some terminology

Software

Software architecture

Development life cycle

Real time operating system

Some terminology

Development Environment

Embedded System Applications

Question and Answers


What is an embedded system ?

What is a real time embedded system ?

Why embedded system is required ?

What are the building blocks of embedded system ?

Where embedded system are used ?


An embedded system is a software system that is completely

encapsulated by hardware that it controls, i.e., an embedded system is a

combination of computer hardware and software

A real time embedded system is one whose logical correctness is based

on both the correctness of the outputs and also timeliness, i.e., response-

time constraints

A system has set of one or more inputs and one or more outputs

The time between the presentation of a set of inputs to a software system

and the appearance of the all the associated outputs is called the response

time of the software system


Real time systems do not have to be FAST Systems

Performance is crucial parameter in real time systems

Soft Real Time Systems: Systems in which performance is degraded but

not destroyed by failure to meet response-time constraints.

Hard Real Time Systems: Systems where failure to meet response-time

constraints leads to system failure.

Time-loading: Time-loading or utilization factor is measure of the

percentage of USEFUL processing that system is doing.


Hardware

Embedded System

Embedded system is a Computer system.

Embedded System is designed for a very specific task to

control a particular system.

Embedded System is a programmable machine which

responds in a well-defined manner to a specific set of

instructions (program) provided by a human programmer.

Embedded System program instructs the computer to

perform long sequences of very simple actions to

accomplish useful tasks as intended by the programmer.

Embedded System programs are stored in memory and are executed by a central processing

unit.

Embedded System interact with the environment using input/output peripherals.

Embedded System are developed using microprocessor / microcontrollers / DSPs

Typically, an embedded system is housed on a single microprocessor board with the programs

stored in ROM

Microprocessor vs. Microcontroller

Microprocessor

Contains the central processing unit.

The input/output system and memory are accessed using an external bus.

Commonly used in general purpose computers.

Easier to expand and upgrade

NOT a single chip computer

Central

Process Unit

Input / Output

System Memory

Inputs

Outputs

Microprocessor

Microprocessor vs. Microcontroller

Microcontroller

The central processing unit, input/output system, memory, timer, serial ports,

interrupt control unit, PWM, ATD etc are contained in a highly integrated single

chip.

Commonly used in specific purpose computers for real-time applications.

Systems are constrained by Microcontroller limitations.

Generally referred to as Single Chip Computer

Central

Process Unit

Input / Output

System Memory

Inputs

Outputs

Microcontroller

Motorola HC12 Microcontroller Block Diagram

Memory

Volatile Memory – requires power to maintain the stored information

RAM

Non-volatile Memory – can retain the stored information even when not

powered

ROM

EEPROM

UV ROM

FLASH

NVRAM

FRAM

Memory - EEPROM

Electrically Erasable Programmable Read Only Memory

Many Microcontrollers have limited amounts of EEPROM on the chip

EEPROM seems more suited (because of its economics) to small amounts

of memory that hold a limited number of parameters that may have to be

changed from time to time

This type of memory is relatively slow, and the number of erase/write

cycles allowed in its lifetime is limited.Typically ~10,000 Cycles.

EEPROM can be selectively erased and flashed byte wise

EEPROM is a non-volatile memory

Memory - FLASH

Provides large amounts of non-volatile program memory

Faster than EEPROM

Permits more erase/write cycles than EEPROM

Typical write cycles 100/20,000 ( Embedded, Motorola/Zilog)

Memory can only be erased and flashed block wise

Flash comes with Software protection of certain blocks (e.g., Tuning block)

Memory - RAM

Random Access Memory

Read - Write memory, i.e., variable data are stored at each memory location

can be read or written

RAM is a volatile memory

Many Microcontrollers have limited amounts of RAM on the chip

Memory - NVRAM

Battery backed-up static RAM

Useful when large non-volatile program and DATA spaces are required.

A major advantage of static RAM is that it is much faster than other types of

non-volatile memory so it is well suited for high performance application.

There also are no limits on the number of times that static RAM may be

written to so it is perfect suited for applications that keep and manipulate

large amounts of data locally.

Its primary use in automotive applications is to retain dynamic non-volatile

data.

Memory Validation

ROM

Checksum

Cyclic Redundancy Code (CRC)

RAM

Bit patterns like 0x55 and 0xAA can be written and read

Serial Communication - UART

Universal Asynchronous Receiver Transmitter

A serial port adapter for asynchronous serial communications.

Each Data character has a bit which identifies with one start and stop bit. A

parity bit can also be added to verify the integrity of data

Since each character is individually identified, characters can be sent at any

time

Minimum of 10 bits is required for an 8 bit character

Two port pins for SCI provide the external interface for the transmitted data

(TXD) and the received data (RXD)

Serial Communication - SCI

SCI (Serial Communications Interface) is an asynchronous serial

communication bus

SCI is an enhanced UART

SCI allows asynchronous serial communications with peripheral devices

and other CPUs

Two port pins for SCI provide the external interface for the transmitted data

(TXD) and the received data (RXD)

RXD

SCI Port

TXD

SCI Block Diagram

Serial Communication - SCI

SCI Data Formats

A data frame consists of a start bit, a character of eight or nine data bits and a stop bit

The high state before transmission or reception of a message indicates that bus is idle

A start bit (logic zero), transmitted or received, indicates the start of each character.

Data that is transmitted or received least significant bit (LSB) first. SCI can be configured

for eight or nine data bits. Ninth data bit acts as parity bit, odd or even. If enabled, parity is

generated in hardware for transmitted and received data. Receiver parity errors are

flagged in hardware.

A stop bit (logic one), used to indicate the end of a frame.

Data is transmitted in NRZ format

The baud rate registers are used to select the required baud rates

SPI (Serial Peripheral Interface) is a synchronous serial communication bus

The SPI bus specifies four logic signals.

SCLK — Serial Clock (output from master)

MOSI/SIMO — Master Output, Slave Input (output from master)

MISO/SOMI — Master Input, Slave Output (output from slave)

SS — Slave Select (Active low; output from master)

Serial Communication - SPI

SPI Block Diagram

Serial Communication - SPI

Master/Slave Transfer Block Diagram

In the SPI system, the 8-bit data register in the master and the 8-bit data register in the slave are

linked to form a distributed 16-bit register.

When a data transfer operation is performed, 16-bit register is serially shifted eight bit positions by

the SCLK clock from the master so the data is effectively exchanged between the master and the

slave.

Data written to the register of the master becomes the output data for the slave and data read from

the register of the master after a transfer operation is the input data from the slave.

The baud rate registers are used to select the required baud rates

SPI is used to talk to a variety of peripherals, such as temperature sensors, pressure sensors,

Flash, EEPROM etc.

Serial Communication – I2C

Inter-Integrated Circuit bus (I2C bus) is a simple 2 wire, bidirectional serial bus

developed by Philips.

Developed for 8 bit applications

In addition to Microcontrollers, several peripherals also exist that support the I2C

bus.

The I2C bus is a two line, multi-master, multi-slave network interface with collision

detection.

Up to 128 devices can exist on the network and they can be spread out over 10

meters.

The two lines of the network consist of the serial data line and the serial clock

line.

Each node on the network has a unique address which accompanies any

message passed between nodes.

Widely used in consumer electronics, automotive, aerospace and industrial

applications.


START Signal : When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA

lines are at logical high), a master may initiate communication by sending a START signal. START

Signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of

data) and wakes up all slaves.


Slave Address Transmission : A unique slave address is transmitted by the master. This is a seven-bit

calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer.

1 = Read transfer, the slave transmits data to the master.

0 = Write transfer, the master transmits data to the slave.

Only the slave with a calling address that matches the one transmitted by the master will respond by

sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock

Data Transfer : Once successful slave is identified, the data transfer can proceed byte-by-byte in a

direction specified by the R/W bit sent by the calling master.

STOP Signal : The master can terminate the communication by generating a STOP signal to free the

bus

Repeated START Signal : A repeated START signal is a START signal generated without first

generating a STOP signal to terminate the communication. This is used by the master to communicate

with another slave or with the same slave in different mode (transmit / receive mode) without releasing

the bus.

Bus Arbitration: I2C is a multi-master bus that allows more than one master to be connected on it. If two

or more masters try to control the bus at the same time, bus conflict is resolved by bus arbitration.

Serial Communication - CAN

Controller Area Network (CAN)

CAN is a multiplexed wiring scheme that was developed Bosch for automobiles.

Bit-oriented Serial Communications Protocol

Variable bit rate: 5 Kbit/s up to 1 Mbit/s

Peer-to-Peer: any node may transmit at any frame

Multi-cast without routing: all nodes receive all messages

Non-destructive bit-wise arbitration

Prioritization of messages via the identifier

System wide data consistency

Fault confinement

Automatic retransmission of corrupted messages

High level of error detection (< 10-10)


Message Transfer

Information is sent on the bus in fixed format message frames.

Any node may start to transmit when the bus is free (Bus Idle).

If two or more nodes start transmitting in the same frame, bus access conflict is resolved by bit-wise

arbitration.

The highest priority message wins bus access.

Transmitting nodes which loose arbitration become receivers.

No data or time is wasted, someone always wins.

Nodes which loose arbitration will automatically re-transmit.

Arbitration Field (identifier) determines the message priority.

Identifier - intended to label message contents (no physical node addresses).

All nodes check the consistency of messages received and will flag an inconsistent message to the

entire network.

All receiving nodes will acknowledge a valid message.

A message is received correctly by all nodes or no nodes.

All nodes apply Message Filtering to decide whether to accept a message.

Any number of nodes can simultaneously receive and accept a message (Multicast transmission)


Message Types

Data Frame : Carries data from a transmitter to the receivers. Used to transmit

up to 8 bytes of data.

Remote Transmission Request (RTR) Frame : Transmitted by a bus used to

request a Data Frame with the same Identifier.

Error Frame : Transmitted by any node on detecting the bus error (independent

of CPU)

Overload Frame : Used to provide an extra delay between the preceding and

the succeeding Data Frames or Remote Frames.

Data Frames and Remote Frames are separated from preceding frames by an Inter-

frame space

Analog to Digital Conversion

Converts an external analog signal (typically a voltage) into digital format

ATD converter terminology:

Start of conversion

End of conversion

Conversion Modes

One shot

On-demand

Continuous

Conversion channel

Single Channel

Multi Channel

Sampling rate

Resolution

A2D Conversion Process

Pulse Width Modulator

PWM generates pulses of variable

pulse width

PWM allows selection of duty cycle

and signal period time

PWM counter increments

periodically to the clock and is reset

at the end of every period of the

PWM

PWM duty and period registers are

programmable

Duty rates are programmable from

0 percent to 100 percent

PWM output changes state from

high to low or low to high, when the

PWM counter value is greater than

or equal programmed duty / period

register value

PWM outputs can be used control

an electric motor, blinking of LEDs

etc

PWM Signal Description

PWM Duty

Register

PWM Period Register

PWM

Counter

S Q

_

R Q

PWM Output Signal

CLOCK

RESET

PWM Block Diagram

Timers

Pulse Accumulator is an event counter. Each pulse increments the pulse accumulator register,

recording the number of times this event has occurred. Allows one-shot or continuous timer

notifications.

Input Capture can precisely measure external frequencies and schedule the internal functionality

based on the number of external events. Time intervals or events are captured by copying the

value from a free running counter into a register when an external event occurs. It provides

Period / Low / High time measurement

Edge detection and notification

Edge counting

Edge time-stamping

Wake-up interrupts

Output Comparators operate much like standard comparators however the input and output

signals are available on the Microcontroller bus. It compares the data on the bus with the data in

comparator register.

A full access for the counter registers or the input capture / output compare registers should take

place in one clock cycle. Accessing high byte and low byte separately for all of these registers

may not yield the same result as accessing them in one word.

General Purpose I/O

Ports which can be used for general purpose digital input / output

Each GPIO has a Data Direction Register (DDR), which defines direction of data, i.e.,

input / output

Most of the I/O ports are multiplexed with peripheral I/O. When a peripheral is not

used, its I/O port can be used for GPIO

Watchdog Timer

Watchdog Timer (WDT) / COP (Computer Operating Properly) Reset

The watchdog timer provides a fail-safe mechanism that intervenes if a system stops functioning.

The problem could be a program that goes into an endless loop.

A hardware problem that prevents the program from operating correctly.

Watchdog timer is a hardware timer that is periodically reset by software at a fixed regular interval.

When software crashes or hangs, the program fails to reset the watchdog timer at some

predetermined interval. The watchdog timer will expire and a hardware reset will be initiated.

Though the bug may still exist, the system has a way to recover. This is especially useful for

unattended systems.

Watchdog timer shall be enabled in all applications.

Block diagram of Watchdog Timer

Interrupts

An interrupt is a hardware signal that initiates an event

Event could be Synchronous or Asynchronous

Synchronous events occur at predictable times. Ex: Timer interrupt

Asynchronous events occur at unpredictable times. Ex: Rx / Tx interrupt

On interrupt, the controller suspends its current operation, identifies the interrupting

peripheral, then jumps (vectors) to the appropriate Interrupt Service Routine (ISR)

Interrupts are generated from hardware outside the CPU. Peripherals interrupt the

controller when the data is ready.

The controller can carry out its normal function doing other work and only respond to

interrupts by peripherals when there is data available.

Interrupts can be edge (rising or falling) triggered or level triggered.

Both systems (edge / level triggered) have advantages and disadvantages.

Edge triggered interrupt is not time sensitive, but is susceptible to glitches.

Level triggered interrupt must be held high (or low) for a specific duration (it is less

susceptible to glitches).

Interrupts

Types of Interrupts

Maskable interrupts (IRQs)

Peripheral (SPI, SCI, Timer, CAN, ATD etc) interrupts

Non-maskable interrupt (NMI)

Hardware reset, Watchdog reset etc

When an interrupt shared by multiple sources, interrupt flag should be cleared by software,

otherwise it is cleared by hardware

A higher priority interrupt can not be interrupted by a lower priority interrupt but a lower priority

interrupt can be interrupted by a higher priority interrupt

Priority of the interrupts can be set by priority register, otherwise default priority will be taken

Systems in which interrupts occurs at fixed at rates (periodically) are called fixed-rate systems

Systems in which interrupts occur aperiodically are called sporadic systems

Systems in which interrupts occurs periodically and aperiodically are called hybrid systems

Context switching is the process of saving and restoring the sufficient information for a real-time

task so that it can be resumed after being interrupted

Interrupt latency is the delay between when an interrupt occurs and when the CPU begins

reacting to it.

Exceptions

Exceptions are special conditions (internal events) generated from the CPU during

program execution that preempts normal processing

Exceptions change machine state and redirect program flow to one of several

possible locations, depending on the exception.

Exceptions are SW interrupts which are executed whenever there is an unwanted

instruction executed in the code

When exceptions occur the SW jumps to the appropriate corresponding exception

vector service routine.

Exceptions are sometimes called traps

Some of the exceptions are divide by zero errors, overflow conditions, invalid opcode,

floating point operations errors.

Polling

Polling is a software technique whereby the controller continually checks the

status of flag to see if a peripheral needs servicing.

The peripheral sets a flag when it has data ready for transferring to the

controller. The controller then notices the flag on its next poll.

Several peripherals (flags) can be polled successively

Depending on the flags set by the peripheral, controller jumps to the

different software routines

Software routine is responsible for clearing the flag

RISC and CISC

RISC (Reduced Instruction Set Computers)

The trend for microprocessor design is for Reduced Instruction Set Computers .

By implementing fewer instructions, the chip designer is able to dedicate some of

the precious silicon real-estate for performance enhancing features.

Separate buses for instructions and data allows simultaneous access of program

and data, with overlapping of some operations for increased processing

performance

Instruction pipelining increases execution speed

Instruction set aids programming simplicity; by allowing each instruction to

operate on any register or use any addressing mode.

Instructions have no special combinations, exceptions, restrictions, or side

effects

RISC normally consists of few instructions

All or several instructions executed in one clock cycle.

RISC and CISC

CISC (Complex Instruction Set Computer)

Powerful and very specialized for specific control tasks.

It is quite common for all the instructions to behave quite differently.

Some might only operate on certain address spaces or registers, and others

might only recognize certain addressing modes.

Advantage is that many of the instructions are macro-like, allowing the

programmer to use one instruction in place of many simpler instructions.

CISC normally consists of many instructions

Little Endian and Big Endian

Little Endian

Least significant byte (LSB) of a multi-byte value is stored at

the lowest memory address

Intel processors generally use little endian format

Big Endian

Most significant byte (MSB) of a multi-byte value is stored at

the highest memory address

Motorola processors generally use big endian format

Bi-endian

Bi-endian hardware provides capability to compute data in

either of the formats

Either of the format is selectable by software

Bi-endian refers to how a processor treats data accesses.

Instruction accesses on a given processor may still assume

a fixed endianess

Some architectures like ARM, PowerPC provides bi-endian

feature

Harvard and Von-Neumann Architecture

Von-Neumann Architecture

Program instructions and data are stored in a shared memory with one data bus and one

address bus between processor and memory

CPU can be either reading an instruction or reading/writing data from/to the memory

Instructions and data have to be fetched in sequential order limiting the operation bandwidth

CPU first fetches an instruction and then fetches the data from the memory

Two separate fetches slow the controllers operation

CPU

Program

and

Data

Memory

Data bus

Address Bus

Von-Neumann Architecture

Harvard and Von-Neumann Architecture

Harvard Architecture

Program instructions and data are stored in a separate program memory and data memory

with separate data bus and address bus between processor and program / data memory

CPU can read both an instruction and perform a data memory access at the same time

Separate buses for instructions and data allows simultaneous access of program and data,

and overlapping of some operations for increased processing performance

CPUProgram

Memory

Data bus

Address Bus

Harvard Architecture

Data

Memory

Data bus

Address Bus

Operating Modes

Normal operating mode

When the microcontroller is Powered ON, it enters the Normal operating mode

and it can be forced to different modes based on the application.

In Normal operating mode, the processor is capable of performing all its

functionality

The device can be placed into Sleep / Halt mode by software control

Idle / Sleep Mode

All activities are stopped except on-board oscillator circuitry, clock monitor and

idle timer (a free running timer)

Power consumption on the microcontroller in this mode is typically around 30%

of normal power consumption for the microprocessor

Idle mode is exited by a reset or some other stimulus such as timer interrupt,

serial port interrupt

Operating Modes

Halt mode

On-chip oscillator is stopped

With clock frozen, all activities are stopped (including timers)

The only way to wake up the microcontroller is by a hardware reset

The power requirements of the device are minimal and the applied voltage can

be sometimes decreased below operating voltage without altering the state

(RAM / Outputs) of the device

Both in Halt and Idle conditions the state of the microcontroller freezes, but RAM

is not cleared and any outputs are not changed

Cold and Warm Reset

Cold Reset

Restarting the system by turning off the power and then on

All the peripheral registers, variables are initialized

Also called as Hard reset

Example: Power On reset

Warm Reset

Restarting the system without removing the power

Only variables are initialized

Also called as Soft reset

Example: Watchdog reset

Pipelining

An instruction pipeline is a technique used in the design of computers increase their instruction

throughput i.e., the number of instructions that can be executed in a unit of time

Pipelining assumes that successive instructions in a program sequence will overlap in execution

Pipeline with four stages:

Fetch : Instruction is fetched from memory

Decode : Instruction is decoded

Execute : Instruction is executed

Write-back : Instruction results are written back to register or memory

The cycle time of the processor is reduced, thus increasing instruction bandwidth in most cases

ExceuteFetch Decode Write-back




4 staged pipelined execution of instruction


Software

Software Architecture

Hardware

Driver Software

Application programming

Interfaces (API)

Application Software

Software Architecture

Hardware

Target microprocessor or microcontroller platform where

software runs

Driver Software

Software for peripherals like SPI, SCI, CAN ATD, Timers,

PWM, EEPROM, FLASH etc.

Driver software includes,

Initialization of registers like interrupt registers, control

registers, baud rate registers etc.

Enabling and disabling of features provided by registers

Reading and writing of data and status registers

Application Programming Interfaces

Interfaces to application to access the features provided by

driver software for controlling hardware peripherals

Application Software

Software for algorithms, controlling application etc

Software Development Life Cycle

Customer

Requirements

Design Phase

Software Development

Life Cycle

Low Level Design

Integration Testing

System Testing

High Level Design

Unit Testing

Coding

Requirement Phase

SW Delivery

1. SRS Preparation

2. STP Preparation

3. Traceability

Customer Supplied

Documents

1. HLD Preparation

2. ITP Preparation

3. Traceability

SRS document

1. LLD Preparation

2. UTP Preparation

3. Traceability

1. SRS document

2. HLD document

Program code

development

1. SRS document

2. HLD document

3. LLD document

Unit Test Reports

1. UTP document

2. Source code

Integration Test

Reports

1. ITP document

2. Source code

System Test

Reports

1. STP document

2. Source code

Release notes

1. All documents

2. Source code

1. ATP Preparation

2. Traceability

Acceptance Testing

1. Acceptance Test Reports

2. Sign off

Validation Team

Development Team

Hardware and Software Initialization Process

Hardware and Software Initialization Process

Startup code

Small block of assembly code that prepares the way for the execution of

software written in high level language

Most cross-compilers for embedded systems provide an assembly language

file called startup.s, crto.s or something similar

Startup routine usually performs the following

Disable all interrupts

Copy all initialized data from ROM to RAM

Initialize the uninitialized data to zero

Initialize all peripheral registers

Enable Interrupts

Call main function

Addressing Modes

Direct addressing

Operand is specified by an address field in the instruction

Example: ADD A, 7FH

Indirect addressing

Instruction specifies the register which contains the address of the operand

Example: ADD A, @R0

Register addressing

Instruction specifies the register which contains the operand

Example: ADD A, R0

Immediate constant

Constant is specified in the instruction

Example: ADD A, # 100

Indexed addressing

Intended for accessing memory locations using look-up tables

Index register points to address of the memory location

Implied addressing

Operand are in CPU registers

Example: DAA

Addressing Modes

RTOS

Running

The CPU is assigned to the task, so that its

instructions can be executed

Only one task can be in this state at any point

in time

Ready

All functional prerequisites for a transition into

the running state exist, and the task only waits

for allocation of the processor

The scheduler decides which ready task is

executed next

Waiting

A task cannot continue execution because it is

waiting for at least one event

Task States

RTOS

Task is nothing but a piece of software performing particular functionality

RTOS is responsible for the activation, termination and scheduling of the

various system tasks

Full Preemptive scheduling - Task with lower priority can be interrupted

by higher priority. Synchronization is to be handled by the programmer

Non preemptive scheduling - Task can be interrupted by another one only

through schedule calls. No synchronization problem here.

Mixed preemptive scheduling - In this case, some tasks can be

interrupted by the other tasks and the rest not.

RTOS

Read conditionsAnd measuredvvalues ,Values which defineEvent A

Check if eventA hasoccurred

React if event AWenn das Has occurred

Analog for eventsB, C, ...

conditions

Hardware

Read conditionsAnd measuredvvalues ,Values which defineEvent A

Check if eventA hasoccurred

React if event AWenn das Has occurred

Analog for eventsB, C, ...

conditions

Hardware

Event Driven Cyclic Driven

HW- or SW-Mechanisms

Conditions

Event AEreignis B

Event B

Task A

React

...

End

Task B

React

...

End

TriggerTrigger

Hardware

HW- or SW-Mechanisms

Conditions

Event AEreignis B

Event B

Task A

React

...

End

Task B

React

...

End

TriggerTrigger

Hardware

RTOS

Cyclic Event Driven

Merits Easy to manage

Acivities in a cycle is predictable

No synchronisation problem

Processor time is effectively used

Faster response

Demerits Large amount of time is used in processing rarely changing data

Processor time is not effectively utilised

Not easy to manage

Acivities in a cycle is not predictable

Synchronisation problem

Cyclic driven concept is suitable for constantly varying events

Event driven concept is suitable for rare events


Development Environment

How do you BUILD the software that

you have written ????

Software Build Process

Embedded Software Build Process

Embedded software build process is the transformation performed by

software running on a general purpose computer (host computer)

Host and Target

Compiler, assembler, linker, locator are all pieces of software that runs on a

host computer

Embedded software that is built runs on the target platform

Host and Target

Machine Language, Compiler

Machine Language

Machine language is the representation of the

program that the microcontroller can understand

and execute

Consists of a series of bit patterns, which when

entered into the instruction register of the

microcontroller will result in specific actions by the

microcontroller

Machine language code is generally very difficult

for humans to understand

Compilers

Translates programs written in high level language

(some human readable language) into an

equivalent set of opcodes (machine-language

instructions) for a particular processor

Cross-compiler is a compiler which run on one

computer platform and generates code for another

Input to the cross-compiler is source code written

in high level language (C, C++ etc) and output of

the cross-compiler is object file

Assembler, Interpreter

Assembler

Assembly language compiler

Translates programs written in assembly language into an equivalent set of opcodes for a particular

processor

Performs a one-to-one translation of human readable mnemonics to the equivalent opcode

Input to the assembler is source code written in assembly language and output of the assembler is

object file

The resulting executable program is fast and compact

Interpreter

An interpreter is used for high level language that is closer to natural language.

It is slow because it translates each source code line every time it executes. With an interpreter,

the program is developed interactively. It is often useful for short quick development activities.

However, with rapid compilation available with modern languages, the advantage is less obvious.

Translates each line of a program into machine language as the statement is encountered. If a

statement is encountered multiple times (as occurs in a loop) the machine must convert it to

machine language each time.

Linker

Linker

A software development tool

accepts one or more object files as

input and outputs a relocatable

program

The linker is thus run after all of

the source files have been

compiled and assembled into

object files

Symbol table contains names and

location of variables and functions

referenced within the source file.

Part of this table is incomplete

because all the variables and

functions are not always defined in

the same file

While the linker is in the process of

merging the section contents, it

also lookout for unresolved

symbols

Locator

Locator

A software development tool that

assigns physical addresses to a

relocatable program

This is the last step in preparing

software for execution by an

embedded system

Output file is called an executable

In some cases, the locator's

functionality is built into the linker

How do you VERIFY the software

that you have written ????

Verification Methods

Verification of Software without using the test and debug tools

Peer Reviews

Offline

Walkthrough

Inspection

Verification of Software using the test and debug tools

Simulators

Debuggers

Emulators

Verification of Software WITHOUT

using the test and debug tools

Peer Review Process Flow

Peer Review

Offline

Process

Work Product

Review Type

Peer Review

Walkthrough

Process

Peer Review

Inspection

Process

Defect Definitions

Major - System not working

An implementation that does not meet the requirements (or any other input document)

Defects that may cause the system to hang, crash, produce incorrect / unexpected results or

behaviour, or corrupt user data with no known work-around

Minor - Minor function disabled / incorrect

Non conformance to standards; Defects that cause incorrect results or behaviour with known

work-around.

Large and/or important areas of the system is affected that would not cause operational

failure

Trivial

Defects that affect limited areas of functionality that can either be worked around or ignored

Peer Review Team

Author

Developer of the work product being reviewed

Moderator

Leads the review team and keep the team focused

Reader

Paraphrase the work product in the defect logging meeting to provide an

exact view of the work product

Reviewer

Reviews the work product - NOT the author

Recorder

Record errors as detected and classify errors

Offline Review Process

Walkthrough Review Process

Inspection Review Process

Verification of Software USING

test and debug tools

Debug Environment

Block diagram of debug environment

Simulators

Software Simulator

A debugging tool runs on the host computer and acts as target processor

A simulator can be used to test pieces of the embedded software before the

embedded hardware is available. Attempts to simulate interactions with complex

peripherals are often more complex or limited.

One can step through the code to monitor the status of program. Contents of

registers or variables can be altered to change the way the program runs.

Eliminates (or at least delays) the erase / burn / program EPROM cycle common

in microcontroller program development.

A simulator can't support real interrupts or devices, and usually runs much slower

than the real device

Hardware Prototypes / Simulators

Hardware simulators might be required when the software is ready before the

prototype hardware

Debuggers

Debugger

A debugger can be used to download, execute and debug embedded software over serial

port or network connection between the host and target.

In embedded systems, the debugger and the software being debugged are executing on two

different computer systems.

A debugger actually consists of two pieces of software.

Front-end runs on the host computer and provides the human interface to monitor /

update through GUI-based main window and several smaller windows for the source

code, register contents, and other relevant information about the executing program

Back-end that runs on the target processor and communicates with the front-end over a

communications link of some sort. The back-end provides for low-level control of the

target processor and is usually called the debug monitor.

Debug monitor is software that has been designed for use as a debugging tool. It usually

resides in ROM and communicates with debugger via serial port and provides set of debug

commands to view and modify memory locations or registers, create or remove breakpoints

etc

BDM, JTAG are some of the serial port interfaces

Emulators

In-Circuit Emulators (ICE)

An emulator is a special hardware that takes the place of (emulates) the

microprocessor itself on the target. It is itself an embedded system with its own

copy of target processor, RAM, ROM and its own embedded software

Debuggers are helpful for monitoring and controlling the state of embedded

software but only an ICE allows the to programmer to examine the sate of the

processor on which that program is running

ICE allows the software to be run and tested on the actual hardware on which it

is to run and like debugger, ICE also provides programmer to download, execute

and debug software with enhanced debugging features

Provides full control over target, while at the same time not requiring any

resources from the target

In-circuit emulators are powerful tool but expensive than debuggers

Oscilloscope, Logic Analyzer

Oscilloscope

Oscilloscopes can be used for monitor analog, digital signals, voltage on

particular pin

Logic Analyzer

Logic Analyzer can be used to capture data or events, to measure instruction

times, time sections of code

Embedded System Applications

Automotive

Aerospace

Medical Electronics

Consumer Electronics

Industrial electronics

So on…

If you are given a chance to develop an

EMBEDDED SYSTEM,

how do you design and develop ????

Real Time Embedded System Design

Real Time Embedded System Design Parameters

Selection of Hardware and Software and appropriate combination needed for a

cost-effective solution

Cost of microprocessor / microcontroller / other hardware

Cost of licensed software/s

Decision to take advantage of a commercial RTOS or design a special operating

system

Duration of project

Cost of development

Selection of appropriate software language for Software development

Maximizing the system fault tolerance and reliability through careful design and

rigorous testing

Selection of development and test environment

Cost of development and testing tools

?

ANY Questions ?