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Microelectronics & Emerging Technologies Microelectronics & Emerging Technologies Thermal LaboratoryThermal Laboratory

Therminic 2002

EMERGING THERMAL CHALLENGES IN ELECTRONICS

DRIVEN BY PERFORMANCE, RELIABILITY AND ENERGY

EFFICIENCY

Yogendra JoshiG. W. Woodruff School of Mechanical Engineering

Georgia Institute of TechnologyAtlanta, GA 30332

Sponsors: Defense Advanced Research Projects Agency, Semiconductor Research Corporation, Office of Naval Research


Therminic 2002

OutlineRoadmap trends and recent initiatives

ITRSNEMIDARPA-HERETIC

Thermal management solutions for high performance microprocessors

Two-phase thermosyphonsStacked microchannels

Thermal characterization for high reliability power electronics modulesEnergy efficient thermal management

Data center challenges


Therminic 2002

International Technology Roadmap For Semiconductors - 2001

Projections from 2001 (0.13 µm) to 2016 (0.022 µ m)1

Commodity products (< $300)

Handheld products (< $1,000)

Cost/Performance products (< $3000)

High Performance products (> $3000)

Automotive

n/a

2.4-3

130-288

14-27

61-158

(Micro-controllers, disk drives, displays)

(Mobile products, cellular telecommunications)

(Notebooks, desktops, PCs)

(High end work stations, servers, avionics)

(Under-the-hood sensors, passenger products)

W Junction Ambient mm2 MHz

Power2 TemperatureLimits (oC) Size Perf.Chip Features

2. Single chip packages

125 55

100 55

85 45

85 45

150 -40-125

57-90

57-90

170-307

310-310

60-150

415-10,000

1,700-29,000

1,700-29,000

60-234

415-10,000

Chip Features

1. Excluding memory


Therminic 2002

Microprocessor Power Density

PowerDensity,W/cm2

50

10

Device miniaturization has led to integration of cache contained on a multi-chip package level to one contained on the microprocessor die resulting inhigh CPU core power density - e.g. 60% of the 20 mm by 20 mm micro-processor die may contain the CPU core, the rest is made of cache

Jan 95 Jan 00

Microprocessor with integrated 2nd level cache

Data provided by Mr. C. Patel, Hewlett-Packard Laboratories, Palo Alto, CA, June 1999.


Therminic 2002

Pre-metal dielectric

Tungsten contact plug

Copper conductor

Dielectric

Etch stop layer

Dielectric diffusion barrier

Passivation

Silicon with transistors

Local (2)

Intermediate (up to 4)

Global(up to 5) Via

Representative cross-section of interconnect structure (based on ITRS 2001)

• Characterized by many interconnect levels (11 levels for 22 nm node)

• New materials being introduced at a significantly higher pace

• Interconnect nets distributing clock signals and power can dissipate up to 40-50% of the power on the chip (~ 120 W)

Overview of Multilevel Interconnects

Thermal Issues in Future Technology Nodes


Therminic 2002

NEMI Roadmap-Thermal Needs

Improved thermal interfaces, Thermal spreaders, Mechanically robust packages that minimize the thermal resistance path to air,Thermal integration with EMC shielding, Low cost, compact and reliable water cooling, Low cost, compact, reliable and efficient refrigeration, Low cost, compact, and reliable dielectric liquid cooling, High heat flux, efficient thermoelectric cooler, cooling Abatement of heat load, impact on installation, Advanced modeling tools

High Performance

Improved thermal interfaces, Thermal spreaders, Thermal integration with EMC shielding, Low cost, compact and reliable water cooling, Low cost, compact, reliable and efficient refrigeration, High heat flux, efficient thermoelectric cooler, High performance air cooling solutions, Advanced modeling tools

Cost/Performance

No significant improvements needed as long as battery power remains constrained. Breakthroughs in plastic batteries could necessitate more aggressive thermal solutions (e.g. improved thermal interfaces, thermal spreaders, package integrated heat sinks, etc.)

Hand Held

RequirementsProduct


Therminic 2002

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0.01 0.1 1 10

die

die

khLBi =Biot number

ThermalResistance

(oC/W)

Die With Convection on All Sides

ForcedGases

Freeliquids

Forcedliquids

Phasechange

Typical air-cooled heat sinkcase-to-ambient thermal

resistance (Rc-a)Acceptable resistance values achievable only by forced liquid cooling and phase change cooling


Therminic 2002

Air velocity: 1. 100 - 300 ft/min; 2. 200 - 500 ft/min; 3. 800 ft/min

Increasing Size of Air-Cooled Heat SinksV

olum

e of

Hea

t Sin

k (c

m3 )

Heat Dissipated (W)0 10 20 30 40 50 60

0

50

100

150

200

250

300

Intel Mobile Pentium 90 MHz

(1998)

AMD K-6 2® 1

Mobile300 MHz

(1999)

Cyrix M II333 MHz

(1997)

AMD K-6 2® 1

450 MHz(1998)

Motorola Power PC 604e(1997)

AMD K-6 III2

450 MHz(1999)

Sun Ultra Sparc II2 480 MHz

(1998)

Intel Pentium II

Xeon2

450 MHz(1998)

Digital 211641

533 MHz (1997)

Apple G4 (2000)

400

80

AMD Athlon2

1.2 GHz(2000)

AMD Athlon XP3

2000+ MHz(2002)

Intel Pentium-IV3

2 GHz(2001)


Therminic 2002

Transport Properties of Various Liquid Coolants

Property Perflourinated Liquid DesignationFC-87 FC-72 FC-84 FC-77 FC-43 Water

Boiling point, oC

Specific heat, J/kg K

Thermal conductivity,W/m K

Surface tension, N/m

Dynamic viscosity, kg/m sec

30

5.5x10-2

8.9x10-3

4.2x10-4

1088

56

1088

5.45x10-2

8.5x10-3

4.5x10-4

83

1130

5.35x10-2

7.7x10-3

4.2x10-4

100

1172

5.7x10-2

8.0x10-3

4.5x10-4

172

1255

6.5x10-2

4.5x10-3

3.9x10-4

100

4184

6.8x10-1

5.9x10-2

2.7x10-4

Danielson, R.D., Tousignant, Bar-Cohen, A., “Saturated pool Boiling Charactersitics of Commercially Available Perflourinated Liquids”, Proc. ASME/JSME Thermal Eng. Joint Conf., Vol.3, pp. 419-430, 1987

(Atmospheric Pressure)


Therminic 2002

Thermosyphon Incorporating Enhanced StructureDetailed view of evaporator

g

Dimensions in mm

201

160

Plate-fin condenser

Con

dens

ed

liqui

d

Evaporator

9090

80

60

Vapor

B

L

Enhancedmicrostructure

Top cap

Bottom cap

Base plate

FC-72

Cartridge heater

Hs


Therminic 2002

Examples of Structures in Copper (wire EDM)

Magnification = 100XMagnification = 100XMagnification = 5 X

• A 100 µm brass wire was used to cut these channels in a 1 mm thick copper plate.

• An overburn of 100 µm results in a final channel width of 200 µm.

Top view Cross-sectional view


Therminic 2002

Wet Chemically Etched Structures

• A set of master masks was fabricated using a high resolution laser printer.• The pattern was transferred to a silicon wafer (<110> orientation) using

photolithography.• The patterned wafer was then etched in a 40 % (by weight) KOH solution,

at 75oC for approximately 2 hours.• Process ideal for mass production, but needs special wafers (<110>

orientation) and at least a class 100 clean room.

Top view Cross-sectional view

Magnification - 10 XMagnification - 2.5 X

Channel size = 60 µm

Pores(60 x 60 µm)


Therminic 2002

Thermosyphon Prototype for Desktop Computer (Implemented with HP Labs and Thermacore)

Major components – evaporator, condenser and connection tubings.

Working Fluid – water, dielectric liquid (PF5060).

Evaporator – has boiling enhancement structure.

Condenser – plate-fins cooled by forced convection.

Fluid transport takes place in a closed loop.

Cooling performance can be monitored by powering the chip at a prescribed percentage of maximum power.


Therminic 2002

Final Configuration of the Thermosyphon


Therminic 2002

Effect of Working FluidsSystem Charged with Water

20 30 40 50 60 70 80 90 1000

10

20

30

40

50

60

Evaporator Bottom ∆T (Evaporator to Ambient)

Tem

pera

ture

(o C)

Power (W)


Therminic 2002

Effect of Inclination on the ThermosyphonEvaporator Temperature vs. Tilting Angle

Fluid – PF5060

-60 -40 -20 0 20 4060

70

80

90

100

110

120

130

Evap

orat

or T

empe

ratu

re (o C

)

Tilting Angle (o)

Dry-out


Therminic 2002

Liquid-Cooling using Microchannel Heat Sink

Large heat transfer coefficientsH

H

dhconst

kdhNu 1

∝⇒=⋅

=

A-AA

AHeat Source

Inlet Flow Outlet Flow

Cover Plate

Manifold Block

Silicon Substrate

Wc

Hc

cc

ccH HW

HWd

+=

2

Mass production made possible by IC microfabrication technique

~ 105 W/(m2 oC)

Small volume ~ several cm3 For water cooled silicon microchannel heat sink of Wc=50 µm, Hc=302 µm and ∆P=2.14 bar, thermal resistance=0.09 oC/(W/cm2) (Tuckerman, 1984)


Therminic 2002

Challenges in Microchannel Liquid Cooling of Microelectronics

( )3

2/11Re21

c

cc

c WnHWQ

Hf

LP

⋅+⋅⋅

=∆ µ

• Temperature non-uniformity

∆P=2.14 bar to achieve thermal resistance of 0.09 oC/(W/cm2) (Tuckerman, 1984)

• Flow distribution

For fully developed laminar flow and constant heat flux, chip temperature increases linearly from inlet to outlet.

Tw

Distance from inlet

Tf

• Large pressure drop

• Accurate prediction of Transport in microchannelManifold design is challenging due to the constrained space


Therminic 2002

Stacked Microchannel Heat Sink

Stacked Micro-channels

Micro-pump

flip-chip

Insulator cap

Heat sink to ambient

PWB

Encapsulant

Hc

WcWf

t

Schematic illustration of the single phase flow loop with a stacked microchannel heat sink


Therminic 2002

fixed flow rate (0.83x10-6 m3/s or

50 ml/min)0.920.940.960.98

11.021.041.061.081.1

1 2 3 4 5Number of layers

1θθ

Variation of thermal resistance

Resistance Network Analysis

0

2

4

6

8

10

1 2 3 4 50

0.002

0.004

0.006

0.008Pressure droppumping power

Number of layers

Pres

sure

dro

p (k

Pa)

Pum

ping

pow

er (W

/cm

2 )


Therminic 2002

Different Microchannel Configurations

xy

z

Not to scale

Wf

Hc

Wc

q”

L

Wf

Hc

Wc

q”

L

Wf

Hc

Wc

q”

L

Wf

Hc

Wc

q”

L

(a) SGMC (b) STMC-PL

(c) STMC- CC (d) STMC-SE

Hc=300 µm

Wc=25 µm


Therminic 2002

Wall Temperature Distribution

300

305

310

315

320

325

0 0.005 0.01 0.015X (m)

Tw(K

) STMC-CC STMC-PLSGMC

STMC-SE


Therminic 2002

Fabrication of Stacked Microchannels

Stacked two-layered micro-channels using precision milling in copper, 1cmx1cm, Hc=450 µm,Wc=275 µm, Wf=275 µm)

Magnified surface image of microchannels in silicon by wafer dicing, Hc=350 µm, Wc=140 µm, Wf=260 µm)

Wc

Wf

Approaches to bond microchannels into a stack

• Eutectic bonding (aluminum-silicon)

• Low temperature epoxy

• 63Sn-37Pb soldering (copper)


Therminic 2002

Concurrent Optimization-Based Design of Reliable Power Electronic (PEBB) Modules

Collaborators: S. Azarm, D. Gopinath, R. Iyengar, P. McCluskey,

B. Reynolds, P. Sandborn, T. K.Trichy


Therminic 2002

ApproachReliability Thermal

Integration Software

Material & Process Cost

Optimization

Wei

ght

CostMinimize

Min

imiz

e

Optimized Set of Designs

Selected Design

Mean = $73.59

70.08 73.59 77.11

0

0.2

0.4

0.6

0.8

1

1.2

1 2 3 4 5

ThermalReliabilityCostiSIGHT

Hysteresis Loop Stabilization

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 0.02 0.04 0.06 0.08 0.1 0.12

Total Equivalent Strain

Von

Mis

es S

tress


Therminic 2002

Desired Outcome

0

0.2

0.4

0.6

0.8

1

1 2 3 4 5 6 7 8 9 10 11 12 13

Temperature

TTF

Cost

Solution Number

Nor

mal

ized

Obj

ectiv

e Va

lue


Therminic 2002

Reliability Assessment

AEPS Module Relevant Failure Mechanisms

Die attach/solder fatigue, DBC cracking, SDDV, TDDB, Die cracking

•Life prediction is crucial to overall design optimization because of trade-offs between product cost, performance and reliability.

•It is important to model and consider multiple failure mechanisms each with its own dependence on geometry, materials, processing and environmental stresses.


Therminic 2002

Reliability Module-Integration Details•Obtains geometrical parameters,material properties and junction temperature.•Sends time to failure.

Reliability Thermal



OptimizationW

eigh

t

CostMinimize

Min

imiz

e


Selected Design

Mean = $73.59

70.08 73.59 77.11

0

0.2

0.4

0.6

0.8

1

1.2

1 2 3 4 5

ThermalReliabilityCost

iSIGHT

Hysteresis Loop Stabilization

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 0.02 0.04 0.06 0.08 0.1 0.12


Von

Mis

es S

tres

s


Therminic 2002

Compact Thermal Resistor Network

TJ = 130 ºC for 8 ThinPaksTM

Number of Devices Junction Temperature (degree C) Numerical Simulation Junction Temperature (degree C)4 108 1158 130 14016 155 170


Therminic 2002

Thermal Module: Integration Details

• Import problem details into thermal model.• Evaluate thermal objectives (junction temperature).• Export results to iSIGHT for analysis of other models.

(Cost & Reliability)

Integration SoftwareOptimization

Wei

ght

CostMinimize

Min

imiz

e


Selected Design

Mean = $73.59

70.08 73.59 77.11

ReliabilityHysteresis Loop Stabilization

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 0.02 0.04 0.06 0.08 0.1 0.12


Von

Mis

es S

tres

s

0

0.2

0.4

0.6

0.8

1

1.2

1 2 3 4 5


iSIGHT

Thermal Material & Process Cost


Therminic 2002

Cost Module: Integration Details•Obtains module/package geometry and materials

• Sends manufacturing cost and yield

Thermal



Optimization

Wei

ght

CostMinimize

Min

imiz

e


Selected Design

Mean = $73.59

70.08 73.59 77.11

0

0.2

0.4

0.6

0.8

1

1.2

1 2 3 4 5


iSIGHT

ReliabilityHysteresis Loop Stabilization

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 0.02 0.04 0.06 0.08 0.1 0.12


Von

Mis

es S

tress


Therminic 2002

Multi-Objective Genetic Algorithm

f1 : Junction Temperature

f 2: C

ost

PARETO FRONTIER

Design Alternative A

Design Alternative B

Design B dominates design A in terms of Junction Temperature and Cost.


Therminic 2002

Results

Substrate thickness=4.74 mmSubstrate Mat : BerylliaLife Cycles = 2401 Solder Mat: J alloy (65Sn 25Ag 10Sb)

Substrate thickness = 3.14 mmSubstrate Mat : ALNLife Cycles = 7893Solder Mat: 90Pb 10Sn

Substrate thickness= 2.51mmSubstrate Mat : AluminaLife Cycles = 5810Solder Mat : J alloy (65Sn 25Ag 10Sb)

Substrate thickness=1.86 mm Substrate Mat : BerylliaLife Cycles = 2756Solder Mat : 90Pb 10Sn

15080

100

120

140

160

100 110 120 130 140Temperature(oC)

Cos

t ($)

16 Thinpacks 8 Thinpacks 4 Thinpacks

2000

3000

4000

5000

6000

7000

8000

80 100 120 140 160Cost ($)

Life

Cyc

le (c

ycle

s)


Therminic 2002

Energy Efficient Data Centers Through Better Thermal Design

Heat generation within devices and

interconnects

Heat rejection Electronics

coolersFacility

Designers


Therminic 2002

Power Dissipation Trends

Ever increasing power density because of push to increase functionality and decrease floor space consumedIn the 70’s and 80’s average heat load for a data center was ~ 50 W/ft2

In 1990, typical rack dissipated ~1 kW, today a rack may dissipate up to ~12 kW with no change in footprint1

Currently, data center heat fluxes can be ~ 200 W/ft2, based on total power to total floor space ratio

1See Schmidt, et al. IPACK 2001, July 8-13


Therminic 2002

Data Centers Modeling Issues

Variety of scales ranging from the facility level to chip levelHeat generation at smallest scales produces global effectsComputationally impossible to resolve all scales accurately

~10’s meters

35mm

2 m

~0.6 m


Therminic 2002

Physical Model IssuesFlow Regime: Turbulent Mixed Convection (most difficult to model)No clear turbulence model to use for complex flows such as thisAuthors simply use standard k-ε models (employs Boussinesq eddy viscosity model) which fails for flows with:

Boundary layer separation Rapid changes in strain ratesStrong secondary motion

Use ‘wall functions’ to alleviate near wall grid resolution requirements

Possible explanation for up to 25% variation between CFD and experimental results1

1 see Schmidt, et. al. (2001) and Patel, et. al. (2001)


Therminic 2002

Vertical Maximum Temperature Variation

‘Board’ maximum temperature for racks in the y = 1 position – end of rowLocation of significant recirculation – see velocity map of z - mid plane

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 240

42

44

46

48

50

52Vertical Temperature Variation

Rack Vertical Height [m]

Tem

pera

ture

[0 C]

A1B1C1D1


Therminic 2002

Summary


Therminic 2002

Backup


Therminic 2002

Thermal Issues in Future Technology Nodes (Contd.,)

Factors Leading to Higher Temperatures

• Poor thermal conductivity of low-κ dielectrics. An order of magnitude lower than silicon dioxide for some porous gels

• Cumulative effect of large number of metal levels and poor low-κdielectric thermal conductivity

• High current density Jmax = 1.3 MA/cm2 (100 nm node) and 3.9 MA/cm2 (22 nm node) and associated quadratic scaling of heat generation

• Low effective thermal conductivity of copper lines over bulk values due to size effects (when feature sizes are of the order of meanfree path of electrons)


Therminic 2002

Thermal Issues Translating to Reliability and Performance• Mean time to failure due to electromigration is exponentially

dependent on temperature (highly sensitive to even small changes in temperature)

• Higher average temperature increases RC delay due to increase in resistance

• Temperature non-uniformity leads to clock skew (impacts at global interconnect level significantly)

Thermal Issues in Future Technology Nodes (Contd.,)

1. International Technology Roadmap for Semiconductors, 2001 edition, Semiconductor Industry Association, San Jose, CA, 2001.

2. A.H. Ajami, M. Pedram, and K. Banerjee, “ Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs,” Custom Integrated Circuits Conference, San Diego CA, USA, 2001.

3. Y.-L. Shen, “Analysis of Joule heating in multilevel interconnects,” J. Vac. Sci. Technol. B, 17, pp. 2115-21, 1999.4. R. Streiter, H. Wolf, Z. Zhu, X. Xiao, and T. Gessner, “Application of combined thermal and electrical simulation

for optimization of deep submicron interconnection systems,” Microelectronic Enginerring, 60, pp. 39-49, 2002.

References


Therminic 2002

Enhanced Structures for Electronics

Dimensions in mm

10

100.25 x 0.25 x 0.55

Nakayama et al. (1984)(HF: 100 W/cm2 Twall: 83.8 oC)

FC-7212.2

10

Mudawar and Anderson (1993)(CHF: 105 W/cm2 Twall: ~143 oC)

FC-72

1.0

4.5

4.5

ϕ 0.8

Oktay (1982)(HF: 50 W/cm2

Twall: 81 oC)

Oktay (1982)(HF: 90 W/cm2

Twall: 86 oC)

FC-86

0.3050.305

0.3050.305

0.51

Anderson and Mudawar (1989)(CHF: 51 W/cm2 Twall: ~113 oC)

FC-72


Therminic 2002

Effect of Working FluidsSystem Charged with PF5060

20 30 40 50 60 70 80 9020

40

60

80

100

120

Evaporator Bottom ∆T (Evaporator to Ambient)

Power (W)

Tem

pera

ture

(o C)


Therminic 2002

Detailed Numerical Simulations(Sixteen Devices on Heat Sink)

Model setup: IcePakTM

Numerical Analysis demonstrating spreading effects

Model Characteristics:L = 3.5 in LC = 3/8 inW = 2.5 in WC = 3/8 in TH = .025 m TC = 1/16 inV = 4 m/s Q = 200 W per device


Therminic 2002

Representative Data Center Model1200 ft2 facility with 28 racks organized in 4 rows of 7 racks deep4 CRAC units feeding into a 0.6 m deep plenumPerforated tiles of 25% porosity arranged to form hot aisle / cold aisle configuration

CRAC Units

Cold Aisle

Hot Aisle

Top view of model geometry


Therminic 2002

Y - Mid Plane Velocity Vectors [m/s]

n.b. plots show every third velocity vector

• Maximum velocity of 9.91 [m/s]• Strong recirculation back into cold aisles and eventually the upper portions of the racks


Therminic 2002

Z - Mid Plane Velocity Vectors [m/s]

n.b. plots show every third velocity vector

• Significant flow around end portion of racks and in areas adjacent to CRAC units


Therminic 2002

Y - Mid Plane Temperature Field [°C]

Temperature field rescaled to plane values

• CRAC exhaust temperature of 15 °C• Max temperature of 51.8 °C for the base case


Therminic 2002

Preliminary Results

Computations performed using Fluent v5.5100 W/ft2 power density – uniform heat distributionStandard k-ε model with standard wall functionssegregated formulation (no buoyancy)5.73 x 105 cells and 4.014 x 106

degrees of freedom

Row A

7

6

5

6

4

3

2

1

Row B

7

6

5

6

4

3

2

1

Row C

7

6

5

6

4

3

2

1

Row D

7

6

5

6

4

3

2

1

Model Nomenclature for Rack Location

x

y

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