en315-06 layout design rule

8/14/2019 EN315-06 layout design rule

1/64


2/64

EN315_6_layout design rules/gbbarte


3/64



4/64


5/64


Standard Cell Layout Methodology 1980s

signals

Routingchannel

VDD

GND


6/64


Standard Cell Layout Methodology 1990s

M2

No Routingchannels

VDD

GNDM3

VDD

GND

Mirrored Cell

Mirrored Cell


7/64


Standard Cells

Cell boundary

N Well

Cell height 12 metal tracksMetal track is approx. 3 + 3

Pitch =repetitive distance between objects

Cell height is 12 pitch

2

Rails ~10

InOut

VDD

GND


8/64


Standard Cells

InOut

VDD

GND

In Out

VDD

GND

With silicideddiffusion

With minimaldiffusion

routing

OutIn

VDD

M2

M1


9/64


Standard Cells

A

Out

VDD

GND

B

2-input NAND gate

B

VDD

A


10/64


Stick Diagrams


11/64



12/64



13/64


Stick DiagramsContains no dimensionsRepresents relative positions of transistors

In

Out

VDD

GND

Inverter

A

Out

VDD

GNDB

NAND2


14/64


CMOS Inverter


15/64



16/64



17/64



18/64



19/64



20/64


Exercise 1


21/64


Exercise 2Describe the function of the circuit


22/64



23/64


Why Have Design Rules?

To be able to tolerate some level of fabrication errors such as

1. Mask misalignment

2. Dust

3. Process parameters (e.g., lateral diffusion)

4. Rough surfaces


24/64


Designed

Result

decreasing dimension

Why Have Design Rules?


25/64


Design Rules

Interface between the circuit designer and process engineer

Guidelines for constructing process masks

Unit dimension: minimum line width scalable design rules: lambda parameter

absolute dimensions: micron rules

Rules constructed to ensure that design works even whensmall fab errors (within some tolerance) occur

A complete set includes

set of layers

intra-layer: relations between objects in the same layer

inter-layer: relations between objects on different layers


26/64


Printing

0.25 0.18

0.13 90-nm 65-nm

Layout

Figures courtesy Synopsys Inc.


27/64


Intra-Layer Design Rule Origins

Minimum dimensions (e.g., widths) of objects on each layer to maintain that object

after fab minimum line width is set by the resolution of the patterning process (photolithography)

Minimum spaces between objects (that are notrelated) on the same layer toensure they will not short after fab

0.15

0.15

0.3 micron

0.3 micron


28/64


Inter-Layer Design Rule Origins

1. Transistor rules transistor formed by overlap of active and poly layersTransistors

Catastrophicerror

Unrelated Poly & Diffusion

Thinner diffusion,but still working

Transistor Layout


29/64


Transistor Layout

1

2

5

3

Transi

stor

I L D i R l O i i C


30/64


Inter-Layer Design Rule Origins, Cont

2. Contact and via rulesM1 contact to p-diffusion

M1 contact to poly

Mx contact to My

Contact Mask

Via Masks

0.3

0.14

both materials mask misaligned

M1 contact to n-diffusion

Contact: 0.44 x 0.44


31/64


Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um


32/64


Metal FillsLayout Density Control for Improved VLSI

Manufacturability

Manufacturing steps involving chemical-

mechanical planarization (CMP) have varyingeffects on device and interconnect features,depending on local characteristics of the layout.

Layout must be made uniform with respect tocertain density criteria, by inserting "fill"geometries into the layout.


33/64



34/64


The design rules are usually described in two ways :

Micron rules, in which the layout constraints such asminimum feature sizes and minimum allowablefeature separations, are stated in terms of absolute

dimensions in micrometers, or, Lambda rules, which specify the layout constraints in

terms of a single parameter (?) and, thus, allow

linear, proportional scaling of all geometricalconstraints.


35/64


Lambda-based layout design rules were originally

devised to simplify the industry- standard micron-based design rules and to allow scaling capability forvarious processes.

It must be emphasized, however, that most of thesubmicron CMOS process design rules do not lendthemselves to straightforward linear scaling. The use

of lambda-based design rules must therefore behandled with caution in sub-micron geometries.


36/64



37/64



38/64



39/64


LAYOUT DESIGN RULES (LDR)


40/64


OU S G U S ( )

SPECIFIES MIN. ALLOWABLE VALUES FOR:-

Widths, separations, extensions, overlaps of features at various masklevels.

LDRS DEVELOPED TO TAKE ACCOUNT OF:-

MINIMUM FEATURE SIZE: This is limited by:- min feature on a mask that can be routinely resolved in resist - Mask

quality, litho tool, litho process, topography of wafer, wafer diameter.

the change that a resist feature undergoes to define the feature on the

wafer - Type of etching or LOCOS or lateral diffusion etc. electrical effects - Depletion spread, current density etc.

ALIGNMENT: Minimum distances required to allow nesting (alignment)between features on different mask levels. Dependent upon:-

Alignment accuracy possible - Litho tool, operator ability. Variation in size or position of finished feature - Litho tool, type of

etching, lateral diffusion, wafer diameter.

Alignment sequence.

LAYOUT DESIGN RULES (LDR)


41/64


LAYOUT DESIGN RULES (LDR) Alignment sequence (cont)

Sequence A results in a large cumulative misalignment betweencritical layers.

i.e. 6 3 misalignment = 3

Where = misalignment between 2 masks

SEQUENCE BSEQUENCE A

9. TOP-COAT

8. METAL

7. CONTACT

6. P+

5. N+

4. POLY

3. P-WELL

2. DEVICE

1. MASK

Mead - Conway LDRs


42/64


Mead Conway LDR s Above process factors - complex and interelated. Hence IC designer uses a

single set of LDRs that take into account all of these factors for each feature.

An IC process will have a set of LDRs expressed in microns. However,features are getting smaller and thus LDRs will be in a continual state of flux.

The one parameter that characterises any process is the minimum featuresize routinely produced by a process. A set of LDRs expressed in terms ofthis feature will survive the longest.

Mead-Conway uses such an approach.

They express the LDRs in terms of a unit length . Where is themaximum deviation of a feature on the wafer that strays from anotherfeature on the same layer or on another layer.

1978 ~ 3m

1983 ~ 2m

1986 ~ 1.5m

1987 ~ 1.2m

1994 ~ 0.5m

Mead - Conway LDRs (cont)


43/64


Mead Conway LDR s (cont) Two features on different mask levels will therefore be

misaligned by as much as 2 on the final wafer.

M-C compromise this misalignment by stating quitereasonably:-

If overlapping of two features is catastrophic for the design

then they must be separated by at least 2 on the originalartwork.

If the overlapping is undesirable but not catastrophic (i.e. anincrease in C or R results) then they should be separated by

at least .

Using this approach the LDRs are greatly simplified althoughpossibly at the expense of increased Si area and reducedcircuit performance.


44/64


SCMOS Design Rule

(see Principle of CMOS VLSI Design, by Weste,page 144 151)
http://scmos_layout%20rules.pdf/http://scmos_layout%20rules.pdf/http://scmos_layout%20rules.pdf/http://scmos_layout%20rules.pdf/http://scmos_layout%20rules.pdf/http://scmos_layout%20rules.pdf/


45/64



46/64


Gate Layout Layout can be very time consuming

Design gates to fit together nicely

Build a library of standard cells

Standard cell design methodology

VDD and GND should abut (standard height)

Adjacent gates should satisfy design rulesnMOS at bottom and pMOS at top

All gates include well and substrate contacts


47/64


Stick Diagrams Stick diagramshelp plan layout quickly

Need not be to scale

Draw with color pencils or dry-erase markers


48/64


Wiring Tracks


49/64


Wiring Tracks

A wiring trackis the space required for a wire

4 width, 4 spacing from neighbor = 8 pitch

Transistors also consume one wiring track

Well spacing


50/64


Well spacing

Wells must surround transistors by 6

Implies 12 between opposite transistor flavors

Leaves room for one wire track


51/64


Area Estimation Estimate area by counting wiring tracks

Multiply by 8 to express in


52/64



53/64



54/64

Example: NAND3


55/64


Example: NAND3

Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates

Metal1 VDD rail at top Metal1 GND rail at bottom

32 by 40


56/64



57/64



58/64



59/64



60/64



61/64



62/64



63/64



64/64


en315-06 layout design rule

Documents