encoders introduction to computer engineering –...

Introduction to Computer Engineering – EECS 203http://ziyang.eecs.northwestern.edu/∼dickrp/eecs203/

Instructor: Robert Dick

Office: L477 Tech

Email: [email protected]

Phone: 847–467–2298

TA: Neal Oza

Office: Tech. Inst. L375

Phone: 847-467-0033


TT: David Bild

Office: Tech. Inst. L470

Phone: 847-491-2083


EncodersDecoders

MultiplexersHomework

Encoders

Assume you have n one-bit signals

Only one signal can be 1 at a time

How many states can you be in?

How many signals are required to encode all those states?

3 R. Dick Introduction to Computer Engineering – EECS 203

EncodersDecoders


Encoder example

Pressed (i2, i1, i0) Code (o1, o0)

000 00001 01010 10011 XX100 11101 XX110 XX111 XX

Implementation?


EncodersDecoders


Priority encoder

What if we want the highest-order high signal to dominate?

Pressed (i3, i2, i1) Code (o1, o0)

000 00001 01010 10011 10100 11101 11110 11111 11

What impact on implementation efficiency?


EncodersDecoders


Decoders

Need to map back from encoded signal to state

Pressed (i1, i0) Code (o3, o2, o1, o0)

00 000101 001010 010011 1000

o0 isn’t always used. Why?Most straightforward implementation?


EncodersDecoders


Straight-forward decoder implementation

n NOTs n inputs

2n ANDs

i1 i1 i0 i0

o0

o1

o2

o3


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Decoder implementation efficiency

n NOTs

n2 n-input ANDS

O(

n2)

Can’t do this for large number of inputs!

Instead, decompose into multi-level implementation


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Multilevel decoder implementation

Starting point

o0 = i2 i1 i0

o1 = i2 i1 i0

o2 = i2 i1i0

o3 = i2 i1i0

o4 = i2i1 i0

o5 = i2i1 i0

o6 = i2i1i0

o7 = i2i1i0


EncodersDecoders


Multilevel decoder implementation

o0 = i2 (i1 i0 )

o1 = i2 (i1 i0)

o2 = i2 (i1i0 )

o3 = i2 (i1i0)

o4 = i2(i1 i0 )

o5 = i2(i1 i0)

o6 = i2(i1i0 )

o7 = i2(i1i0)

Reuse terms! Schematic?


EncodersDecoders


Multiplexers or selectors

Routes one of 2n inputs to one output

n control lines

Can implement with logic gates


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Logic gate MUX

Decoder

i0

i1

i2

i3

s0

s1

o

However, there is another way. . .


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MUX functional table

C Z

0 I01 I1


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MUX truth table

I1 I0 C Z

0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1


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Review: CMOS transmission gate (TG)

C

A

C

B

C = 1

C = 0


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Review: Other TG diagram


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MUX

C

C

C

C

A

B

D


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MUX using TGs

I3

I0

I2

I1

AA BB

ZZ


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Hierarchical MUX implementation

4 :1

mux

4 :1

mux

8 :1

mux

2 :1

mux

0

1

2

3

0

1

2

3

S

S1

S0

S1

S0

Z

ACB

I0

I1

I2

I3

I4

I 5

I6

I7

0

1


EncodersDecoders


Alternative hierarchical MUX implementation

00

11SS

00

11SS

00

11 SS

00

11SS

00

11

S 1

22

33S 0

AA BB

II00

II11

II22

II33

II44

II55

II66

II77

CC

CC

CC


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MUX examples

2:1

m ux

I0

I1

A

Z

Z = A I0 + AI1


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MUX examples

I0

A

I1

I2

I3

B

Z4:1

m ux

Z = AB I0 + A BI1 + AB I2 + ABI3


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MUX examples

I0

A

I1

I2

I3

B

Z8:1

m ux

C

I4

I5

I6

I7

Z = AB C I0 + AB CI1 + A BC I2 + A BCI3+

AB C I4 + AB CI5 + ABC I6 + ABCI7


EncodersDecoders


MUX properties

A 2n : 1 MUX can implement any function of n variables

A 2n−1 : 1 can also be used

Use remaining variable as an input to the MUX


EncodersDecoders


MUX example

F (A,B,C ) =∑

(0, 2, 6, 7)

= AB C + A BC + ABC + ABC


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Truth table

A B C F

0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1


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Lookup table implementation

8:1

MUX

1

0

1

0

0

0

1

11

0

1

2

3

4

5

6

77 S2 S1 S0

AA BB CC

FF


EncodersDecoders


MUX example

F (A,B,C ) =∑

(0, 2, 6, 7)

= AB C + A BC + ABC + ABC

Therefore,

AB → F = C

A B → F = C

AB → F = 0

AB → F = 1


EncodersDecoders


Truth table

A B C F

0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1

F=C


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Lookup table implementation

S1 S0

AA BB

4:1

M UX

0

1

2

33

00

11

FF

C

C


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Demultiplexer (DMUX) definitions

Closely related to decoders

n control signals

Single data input can be routed to one of 2n outputs


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Recall decoders

n NOTs n inputs

2n ANDs

i1 i1 i0 i0

o0

o1

o2

o3


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DMUXs similar to decoders

Use extra input to control output signal35 R. Dick Introduction to Computer Engineering – EECS 203

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Demultiplexer

C

C

C

C

D

A

E


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Dangers when implementing with TGs

C

C

C

C

D

A

E

C = 1


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Dangers when implementing with TGs

C

C

C

C

D

A

E

C = 1

What if an output is not connected to any input?38 R. Dick Introduction to Computer Engineering – EECS 203

EncodersDecoders


Review: Consider undriven inverter inputs

VDD

VSS

A B


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Set all outputs

C

C

C

C

C

C

A

0

E

0

C

C

D


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Demultiplexers as building blocks

3 :8

dec

0

1

2

3

4

5

6

7

A B C

Enb

ABC

ABC

ABC

ABC

ABC

ABC

ABC

ABCS2

S1

S0

Generate midterm based on control signals


EncodersDecoders


Example function

F1 = AB CD + A BC D + ABCD

F2 = ABC D + ABC = ABC D + ABCD + ABCD

F3 = A + B + C + D = ABCD


EncodersDecoders


Demultiplexers as building blocks

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

F1

F3

0

1

2

3

4

5

6

7

8

9

10

1 1

12

13

14

15

A

S3

S2

S1

S0

4:16

dec

Enb

B C D

F2


EncodersDecoders


Status

CMOS

Switch-based and gate-based design

Two-level minimization

Encoders

Decoder

Multiplexers

Demultiplexers

Is anything still unclear? Then let’s do some examples!


EncodersDecoders


Lab three

Requires error detection

Read Section 1.4 in the book

How to build an error injector, i.e., a conditional inverter?

How to build a two-input parity gate?

How to build a three-input parity gate from two-input paritygates?

How to detect even number of ones?


EncodersDecoders


Reading assignment

M. Morris Mano and Charles R. Kime. Logic and Computer

Design Fundamentals. Prentice-Hall, NJ, fourth edition, 2008

Sections 1.2–1.7


EncodersDecoders


Computer geek culture reference

Cliff Stoll. The Cukoo’s Egg. Bantam Doubleday Dell PublishingGroup, 1989


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