Energy-Effective Issue Energy-Effective Issue LogicLogic

Hasan Hüseyin YılmazHasan Hüseyin Yılmaz

OutlineOutline

IntroductionIntroduction Why is Energy Consumption a big issue ?Why is Energy Consumption a big issue ? What can be done ?What can be done ? Objectives ?Objectives ? Related worksRelated works

DefinitionsDefinitions What is issue logicWhat is issue logic

Register Rename Logic Register Rename Logic Wake-up logicWake-up logic Selection logicSelection logic

SolutionSolution Architectural Design Architectural Design

Changes made to wake-up logicChanges made to wake-up logic Changes made to selection logicChanges made to selection logic

ResultsResults ExperimentsExperiments ConclusionsConclusions

Why is power consumption is Why is power consumption is a big issue a big issue More than %95 of the current More than %95 of the current

microprocessor are used in microprocessor are used in embedded systems embedded systems

Battery life is bottleneck of mobile Battery life is bottleneck of mobile systemssystems

Begining to reach the limits of Begining to reach the limits of conventional cooling techniqueconventional cooling technique

Power saving vs performance Power saving vs performance

ObjectivesObjectives

To show the potential in power To show the potential in power saving through dynamically saving through dynamically reconfiguring the issue logicreconfiguring the issue logic

To maximize the flexibility for a To maximize the flexibility for a system to carry out system to carry out reconfigurations in an effective reconfigurations in an effective and efficient mannerand efficient manner

Minimize the impact on Minimize the impact on performanceperformance

Related WorksRelated Works

Scaling voltage and frequency Scaling voltage and frequency dynamically dynamically

Programmable thermal Programmable thermal thresholdthreshold

Disable unused part of the Disable unused part of the processor processor

Reducing cache power Reducing cache power Smart branch predictions Smart branch predictions

mechanismsmechanisms

Pipeline OrganizationPipeline Organization

More flexibility in reconfiguring the pipeline due to More flexibility in reconfiguring the pipeline due to different types of instructionsdifferent types of instructions

Associated signals are disabled when a cluster is Associated signals are disabled when a cluster is disabled disabled power saving !! power saving !!All instructions within an enabled cluster are “visible” to All instructions within an enabled cluster are “visible” to the selection logic the selection logic power inefficient !! power inefficient !!Shrinking in issue queue size Shrinking in issue queue size limit exposure to ILP limit exposure to ILP

Pipeline organization 2Pipeline organization 2

pipeline stagespipeline stages

Experimental system Experimental system

Energy consumption of units in Energy consumption of units in microprocessor for fp programsmicroprocessor for fp programs

Energy consumption of units in Energy consumption of units in microprocessor for integer microprocessor for integer programsprograms

ConcernsConcerns

Concantrate on Issue LogicConcantrate on Issue Logic Issue Logic consist of 2 sub Issue Logic consist of 2 sub

partsparts Wake-up LogicWake-up Logic Selection LogicSelection Logic

Wake-up LogicWake-up Logic

Updates source dependences for instructions in the Updates source dependences for instructions in the issue window waiting for their source operands to issue window waiting for their source operands to become availablebecome available

Selection LogicSelection Logic

Chooses instructions for execution from the pool of ready Chooses instructions for execution from the pool of ready instructions instructions

Power consumptionsPower consumptions

Instruction queue and its associated Instruction queue and its associated issue logic are responsible for %25 issue logic are responsible for %25 of the total power consumption of of the total power consumption of microprocessormicroprocessor

Empty entries and ready entries Empty entries and ready entries wastes power on wake-up logicwastes power on wake-up logic

Dynamically resize instruction queue Dynamically resize instruction queue to utilize energy usage to utilize energy usage

SolutionSolution

Wake-up logic is disabled for Empty Wake-up logic is disabled for Empty and ready entries in issue queueand ready entries in issue queue

An Algorithm developed to An Algorithm developed to dynamically resize the instruction dynamically resize the instruction queuequeue

Energy analysis for wake-up Energy analysis for wake-up logiclogic Energy consumption of empty entries is on average %74.9 of issue logicEnergy consumption of empty entries is on average %74.9 of issue logic Energy consumption of ready entries is on average %14 of issue logicEnergy consumption of ready entries is on average %14 of issue logic Wake-up logic wastes %89 of total issue logicWake-up logic wastes %89 of total issue logic

Issue Queue Structure Issue Queue Structure

Non-ready instructions are hidden from the Non-ready instructions are hidden from the selection logic selection logic power efficient power efficient

Exposure to potential ILP is maximized by Exposure to potential ILP is maximized by maintaining the size of issue queue at all timesmaintaining the size of issue queue at all times

Broadcasting of computed results are restricted Broadcasting of computed results are restricted to non-ready instructions only to non-ready instructions only power power efficientefficient

Dynamically resized issue Dynamically resized issue queuequeue

AlgorithmAlgorithm

Add a bit to reorder buffer Add a bit to reorder buffer Divide instruction queue to smaller portionsDivide instruction queue to smaller portions Set bit zero when instruction dispatchedSet bit zero when instruction dispatched When an instruction is issued this bit is set When an instruction is issued this bit is set

if it is from the youngest portion of if it is from the youngest portion of instruction queueinstruction queue

İncrease a counterİncrease a counter Check counter in certain number of cycles Check counter in certain number of cycles

which is referred as “ quantum”which is referred as “ quantum” İf it is smaller than a determined number İf it is smaller than a determined number

reduce instruction queue size by 1 portionreduce instruction queue size by 1 portion Every 5 quantum we increase queue size 1 Every 5 quantum we increase queue size 1

portion if it is not at maximum sizeportion if it is not at maximum size

Dynamic issue queue AnalysisDynamic issue queue Analysis

Performance hardly effected Performance hardly effected On average %1.7 IPC lostOn average %1.7 IPC lost

ConclusionConclusion

Energy Consumption reduced %15 on average by Energy Consumption reduced %15 on average by whole processor whole processor

Lost %1.7 IPC on average Lost %1.7 IPC on average

Conclusion 2Conclusion 2

““A good design strategy should be flexible enough A good design strategy should be flexible enough

to dynamically reconfigure available resources to dynamically reconfigure available resources according to the program’s needs” [according to the program’s needs” [22].].

Most energy cosuming part of the processor is out Most energy cosuming part of the processor is out of order intruction issuing mechanism.of order intruction issuing mechanism.

Much unneeded activity and checks are done in Much unneeded activity and checks are done in issue logic issue logic

ReferencesReferences

Folegnani, D. and González, A. 2001. Energy-effective issue logic. In Proceedings of the 28th Annual international Symposium on Computer Architecture (Göteborg, Sweden, June 30 - July 04, 2001). ISCA '01.

Bai, Y. and Bahar, R. I. 2004. A low-power in-order/out-of-order issue queue. ACM Trans. Archit. Code Optim. 1, 2 (Jun. 2004), 152-179

Canal, R. and González, A. 2000. A low-complexity issue logic. In Proceedings of the 14th international Conference on Supercomputing (Santa Fe, New Mexico, United States, May 08 - 11, 2000).

Palacharla, S., Jouppi, N. P., and Smith, J. E. 1997. Complexity-effective superscalar processors. In Proceedings of the 24th Annual international Symposium on Computer Architecture (Denver, Colorado, United States, June 01 - 04, 1997).

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