ENG2410 Digital Design

LAB #8 Data Path Design

ENG241/Lab #8 2

Lab Objectives

Understand the steps required for the data path design.

Design and Implement the Arithmetic Logic Unit of a simple CPU.

Understand the concept of modular and hierarchical design.

VHDL will be used throughout the LAB.

ALU

n

n

nData Out G

Data Input A

Data Input B

Cout

S0 S1 S2

Operation Select

Mode Select

Cin

ENG241/Lab #8 3

Part 1Arithmetic Circuit

Design and Implement 4 bits arithmetic unit. Use the n-bit adder implemented in LAB 5. Design the B-logic that select the operation.

Select Output G = A/B/Ci S1 S0 Y Cin=0 Cin=1 0 0 All 0’S G=A (Transfere) G=A+1 (Increment) 0 1 B G=A+B G=A+B+1 1 0 B G=A+ B G=A+ B +1 (Subtract) 1 1 All 1’S G=A-1 (Decrement) G=A (Transfere)

n-bits Parallel Adder

B-logic

S0 S1

Operation Select

n

n

n

A

B

Cin

Cout

nG

YB B

A

S

ENG241/Lab #8 4

Part 2Logic Circuit

Design the logic part of your data path. Use 4 to 1 Multiplexer to select the required

operation.

MUX4 to 1

Ai

Bi

Ai

Bi

Ai

Bi

Ai

0

1

2

3

S0

S1

S0

S1

Gi Gi

ENG241/Lab #8 5

Part 3Data Path

Combine the arithmetic and logic circuits to build the data bath.

Use 2 to 1 Multiplexer to select the operation Arithmetic/Logic.

Arithmetic Circuit

LogicCircuit

A

B

Ci

Co

S0

S1

AB

S0

S1

2 to 1MUX

S0

S1

AB

Ga

Gb

S2

G

ENG241/Lab #8 6

Part 3Data Path

S2 S1 S0 Cin Operation Function 0 0 0 0 G = A Transfer A 0 0 0 1 G = A + 1 Increment A 0 0 1 0 G = A + B Addition 0 0 1 1 G = A + B + 1 Addition with Carry 1 0 1 0 0 G = A + B A plus 1's complement of B

0 1 0 1 G = A + B +1 Subtraction

0 1 1 0 G = A - 1 Decrement 0 1 1 1 G = A Transfer A 1 0 0 X G = BA AND 1 0 1 X G = BA OR 1 1 0 X G = BA XOR 1 1 1 X G = A NOT (1's complement)

ENG241/Lab #8 7

2 to 1 MUX in VHDLlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity mux_2_1 isport ( a,b : in std_logic_vector (3 downto 0);

s : in std_logic; g : out std_logic);

end mux_2_1;

architecture behaviour of mux_2_1 isbegin

up: process (a,b,s)begin

if s=‘0’ then g <= a;else

g <= b;end if;

end process;end behaviour;

ENG241/Lab #8 8

UCF FileNET SW0 LOC = T10; //Slide switches NET SW1 LOC = T9; NET SW2 LOC = V9; NET SW3 LOC = M8; NET SW4 LOC = N8; NET SW5 LOC = U8; NET SW6 LOC = V8; NET SW7 LOC = T5;

NET BTN1 LOC = P149; // Pushbutton switches

NET LD0 LOC = U16; //LEDs NET LD1 LOC = V16;NET LD2 LOC = U15;NET LD3 LOC = V15;NET LD4 LOC = M11;NET LD5 LOC = N11;NET LD6 LOC = R11;NET LD7 LOC = T11;

Lab Report Title Page – Group # and Names Problem Statement System Overview and Justification of Design Block Diagram of the System Circuit, Schematic VHDL Code (Include COMMENTS!)

Arithmetic Logic Unit Simulation Waveform Problems Encountered and Recommendation

ENG241/Lab #7 9

Academic Misconduct

Reports and demos are submitted as a group, but it is a SINGLE group effort

You may talk with other groups but sharing codes or reports is NOT ALLOWED

Copying reports from previous years is also NOT ALLOWED

If we find copying we are REQUIRED to report it