ENG3050ENG3050Embedded Embedded

Reconfigurable Reconfigurable Computing SystemsComputing Systems

Hardware Description Hardware Description Languages Languages

SynthesisSynthesis

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TopicsTopics

Synthesizable/Non-Synthesizable Synthesizable/Non-Synthesizable CodeCode

Translation to HardwareTranslation to Hardware Simulation vs. SynthesisSimulation vs. Synthesis Synthesis: Hints, GuidelinesSynthesis: Hints, Guidelines SummarySummary

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ReferencesReferences

– Kenneth Short, “VHDL For Kenneth Short, “VHDL For Engineers”, Prentice Hall, 2008.Engineers”, Prentice Hall, 2008.

– Sudhakar Yalamanchili, “Introductory Sudhakar Yalamanchili, “Introductory VHDL: From Simulation to Synthesis”, VHDL: From Simulation to Synthesis”, Prentice Hall, 2001.Prentice Hall, 2001.

– VHDL Guidelines for Synthesis”, Siemens Semiconductor Group.

– ““RTL Hardware Design Using VHDL”, Pong RTL Hardware Design Using VHDL”, Pong Chu, Wiley, 2006.Chu, Wiley, 2006.

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Execution Models for VHDL Execution Models for VHDL ProgramsPrograms

Two classes of execution models govern the application of VHDL programs

For SimulationSimulation– Discrete event simulation– Understanding is invaluable in debugging

programs For SynthesisSynthesis

– Hardware inference– The resulting circuit is a function of the building

blocks used for implementation» Primitives: NAND vs. NOR» Cost/performance

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VHDL for SynthesisVHDL for Synthesis

VHDL for VHDL for SimulationSimulation

VHDL for VHDL for SynthesisSynthesis

1.1. Only a subsetOnly a subset of the VHDL language is synthesizable

2.2. You need to understand You need to understand what is meant for simulation versus what is meant for producing hardware (i.e. synthesis)

3. The VHDL subset that is synthesizable is tool specific!tool specific!– Do not expectDo not expect two different tools to produce the same

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Synthesis and Hardware Synthesis and Hardware InferenceInference

Processes can produce very differentvery different results! Why?Why?

Synthesis engine

HDLDesign Specification

Author #1 HDL

Author Hardware Design

Author #2 HDL

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SynthesisSynthesis

Hardware implementation of VHDL code depends

on:

• Coding convention & style used• Fitter technology (synthesis based on compiler)• Optimization option (area vs. speed vs. power)• Nature of application (simple vs. complex)

Not all designs are synthesizable:

several constructs defined in the language cannot be synthesized!

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Non Synthesizable Non Synthesizable SubsetSubset

• Examples of constructs that cannot be synthesized into hardware:

File operations including text I/O Wait and After statements. Assertion/Report statements Loops with no bound (infinite while loop) Real data types are not supported Certain operators e.g., /, **, mod, rem Recursive Functions

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VHDL versus C TerminologyVHDL versus C Terminology

The following comparison shows some rough equivalents The following comparison shows some rough equivalents between the VHDL Concepts and C programming.between the VHDL Concepts and C programming.

1.1.Analyze or compile Analyze or compile the package declaration?the package declaration?

2.2.InstantiateInstantiate a component? a component?

3.3.UseUse a Package? a Package?

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Synthesis: Hardware Synthesis: Hardware Translation Translation

• How does a data type translate to hardware? Integer, Real, Boolean, …

• How do data objects map to hardware? Signals, variables, constants, …

• How are statements translated to hardware? Assignments, operators, …

• How do constructs differ when translated to

hardware? If-Else, Case, For, While, …

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VHDL Hardware VHDL Hardware CorrespondenceCorrespondence

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Variables versus Variables versus SignalsSignals

When a variable is assigned a value, it takes that value immediately (similar to conventional programming languages).

When a signal is assigned a value, the assigned value does not take effect immediately. The signal does not take the new value until after

the process has suspended. As a general guideline, a variable is used to store data

within a process when the new value assigned to the variable is to be used (read) in the same execution of the process.

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Simple Assignment StatementsSimple Assignment Statements

architecture behavior of stover issignal sig_s1, sig_s2: std_logic;beginproc1: process (x, y, z) is -- Process 1 using variablesvariable var_s1, var_s2: std_logic;begin var_s1:= x and y; var_s2:= var_s1 xor z; res1 <= var_s1 and var_s2;end process proc1;

proc2: process (x, y, z) -- Process 2 using signalsbegin sig_s1 <= x and y; sig_s2 <= sig_s1 xor z; res2 <= sig_s1 and sig_s2;end process proc2;

end architecture behavior;

x

y

z

res1

res2

Variables, Signals usually translate into Wires

PS: Simulation mismatch– synthesis collapses

multiple simulation cycles

var_s1 var_s2

sig_s1

sig_s213

Variables and SignalsVariables and Signals

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Inferring Storage for Inferring Storage for VariablesVariables

A variable used before it is defined

There exists an execution sequence (first) where use precedes definition

architecture behavior of sig_var isbeginprocess variable var_s1, var_s2 :std_logic;beginwait until (rising_edge(clk)); var_s1 := x nand var_s2; var_s2 := var_s1 xor y; res <= var_s1 xor var_s2;end process;end behavior;

z

z

resSL

SD

CLK

Q

SL

SD

CLK

Q

var_s2

Latch? Latch? Why?Why?

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library IEEE;use IEEE.std_logic_1164.all;

ENTITY mux2 is PORT(a : IN std_logic; b : IN std_logic; sel : IN std_logic; y : OUT std_logic);END mux2;

ARCHITECTURE behavior OF mux2 IS

BEGIN y <= a WHEN (sel = '0') ELSE b WHEN (sel = '1') ELSE 'X'; END behavior;

library IEEE;use IEEE.std_logic_1164.all;

ENTITY mux2 is PORT(a : IN std_logic; b : IN std_logic; sel : IN std_logic; y : OUT std_logic);END mux2;

ARCHITECTURE behavior OF mux2 IS

BEGIN y <= a WHEN (sel = '0') ELSE b WHEN (sel = '1') ELSE 'X'; END behavior;

Concurrent When Concurrent When StatementStatement

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library IEEE;use IEEE.std_logic_1164.all;

ENTITY mux4 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic);END mux4;

ARCHITECTURE behavior OF mux4 IS BEGIN WITH sel SELECT y <= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN "11", 'X' WHEN OTHERS;END behavior;

library IEEE;use IEEE.std_logic_1164.all;

ENTITY mux4 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic);END mux4;

ARCHITECTURE behavior OF mux4 IS BEGIN WITH sel SELECT y <= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN "11", 'X' WHEN OTHERS;END behavior;

Concurrent With StatementsConcurrent With Statements

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Synthesis of Case StatementSynthesis of Case Statement

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Synthesis of an IF Synthesis of an IF StatementStatement

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Case vs. If StatementsCase vs. If Statements Any case statement does have an equivalent

(functionally) formulation in an if-then-elsif form.

However the if-then-else must produce priority priority logic to maintain the priority order implicit in the nesting of the branches. This is not the situation for the case

statement. Which is more efficient?

As a result we would expect that the case the case statementstatement is a more efficienta more efficient alternative when there is no priority ordering among the alternatives.

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Inference of basic Inference of basic Memory ElementsMemory Elements

• VHDL code should be clear so that the pre-designed cells can be inferred.• VHDL code can (might) produce:

D Latch Positive edge-triggered D FF Negative edge-triggered D FF D FF with asynchronous reset

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Latch vs. Flip Flop InferenceLatch vs. Flip Flop Inference

Predicates in conditional expressions lead to latch inferencelatch inference– if ( sel = ‘1’) then...

Edge detection expressions lead to flip flop flip flop inferenceinference– if (rising_edge(clk)) then...– if (clk’event and clk = ‘0’) then..– if (clk’lastvalue = ‘0’ and clk = ‘1’ and

clk’event) ..

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FlipFlop/Latch Inference FlipFlop/Latch Inference RulesRules

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D LatchD Latch

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Variable as LatchVariable as Latch

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Nested Constructs: D LatchNested Constructs: D Latch

architecture behavior of nested_if is

beginprocess (x,y,z,sel1,sel2,sel3) begin if (sel1 = ‘1’)then res <= x and y; elsif (sel2 =’1’) then res <= y xor z; elsif (sel3 =’1’) then res <= x or y; end if;end process;

• Latch inference due to the absence of the last “else”

sel1

sel2

sel3

x

y

z

res

Condition under which a latch is inferredWhen sel1,sel2,sel3 are all zero

Add an else to avoid latch Add an else to avoid latch inferringinferring

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Positive Edge Triggered Positive Edge Triggered FFFF

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D FF with Async ResetD FF with Async Reset

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Two Types of Resets (Sync, Two Types of Resets (Sync, Async)Async)

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y

z

sel

x

w

(load)

AL

AD

Q

Conditional StatementConditional Statement

architecture behavior of inflate is

beginprocess (x, y, z, sel) is variable s1, s2: std_logic;beginif (sel = ‘1’)then s1:= x and z; s2:= s1 xor y; w <= s2 and s1; end if; end process;end architecture behavior;

conditional body

latch enableS1

S2

How can we avoid latch inference without using else statement?

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-- w gets a value only conditionally-- hence a latch is inferred

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Revisit the ExampleRevisit the Examplearchitecture behavior of inflate isbeginprocess (x, y, z, sel) isvariable s1, s2: std_logic;begin w <= ‘0’; -- output signal set to a default value to avoid latch inference if (sel = ‘1’)then s1:= x and z; -- body generates combinational logic s2:= s1 xor y; w <= s2 and s1; end if; end process;end architecture behavior;

No Latches

x

z

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Muxes vs. LatchesMuxes vs. Latches

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Case StatementsCase Statements

Synthesis of a multiplexor Any incomplete when clause syntax error

architecture behavior of case_st isbeginprocess (x,y,z,sel) is begincase sel is when 0 => res <= x and y; when 1 => res <= y xor z; when 2 => res <= x nand z; when others => res <= x nor z;end case;end process;end architecture behavior;

x

y

z

sel<0>

sel<1>

res

No LatchNo Latch

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Case Statements Case Statements (cont.)(cont.)

Use of the “null” statement and latch inference How do we avoid a latch in this case?How do we avoid a latch in this case?

architecture behavior of case_ex isbeginprocess (x,y,z,sel) isbegincase sel is when 0 => res <= x and y; when 1 => res <= y xor z; when 2 => res <= x nand z; when others => null; -- in this case the value of res -- remains unalteredend case; end process;end architecture behavior;

z

y

x

sel<0>

sel<1>

res

(load)

SEQQ

AL

AD

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Case Statements: Avoiding Case Statements: Avoiding LatchesLatches

1) By having an initialization statement prior to case.

2) Use don’t care values in the “when others” clause often synthesis compilers can use this information to optimize the generated hardware.

architecture behavior of case_ex isbeginprocess (x,y,z,sel) isBeginres <= ‘0’;case sel is when 0 => res <= x and y; when 1 => res <= y xor z; when 2 => res <= x nand z; when others => null; -- in this case the value of res -- remains unalteredend case; end process;end architecture behavior;

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Process: Incomplete Sensitivity ListProcess: Incomplete Sensitivity List

signal a, b, c, y: std_logic …..process (a, b, c) is begin y <= a and b and cend process;

When the ‘a’ signal changes, the process is activated and the circuit acts as expected. On the other hand, when ‘b’ or ‘c’ signal changes, the process remains suspended and the ‘y’ signal keeps its previous value. This impliesThis implies that the circuit has some sort of some sort of memory elementmemory element

signal a, b, c, y: std_logic …..process (a) is begin y <= a and b and cend process;

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Synthesis Modeling Synthesis Modeling Issues Issues Ensuring compatibility between simulation and

synthesis. Both VHDL descriptions below generate the same

synthesis output, but differ in their simulation.

Process (enable, in1, in2) Process (enable, in1, in2, in3)begin beginif (enable =‘0’) then if (enable =‘0’) then output <= (in1 and in2) or in3; output <= (in1 and in2) or in3;end if ; end if;end process; end process;

Full sensitivity list

Note: most synthesis tools ignore the sensitivity list, but IEEE RTLstandard recommends using a full sensitivity list to ensure compatibilitywith the simulation.

Incomplete sensitivity list

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Avoiding Latch Avoiding Latch InferenceInference

Ensure every path computes a value for every signal– Presence of the else branch

» Nested structures» if-then-elsif structure

– Complete sensitivity list– Use initial values

Basic principle: ensure that every combination of input signal values leads to a computation of a value for every output signal

combinational logic

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Synthesis of 3-state Synthesis of 3-state DriverDriver

To specify that an output should be set to the high-To specify that an output should be set to the high-impedance state, we use a signal of type std_logic and impedance state, we use a signal of type std_logic and assign it a value of ‘Z’assign it a value of ‘Z’

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Tri-State BusesTri-State Buses

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Signal Selection in Signal Selection in VHDLVHDL

Signal selection in VHDL for some FPGA targets could be different from that used for ASICs, as shown below:

General signal selection in VHDL

if (sel =‘0’) then output <= signal_0; else output <= signal_1; end if;

Preferred signal selection for FPGAsusing tri-state busses

output <= signal_0 when (EnA = ‘1’) else ‘Z’;output <= signal_1 when (EnB = ‘1) else ‘Z’;

Signal selection is implementedhere using muxes

In some FPGAs, muxes can be expensive,and tri-state buffers are cheaper

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Loop StatementsLoop Statements What/How much hardware should be

generated? Most commonly supported is the for loopfor loop

– Number of iterations is known a priori– Loop is unrolled and optimized as a sequence

of sequential statementsshift_reg (3) <= shift_reg (2);shift_reg (2) <= shift_reg (1);shift_reg (1) <= shift_reg (0);

for N in 3 downto 1 loop shift_reg (n) <= shift_reg (n-1);end loop;

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While loop: unrollingWhile loop: unrolling

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Replicated Logic: Replicated Logic: ProceduresProcedures

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While StatementsWhile Statements

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Synthesis Modeling Synthesis Modeling IssuesIssues

Using parentheses in arithmetic expressions facilitates optimization through resource sharingoptimization through resource sharing, and specification of concurrency, and improves critical path.

The second statement below has a shorter critical path, for instance,

d

Output <= a + b + c + d; Output <= (a + b) + (c + d)

a

b c d

a

b

c

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Efficiency Efficiency ConsiderationsConsiderations

Now that we can control latch inferencing what about circuit size circuit size and speed?

Move common operations (hardware) out of the branches– Good programming practice in general– Trade multiplexors for more expensive hardware

Set up operands

Set up operands

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Efficiency Efficiency ConsiderationsConsiderations

Efficiency Efficiency ConsiderationsConsiderations

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Efficiency Efficiency ConsiderationsConsiderations

Computation (logical AND) preceded by operand selection (mux)

entity inference is port (sel : in std_logic; x, y, z: in std_logic;w: out std_logic );end inference;

architecture behavior of inference isbeginprocess (x, y, z, sel)variable right: std_logic;begin if (sel = ‘1’)then right:= y; else right:= z; end if;w <= x and right; end process;end behavior;

entity inference is port (sel : in std_logic; x, y, z: in std_logic;w: out std_logic );end entity inference;

architecture behavior of inference isbeginprocess (x, y, z, sel) isbegin if (sel = ‘1’)then w <= x and y; else w <= x and z; end if;end process;end architecture behavior;

w

x

y

sel

z

2:1 multiplexor

Logic forthen part

Logic forelse part

x

y

z

sel

w

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Synthesis Hints: Inferring Synthesis Hints: Inferring StorageStorage Generally, edge-detection expressions will cause edge-detection expressions will cause

flip-flopsflip-flops rather than latches to be inferred. Otherwise latches will be inferred.

If you wish to avoid having a latch inferred for a signal in a process then every execution path every execution path through the process must assign a valuethrough the process must assign a value for that signal.

If you use variables in a process before they are use variables in a process before they are defineddefined a latch will be inferred for that variable.

To avoid the inference of latches, make sure that make sure that default values are assigned to signalsdefault values are assigned to signals before a conditional block of code.

For variables or signals assigned within a for-loop a default value must be assigned before the for-loop to avoid latch inference.

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Synthesis HintsSynthesis Hints Avoid programming in C or Java where we try to

exploit the sequentially of the code. This will lead to long signal paths. Attempt to minimize dependencies between statements and try to promote concurrency.

Move common complex operations out of the branches of if-then-else statements and place them after the conditional code. This will generally lead to less generally lead to less hardwarehardware.

Using don’t care values to cover the when others caseUsing don’t care values to cover the when others case in a case statement can enable the synthesis compiler to optimize the logic and create a smaller circuit than if all remaining options were set to values.

Using a case statement rather than an if-then-else construct will produce less logicproduce less logic since priority logic will have to be generated for if-..

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Consistency with SimulationConsistency with Simulation In a simulation model delays can be specified

using the after clause in the signal assignment statements. During synthesis the delay value of the operations are derived from the synthesized implementation. This may differ from the values that the designer specified for simulation.

Include all signals in a process in the sensitivity list of the process to avoid pre-synthesis and post-synthesis simulation mismatches.

Use a VARIABLE instead of a SIGNAL; Variables may be synthesized the same as signals but simulation is faster.

Minimize the number of processes. This avoids the overhead of multiple processes suspending and restarting.

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Variables vs. Signals: Variables vs. Signals: ExampleExample

proc1: process (x, y, z) is -- Process 1variable var_s1, var_s2: std_logic;beginL1: var_s1 := x and y;L2: var_s2 := var_s1 xor z;L3: res1 <= var_s1 nand var_s2;end process;

proc2: process (x, y, z) -- Process 2beginL1: sig_s1 <= x and y;L2: sig_s2 <= sig_s1 xor z;L3: res2 <= sig_s1 nand sig_s2;end process;

variables signals

Distinction between the use of variables vs. signals

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Relational OperationsRelational Operations

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