Department of Electrical Engineering

EE5O3 IC FABRICATION & PACKAGING TECHNOLOGY END OF CHAPTER 1

NAME

REGISTRATION NO.

PROGRAMME

LECTURERS NAME

DATE

REMINDER: Cheating or plagiarism will not be tolerated. All parties involved in cheating or plagiarism will be given zero mark on the specified assessment.

Learning Outcome CLO1 CLO2 CLO3 CLO4 CLO5

Q1(6) Q2(10) Q3(7) Q4(3) Q5(12) Q6(9) Q7(7) Q8(3) Q9(8) Q10(5)

Score

EE5O3 IC FABRICATION & PACKAGING TECHNOLOGY END OF CHAPTER 1

Organize yourself into a group of TWO (Number of students in a group may varies between

class based on lecturer decision). Students are required to answer ALL questions.

Submission guidelines.

Paper: A4, white, staple on upper-left corner, single page printing

Font: Arial, size 10, 1.0 spacing.

All drawing must be hand drown. Copy and paste of picture are not allowed!

Due date: Week 11

Question

1. Explain the steps to obtaining Semiconductor-Grade Silicon (SGS) (6 marks, CLO2, 2.1.3)

2. Illustrate the Czochralski (CZ) method with the aid suitable diagram

(10 marks, CLO2, 2.2.3)

3. Explain the Vapour Phase Epitaxy (VPE) process with the aid suitable diagram.

(7 marks, CLO2, 2.3.4)

4. Explain the benefit of using larger diameter wafer. (3 marks, CL02, 2.3.7)

5. Explain wet oxidation with the aid suitable diagram (12 marks, CLO2, 3.1.4)

6. Explain thermal diffusion steps (9 marks, CLO2, 3.2.4)

7. lllustrate the subsystem for an lon lmplanter (7 marks, CLO2, 3.2.7)

8. Explain photolithography process (3 marks, CLO2, 3.3.1)

9. Explain the terminology for metallization below:

a) Interconnect

b) Contact

c) Mask

d) Metal Plug (8 marks, CLO2, 3.4.1)

10. Compare between wet etching and dry etching in terms of directionality, cost, and

selectivity, typical etch rate and control. (5 marks, CLO2, 3.5.2)

PREPARED BY: Course Lecturer

APPROVED BY: Head of Programme

Date: 17.7.2014 Date:17.7.2014