eos: a monolithic cmos photonic platform
TRANSCRIPT
EOS: A Monolithic CMOS Photonic
Platform
Vladimir Stojanović, Rajeev Ram, Milos Popović*,
Jason Orcutt, Michael Georgas, Jonathan Leu,
Benjamin Moss, Chen Sun, Jie Sun and Hanqing Li
Massachusetts Institute of Technology *University of Colorado, Boulder
Monolithic Si-Photonics for core-to-core and
core-to-DRAM networks
2 2
Supercomputers
Embedded apps
Si-photonics in advanced
CMOS and DRAM process
NO costly process changes
Bandwidth density – need dense WDM
Energy-efficiency – need monolithic integration
Many architectural studies show promise
3
[Shacham’07]
[Petracca’08]
[Vantrease’08]
[Psota’07]
[Kirman’06]
[Joshi’09]
[Pan’09]
[Batten’08] [Beamer’10] [Koka’08-10]
Significant integration activity,
but hybrid and older processes …
4
[Luxtera/Oracle/Kotura] [IBM]
[HP]
[Watts/Sandia/MIT]
[Intel]
130nm
thick BOX SOI
130nm
thick BOX SOI
Bulk CMOS
Backend
monolithic
[Lipson/Cornell]
[Kimerling/MIT]
[Many schools]
Big Challenge:
Efficient integration with circuits
5
Reg
iste
r
Mu
x
Pre-Driver Mod-DriverReceiver
Front-end
Φ Φ Φ
Φ Φ
+
Samplers &
Monitoring
Dem
ux
Reg
iste
r
PLL or
Opt. Clk
1 2 3 4 in PLL or
Opt. Clk
Phase
Adjust
Reg
iste
r
Mu
x
Pre-Driver Mod-DriverReceiver
Front-end
Φ Φ Φ
Φ Φ
+
Samplers &
Monitoring
Dem
ux
Reg
iste
r
PLL or
Opt. Clk
1 2 3 4 in PLL or
Opt. Clk
Phase
Adjust
Dense WDM – 128 wavelengths/waveguide - >1Tb/s per waveguide
Need 1000’s of transceivers on die with < 100fJ/bit cost at > 10Gb/s !
65 nm bulk CMOS Texas Instruments
90 nm bulk CMOS IBM cmos9sf
45 nm SOI CMOS IBM 12SOIs0
6
32 nm bulk CMOS Texas Instruments
~6-uA
EOS Platform for Monolithic CMOS
photonic integration
-200 0 200 400 600 800 1000
-14
-12
-10
-8
-6
-4
-2
0
Tra
nsm
issio
n, dB
Frequency, GHz
2007
2010
Zero-Change
Foundry Mask-Share Integration
7
Integrated link test cell
Detector Modulator
8
Bulk CMOS Cross Section
9
4
Front-end Photonic Integration
10
5
Optical Loss Determines Metal Spacing
• Vertical exclusion (Top Metal) doesn’t
interfere with global signal / power wires
• Lateral Exclusion (Low Metals) doesn’t
violate density rules
Localized Substrate Removal
11
14
Vapor-Phase Selective
Silicon Etch (Undercut)
Single Step
Self-Aligned
RIE Etch
Localized Substrate Removal - SEM
12
14
A 32nm bulk CMOS photonic platform
Monolithic CMOS photonic platform integrated with CMOS circuits
32nm process – fabrication support from Texas Instruments
Robust post-processing steps at MIT
Second-order resonator filterbank shows process precision
Great on-die matching (rings track within 40GHz)
Record thermal heating efficiency 25uW/K
Orcutt et al – CLEO 2008, Optics Express 2010 13
Polysilicon and Silicon Photonics on Thin BOX IBM SOI R
eg
iste
r
Mu
x
Pre-Driver Mod-DriverReceiver
Front-end
Φ Φ Φ
Φ Φ
+
Samplers &
Monitoring
Dem
ux
Reg
iste
r
PLL or
Opt. Clk
1 2 3 4 in PLL or
Opt. Clk
Phase
Adjust
Electrical and photonic integration
– Test row –
A 45nm SOI monolithic platform
14
8 rows of electronic-photonic
WDM links with
body and polysilicon
photonic devices
(72 Transmit-receive test-sites,
~1M transistors and
hundreds of photonic devices)
Body and polysilicon photonic devices
Filterbanks, waveguide paperclips, rings, stand-alone
modulators and photodetectors
Seamless CAD Flow Integration
15
Cadence Virtuoso
Structured Custom
Design Environment
Ensure compatibility:
• geometry constraints
• data flow
• wafer processes
Zero process changes
2-8 design rule waivers
Standard-cell photonic infrastructure
P-cell Skill-code infrastructure
Utilize existing GDS layers to block doping and define
photonic shapes
Optimize by drawing polygons with many vertices
(merged at stream-out)
16
Integration into place and route flow
VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
MACRO block_electronic_etch_row_1
CLASS BLOCK ;
ORIGIN -208 -1794 ;
FOREIGN block_electronic_etch_row_1 208 1794 ;
SIZE 2488 BY 165 ;
SYMMETRY X Y R90 ;
PIN heater_a_1
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ua ;
RECT 431 1870.5 436.5 1882 ;
END
END heater_a_1
...
OBS
LAYER m1 ;
RECT 208 1794 2696 1959 ;
...
END
END block_electronic_etch_row_1
END LIBRARY
modulator.LEF
A representation of photonic block for place
and route.
abstract
layout
Integration of photonics into VLSI tools
18
VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
MACRO block_electronic_etch_row_1
CLASS BLOCK ;
ORIGIN -208 -1794 ;
FOREIGN block_electronic_etch_row_1 208 1794 ;
SIZE 2488 BY 165 ;
SYMMETRY X Y R90 ;
PIN heater_a_1
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ua ;
RECT 431 1870.5 436.5 1882 ;
END
END heater_a_1
...
OBS
LAYER m1 ;
RECT 208 1794 2696 1959 ;
...
END
END block_electronic_etch_row_1
END LIBRARY
modulator.LEF
Layout of
photonics
Layout of
Circuit blocks
abstract
abstract
LEF
LEF
LEF of standard cells, I/O pads
(provided by ARM)
Chip-level verilog
(instantiation of.LEF macros and
connectivity)
Technology files
SOC Encounter
Place and route
Floorplan
(macro placement,power grid, routing
Constraints)
Place&routed
layout
Photonic device
p-cell abstract
custom photonics-friendly auto-fill
layout
EOS test cell
Electrical Area = 256x60 um2, replicated 9 times in each of 8 electrical
rows (4 photonic etch rows).
Cell contains 1 Modulator, 1 Clock Receiver, 2 Data Receivers,
and BERT/digital-scope back-end + link configuration bits
Extended metallic fingers align to photonic structure contacts
EOS chip Clock Receiver
Modulator Driver
Data Receiver
Etch Holes
Modulator
Photodiode
Current-sensing optical data receiver
20
Designed for
• Energy-cost < 100 fJ/bt
• 10-Gb/s, < 0.5mW,
• Minimum input photocurrent ~20uA
• -14dBm sensitivity at R=0.5A/W
• Photodiode placed differentially at
sense-amplifier input, enabling highly
digital design
• Area contains 2 Data receivers:
– one receiver connected to optical
photodiode
– one receiver driven by diode
emulation circuit, with TX PRBS
Integrated
Waveguide
Dynamic-to-Static
ConverterBuffer
BufferLatching Sense
Amplifier
+ +
+
+
- -
Vin+ Vdyn+
Vdyn-
Vout+
Vout-Vin--
-
Vbuf+
Vbuf-
Clock EnableΦ Φ
ΦΦ
Φ
in+ in-
Φ
IPHOTO
10
-um
40-um
Optical clock receiver
Mode-locked laser provides ultra short pulses with little jitter
Sensitivity is improved by integrating the photodiode current
on a capacitive node, instead of using a TIA
Uses duty cycle to adjust reset strength, ensuring lock
21
Injection-locked clock receiver with duty-cycle correction loop
Also works on clock-modulated wavelength
(with jitter rms ~1ps)
Simulated
performance
photodiode
responsivity
0.5 A/W
Input optical
power
-14dBm
Clock
frequency
10GHz
Power
consumption
77uW
Jitter (3 sigma) ±0.15ps
out
Link back-end architecture
BERT and Digital Scope
RxDataB-N
Counter
PRBS
Modulator
Driver
Snapshot
Scanchain
TX RX
DFF
ΦTX
SEnable SEnableTX
DFF
ΦRX
SEnable SEnableRX
PRBS
0
1 +
ber
PRBS Snapshot
0
1
RxDataA-N
Counter PRBS
0
1 +
ber 0
1
RxDataB-P
RxDataA-P 0
1
Snapshot
Snapshot
Test
Test
RxClk-1 Counter
Configurability enables different experiments to be performed
Configuration 1: Optical link
RxDataB-N
Counter
PRBS
Modulator
Driver
Snapshot
Scanchain
TX RX
DFF
ΦTX
SEnable SEnableTX
DFF
ΦRX
SEnable SEnableRX
PRBS
0
1 +
ber
PRBS Snapshot
0
1
RxDataA-N
Counter PRBS
0
1 +
ber 0
1
RxDataB-P
RxDataA-P 0
1
Snapshot
Snapshot
Test
Test
RxClk-1 Counter
Configurability enables different experiments to be performed
Configuration 2: Electrical self-test
RxDataB-N
Counter
PRBS
Modulator
Driver
Snapshot
Scanchain
TX RX
DFF
ΦTX
SEnable SEnableTX
DFF
ΦRX
SEnable SEnableRX
PRBS
0
1 +
ber
PRBS Snapshot
0
1
RxDataA-N
Counter PRBS
0
1 +
ber 0
1
RxDataB-P
RxDataA-P 0
1
Snapshot
Snapshot
Test
Test
RxClk-1 Counter
Configurability enables different experiments to be performed
A full electro-optical test setup
25
DUT Chip
Board
HS
Clocks
FPGA
Control
Board
Fiber PositionerFiber
Positioner
USB to laptop
Microscope
Threshold shift with illumination
By coupling light into the photodiodes we can shift
the threshold of the latch.
The plot shows the threshold shift
for different optical powers. Silicon
waveguides saturate at high optical
power levels (>40mW)
Clock
Receiver
Modulator
Driver
Data
Receiver
Etch Holes
Modulator
Photodiode
Couple laser
Φ Φ
ΦΦ
Φ
in+ in-
Φ
IPHOTO
~10-15uA
1310nm
Data receiver electrical self-test
Counter PRBS
TX RX
0
1 +
ber
RxDataB-P
RxDataA-P 0
1 Snapshot
Test
ΦTX ΦRX
PRBS
Decision
Threshold
On-chip Testing Environment
~6-uA
VDD 1V
Speed 2.5-Gb/s
Power 40fJ/bit
Input Sensitivity 6-uA
No photodiode attached
31-bit PRBS
Runlength=30s
Threshold Code = -9
Φ Φ
ΦΦ
Φ
in+ in-
Φ
IPHOTO
Summary
Monolithic integration in advanced CMOS processes key to system scaling Energy-efficiency
Bandwidth density
EOS Platform designed for multi-project wafer runs Facilitates monolithic CMOS photonic experimentation
Allows flexible testability
Joint optimization of circuits and devices
Early circuits results 40 fJ/b receivers
PDs work at ~1300nm
High tuning efficiency with undercut ~ 25uW/K
Acknowledgments
Dr. Jag Shah - DARPA MTO
Texas Instruments – Dennis Buss and Tom Bonifield
IBM and Trusted Foundry
Intel Corporation – Ian Young and Alex Kern