Error Correction and Partial Information Rewriting for Flash

Memories

Yue Lijoint work with

Anxiao (Andrew) Jiang and Jehoshua Bruck

Block Erasure is Harmful• Decreasing cell level triggers block

erasure– Erasure degrades cell quality

2E. Cohen, “The Nibbles and Bits of SSD Data Integrity”, Flash Memory Summit, 2013.

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Solutions based on Coding

Error Correcting Codes

Trajectory Codes[8]

Codes for Rewriting• Floating Codes

[2]• Buffer Codes [3]• Rank Modulation

[4]• WOM [5, 6, 7]

[8] A. Jiang, M. Langberg, M. Schwartz, and J. Bruck, "Trajectory Codes for Flash Memory,” IEEE Transactions on Information Theory, vol. 59, no. 7, pp. 4530-4541, July 2013.

[2] A. Jiang, V. Bohossian, and J. Bruck, "Floating Codes for Joint Information Storage in Write Asymmetric Memories,” ISIT, 2007.[3] V. Bohossian, A. Jiang, and J. Bruck, "Buffer Coding for Asymmetric Multi-Level Memory,” ISIT 2007.[4] A. Jiang, R. Mateescu, M. Schwartz, and J. Bruck, "Rank Modulation for Flash Memories,” IEEE Transactions on Information Theory , 2009.[5] R. L. Rivest and A. Shamir, “How to reuse a ‘Write-Once’ memory,” Information and Control, vol. 55, pp. 1–19, 1982.[6] E. Yaakobi, S. Kayser, P. H. Siegel, A. Vardy, J. K. Wolf, "Codes for Write-Once Memories,” IEEE Transactions on Information Theory, 2012.[7] D. Burshtein, and A. Strugatski, "Polar Write Once Memory Codes,” IEEE Transactions on Information Theory, 2012.

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Write-Once Memory CodesR. L. Rivest and A. Shamir, “How to reuse a ‘Write-Once’

memory,” Information and Control, vol. 55, pp. 1–19, 1982.

Data Codeword (1st write) Codeword (2nd write)

00 000 11101 001 11010 010 10111 100 011

Write 2 bits twice using

3 cells

000 010 110Example: store 10 then 01

General Rewriting Graph

5

7

6

5

4

3

2

0

1

Directed, Strongly Connected Graph G(V, E)

Data State

Allowed Transition

A message M0 is updated K-1 times following (M1, M2, …, MK-1)

Sum Rate = K log2|V| / N (bits/cell)

Total number of cells

Total number of message bits

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Example: for R-S WOM code, K = 2, |V| = 4, N = 3. Sum Rate = 4 / 3 = 1.33 bits / cell > 1 bit/cell

Performance Measure

General Rewriting Graph

7

7

6

5

4

3

2

0

1

Directed, Strongly Connected Graph G(V, E)

Data State

Allowed Transition

Partial

Maximum outdegree << |V|

Motivation of Partial Rewriting

Server

A B C

Remote File Synchronization

Update

SynchronizationSync

hron

izatio

n

Dropbox orMobile App

Server

8

BSC(p)

Trajectory Codes

0

a0

a0 b

a5 b

0 1 2a b 5a …

9

Store 0

1

2

5

Update to

Update to

Update to

[1] A. Jiang, M. Langberg, M. Schwartz, and J. Bruck, "Trajectory Codes for Flash Memory,” IEEE Transactions on Information Theory, vol. 59, no. 7, pp. 4530-4541, July 2013.

RegisterA register is a group of

cells

log2|V| bits

log2|D| < log2|V| !!

BSC(p)

BSC(p) BSC(p)

BSC(p)BSC(p)

for Noisy Cells

A register goes through a BSC(p) between two updates.

?

Construction 1 (Example: C = 3, t = 2, K = 6)

0

0 1 2a b 5a …

10

Write 0Corrects BSC(p*3)

Corrects BSC(p*2)

Corrects BSC(p)

0Update to 1 aBSC(p)

0Update to 2 a bBSC(p) BSC(p)

0Update to 5 a bBSC(p) BSC(p) BSC(p)

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Bounds on Achievable Code Rates

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Sum Rate = K log2|V| / N (bits/cell)

N = N0 + N1 + … + Nc-2 + Nc-1

N0 = log2 |V| / minj R0,j Ni = log2 D / minj Ri,j if i > 0

Upperbounds and lowerbounds of R0,j and R0,j can be derived with Polar ECC-WOM [2]

[2] A. Jiang, Y. Li, E. En Gad, M. Langberg, and J. Bruck, “Joint Rewriting and Error Correction for Write-Once Memories,” ISIT, 2013.

Instant rate of the j-th write of the i-th ECC-WOM code

Performance of Construction 1• Compare the bounds of three cases–Max degree: D is larger 21024

– D is smaller 213

– Basic ECC-WOM using only 1 register• Parameters–Message length: log2 |V| = 1KByte (213

bits)– Number of registers: C = 8– Channel error rate p = 10-3

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Performance of Construction 1

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Construction 2 (Example: C = 3, t = 2, K = 6)

0S0

0 1 2a b 5a …

Write 0Corrects BSC(p)

Corrects BSC(p)

Corrects BSC(p)

BSC(p)

a, S0 + S’0

01S’0 BSC(p) BSC(p)

a, S0 + S’0

02S’’0

S1

S’1

b, S’0 + S’’0, S1 + S’1BSC(p) BSC(p)

a, S0 + S’0

0Read 2S’’’0 S’’1

b, S’0 + S’’0, S1 + S’1

S2 BSC(p)

S’2

Recover S1 by decoding S’1 = S1 + BSC(p)Recover S0 by decoding (S’’0 + (S0 + S’0)) = S0 + BSC(p)Recover S0 by decoding S’0 = S0 + BSC(p)Recover S2 by decoding S’2 = S2 + BSC(p)Recover S1 by decoding (S’’1 + (S1 + S’1))= S1 + BSC(p)Recover S0 by decoding (S’’’0 + (S0 + S’0) + (S’0 + S’’0))= S0 + BSC(p)

Performance of Construction 2

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Generalizations• When t = 1and M0 = M1 = … = MK-1

– Erasure-free memory scrubbing [3]– Error correction pointer [4]

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Information Storage Area Error Logging Area

[3] Y. Li, A. Jiang, and J. Bruck, ”Multiphase Scrubbing for Phase-Change Memories,” Technical Report, 2013.

[4] S. Schechter, G. Loh, K. Straus, and D. Burger, “Use ECP, not ECC, for hard failures in resistive memories.” In Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10), 2010.

Generalizations (2)• Error correction support for all kinds of rewriting

codes!

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WOM [5,6,7]

Floating Codes [2]

Buffer Codes [3]

Summary• Error correction trajectory codes are

– Efficient • when D << |V|

– General• Existing practical memory scrubbing/ECP schemes• Error correction for various rewriting codes

– Extensible• q-ary ?• Asymmetric noise channel ?• Capacity ?

18Thank You