essential vhdl systhesis

8/12/2019 Essential VHDL Systhesis

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Essential VHDL 71

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity ints isport (a, b: in integer range 0 to 15;

sum: out integer range 0 to 15;sb: out std_logic);

end ints;

architecture synthesis of ints is--Define a subtype fourbitssubtype nibble is integer range 0 to 15;

--Declare a signal int_tmp of type nibblesignal int_tmp: fourbits;

signal bit_tmp: std_logic_vector(3 downto 0);

begin

--Add a and b and assign to an integer

int_tmp


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Essential VHDL 83

architecture count of synthesis is

signal A: std_logic_vector(3 downto 0);

begin

processbegin

wait until clk=1;if reset = 0 then

A


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Essential VHDL 87

process(clk,A)begin

if (clkevent and clk=1) thenif reset = 1 then A


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Essential VHDL 89

process(A,X)begin

if A = "00" thenX


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Essential VHDL 91

if SIG = "11"then D Z Z Z Z null;end case;

B


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Essential VHDL 93

process(input)variable result : bit;

begin

result := 0;

for k in 0 to 3 loopresult:= result xor input(k);

end loop;

parity_out


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Essential VHDL 95

expressing the structure of the digital system under design.

The basic structural statement is the component instantiation statement thatnames the instance, declares which entity is being instantiated, and associates sig-nals and ports with the ports on the entity.

ADDER

EXAMPLE

A

B

DIN

CLK

RESET

SUM

REGISTER

DOUT

TMP

AIN

BINDREG

CLOCK

RESET

AIN

BIN

CLOCK

RESET

DREG

Figure 7.39 Structural Design

Assuming an adder and a register entity are available they can combined bycreating a new entity/architecture pair that species how they are to be connectedor wired together to build an incrementer.

96 Digital Engineering with VHDL

entity example ofport ( AIN, BIN: in std_logic_vector(7 downto 0);

DREG: out std_logic_vector(7 downto 0);CLOCK: in std_logic;RESET: in std_logic);

end example;

architecture structural of example is

--Required for VHDL 1987component adder

port(A, B: in std_logic_vector(7 downto 0);S: out std_logic_vector(7 downto 0));

end component;

--Required for VHDL 1987component reg

port( DIN: in std_logic_vector(7 downto 0);DOUT: out std_logic_vector(7 downto 0);

RESET: in std_logic;CLK: in std_logic);

end component;

signal TMP: std_logic_vector(7 downto 0);

begin

--VHDL 1987 InstantiationU0: adder port map (AIN, BIN, TMP);U1: reg port map (TMP, DOUT, RESET, CLOCK);

--VHDL 1993 Direct InstantiationU0: entity work.adder(synth) port map (AIN, BIN, TMP);U1: entity work.reg(synth) port map (TMP, DREG, RESET, CLOCK);

end structural;

Figure 7.40 Structural Design

A bit of bother is the component declaration (VHDL-93 does not require thisas it supports direct instantiation) that is required in the architecture (or a support-ing package) that species the ports on the instantiated entity (notice that the com-ponent declaration contains the same information as the entity declaration.)


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Essential VHDL 101

Common Mistakes

1) Getting fancy. Keep your VHDL simple. If you are lost draw a block diagramand then write the VHDL for each block as a process in an entity/architecturepair connecting the processes with signals.

2) Being too simple. Remember digital systems are concurrent systems. Usemultiple processes and concurrent signal assignment statements to break upthe behavior of your circuit. A typical use of multiple processes and currentstatements is to separate sequential blocks from combinational blocks.

3) Forgetting your boolean algebra - A NAND B NAND C is not equal to NOT(A AND B AND C).

4) Precedence - VHDL does not assign precedence to the AND and OR opera-tors. Hence given the equation A AND B OR C AND D you will get a com-piler error. Parenthesis must be supplied. You will likely want (A AND B) OR(C AND D).

5) Duplicate assignments - In this course we can only have one concurrent signalassignment to a signal or port. If two drivers assign a common node in a cir-cuit an error will occur both in the VHDL simulation and in the actual circuit.

This is a very common error. Outputs cannot be connected directly together.This does not work in VHDL or in digital logic at the RTL level. You mustuse a multiplexer or a tri-state bus controlled by a conditional to enforcemutual exclusion on the shared signal. A signal can be assigned repeatedly ina single process, but not in multiple processes.


begin A


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Essential VHDL 103

Multiplexer and control signalenforces mutual exclusion soonly adder or subtracter drivessignal A

enforces mutual exclusion soonly adder or subtracter drivessignal A

Tri-state drivers and control signal

Adder drives a value on A

Subtracter drives a value on A

X

Y

X

Y

+

-

CON

A

Create two tri-state driversto mutiplex values onto A

Adder drives a value on A

Subtracter drives a value on A

X

Y

X

Y

+

-

A

CON

A


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Essential VHDL 105

Basic Rules

Always include the library and use declarations.

Use the std_logic and std_logic_vector types. No need to get fancy with entitydeclarations.

Adhere to the style guidelines.

Use the architecture declarative region to declare signals.

Use case statements instead of if statements.

Simple combinational circuits should use concurrent statements.

Signals in unclocked processes must be assigned a value for every possibleexecution sequence of the process to avoid unintended latches.

Use case statements for combinational logic.

If statements when used for combinational logic must include an else part toensure all signals are assigned a value under all possible execution sequences of the if conditional.

Use a process for clock circuits.

Use Wait until clk =1; for a synchronous reset.

Wait until clk =1; must be the rst statement in a process and can onlyappear once.

Use (clkevent and clk=1) for asynchronous resets.

(clkevent and clk=1) must either be the only conditional of an if-then-endstatement, or must be the elsif conditional of a if-then-elsif-then-end statement.


The use of variables does not ensure the generation of combinational logic. Thesame rules as for signals must be observed.

Understand the capabilities of your target technology and dont ask throughyour VHDL synthesis system do more than it can. Remember you are describ-ing hardware that consists of basic gates, registers, adders, and counters.

essential vhdl systhesis

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