evaluating the adau1442, adau1445, and adau1446 …€¦ · evaluating the adau1442, adau1445, and...

Evaluation Board User GuideUG-032

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the ADAU1442, ADAU1445, and ADAU1446 SigmaDSP Products

See the last page for an important warning and disclaimers. Rev. 0 | of 44

FEATURES 8-channel analog input and 16-channel analog output Optical and electrical S/PDIF connections directly to the

S/PDIF I/O pins on the DSP Full access to all digital I/O via digital connectors Built-in USB communications interface Built-in power regulator with wall supply Interface to external GPIO board Self-boot capability Includes full version of SigmaStudio programming tools Compatible with industry-standard communications and

audio interfaces

PACKAGE CONTENTS EVAL-ADAU144xEBZ Universal power supply USB cable GPIO daughter board EVAL-ADUSB2EBZ QuickStart Guide

GENERAL DESCRIPTION This document explains the design and setup of the evaluation boards for the ADAU1442, ADAU1445, and ADAU1446 SigmaDSP® products. Two evaluation boards are available: the EVAL-ADAU144xEBZ for evaluation of the ADAU1442 and ADAU1445, and the EVAL-ADAU1446EBZ for evaluation of the ADAU1446. Together, the boards are referred to as the EVAL-ADAU144xEBZ.

The EVAL-ADAU144xEBZ provides a full range of analog and digital inputs and outputs to and from the ADAU144x. The SigmaDSP can connect to analog I/O signals through AD1938 codecs. Digital I/O connections are available in both S/PDIF and 3-wire serial data formats.

EVALUATION BOARD FUNCTIONAL BLOCK DIAGRAM

ADAU144xSELF-BOOT

EEPROM

SPI/I2C

AD1938CODECS

ANALOGOUTPUTS

DIGITALCONNECTORS

MULTIPURPOSE PIN INTERFACE

USB CONTROLINTERFACE

POWER SUPPLYREGULATION

COMMUNICATIONSHEADERS

ANALOGINPUTS

S/PDIFRECEIVER ANDTRANSMITTER

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Figure 1.

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UG-032 Evaluation Board User Guide

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TABLE OF CONTENTS Features .............................................................................................. 1 Package Contents .............................................................................. 1 General Description ......................................................................... 1 Evaluation Board Functional Block Diagram ............................... 1 Revision History ............................................................................... 2 Using the EVAL-ADAU144xEBZ with SigmaStudio ....................... 3

SigmaStudio Software Installation ............................................. 3 Installing the Drivers ................................................................... 3 Connecting the Evaluation Board .............................................. 4 Adding the EVAL-ADAU144xEBZ to a SigmaStudio Project 4 Adding an ADAU144x IC ............................................................ 5 Adding a Self-Boot EEPROM ..................................................... 5 Programming the Signal Flow .................................................... 5 Monitoring the USB Communications ................................... 12 Programming the Self-Boot EEPROM .................................... 12

Hardware Description .................................................................... 13 Integrated Circuits (ICs) ............................................................ 13 Crystal Resonators ...................................................................... 16

Transistors ................................................................................... 17 Links ............................................................................................. 18 Switches ....................................................................................... 20 Connectors and Jacks................................................................. 22

Circuit Schematics .......................................................................... 24 ADAU144x SigmaDSP .............................................................. 24 S/PDIF Transmitter and Receiver ............................................ 25 Self-Boot EEPROM .................................................................... 25 AD1938 Audio Codecs .............................................................. 26 Analog Audio Inputs .................................................................. 27 Analog Audio Outputs ............................................................... 30 External Connectors .................................................................. 34 USB Control Interface ............................................................... 37 Reset Generator .......................................................................... 38 Power Supply ............................................................................... 38 Bill of Materials ........................................................................... 39 ESD Caution................................................................................ 43

REVISION HISTORY 4/10—Revision 0: Initial Version

Evaluation Board User Guide UG-032

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ad.

USING THE EVAL-ADAU144xEBZ WITH SigmaStudio SigmaStudio SOFTWARE INSTALLATION SigmaStudio™ must be installed to use the EVAL-ADAU144xEBZ. To install the Sigma Studio software, obtain the password from the QuickStart™ Guide and follow these steps:

1. If Microsoft® .NET Framework Version 2.0 is not already installed on the PC, install it by downloading the redistri-butable package from the Microsoft website.

2. Download the SigmaStudio software from http://www.analog.com/sigmastudiodownlo

3. Open the .zip file and extract the files to your PC. 4. Install SigmaStudio by double-clicking setup.exe and

following the prompts. A computer restart is not required.

INSTALLING THE DRIVERS After SigmaStudio is installed, follow these steps to install the drivers:

1. Plug the USBi into the USB port of the PC using the included mini USB cable.

2. If this is the first time the USBi has been connected to the PC, the Windows Found New Hardware notification should appear in the taskbar.

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Figure 2. Windows Found New Hardware Notification

3. When the Found New Hardware Wizard opens, click Install from a list or specific location (Advanced).

4. Click Next.

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Figure 3. Windows Found New Hardware Wizard

5. Click Search for the best driver in these locations and select Include this location in the search.

6. Click Browse and select the USB drivers subfolder, located in the SigmaStudio install directory.

7. Click Next.

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Figure 4. Windows Found New Hardware Wizard Search and Install Options

8. When the warning about Windows logo testing appears, click Continue Anyway.

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Figure 5. Windows Logo Test Warning

Next, Windows proceeds with the installation of the drivers, as shown in Figure 6.

http://www.analog.com/sigmastudiodownload


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Figure 6. Windows Installation of the USBi Drivers

9. When the installation of the drivers is complete, the window shown in Figure 7 appears. Click Finish.

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Figure 7. Driver Installation Complete

A notification of successful installation should appear in the taskbar, as shown in Figure 8.

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Figure 8. Successful Driver Installation Notification

CONNECTING THE EVALUATION BOARD 1. Plug the included dc power supply into the J24 power jack on

the board. 2. Connect the USBi 10-pin communication cable to the J18

communications port on the evaluation board.

ADDING THE EVAL-ADAU144xEBZ TO A SigmaStudio PROJECT To use the EVAL-ADAU144xEBZ with SigmaStudio, follow these steps:

1. Start the SigmaStudio software. 2. Begin a new project by opening the File menu and

selecting New Project. (The keyboard shortcut for this operation is Ctrl + N.)

3. The default view in SigmaStudio is the Hardware Configuration tab. a. On the left side of the screen is the Tree Toolbox tab. b. Within the Tree Toolbox there is a subsection called

Communication Channels. From the list of Communi-cation Channels, click and hold USBi dragging it to the right into the empty white project space. See Figure 9 and Figure 10 for details.

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Figure 9. Adding the USBi Communication Channel to the Evaluation Board

for the ADAU144x

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Figure 10. Adding a USBi to the Project

If SigmaStudio cannot detect the USBi on the USB port of the computer, the background of the USB label turns red, as shown in Figure 11. This happens if the USBi is not connected or when the drivers are not installed correctly.

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Figure 11. EVAL-ADAU144xEBZ Not Detected by SigmaStudio

If SigmaStudio detects the USBi on the USB port, the back-ground of the USB label changes to orange, as shown in Figure 12.


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Figure 12. USBi Detected by SigmaStudio

ADDING AN ADAU144x IC To communicate with the targeted ADAU144x IC on the evaluation board, add ADAU144x to the processor list in SigmaStudio.

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Figure 13. Adding an ADAU144x IC

To use the USBi to communicate with the target ADAU144x IC, click the top blue pin of the USB and drag a wire to the green pin of the ADAU144x IC 1, as shown in Figure 14. The I2C Address 0x70 is assigned automatically.

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Figure 14. Connecting the EVAL-ADAU144xEBZ to an ADAU144x IC

ADDING A SELF-BOOT EEPROM To evaluate the EVAL-ADAU144xEBZ self-boot functionality, an E2Prom IC must be added to the project. This corresponds to the EEPROM U2 device on the evaluation board.

1. Click and drag an E2Prom IC into the project space. 2. Drag a wire from the second blue pin on the USBi to the

green pin on the E2Prom IC, as shown in Figure 16.

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Figure 15. Adding an E2Prom IC

When the second pin on the USBi communication channel is connected to the EEPROM, I2C Address 0xA0 is assigned automatically.

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Figure 16. Connecting the EVAL-ADAU144xEBZ to the E2Prom IC

An E2Prom IC does not have to be added unless the self-boot functionality of the board is required.

PROGRAMMING THE SIGNAL FLOW To program the signal processing flow, use the Schematic tab, located at the top of the window as shown in Figure 17.

1. Click the Schematic tab.

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Figure 17. Schematic Tab


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The left side of the schematic box shows the Tree ToolBox. It contains a list of all signal processing algorithms for use in the ADAU144x, as shown in Figure 18.

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Figure 18. Tree ToolBox

2. Open the IO folder.

a. Open the Input subfolder.

b. Locate an Input cell, as shown in Figure 19.

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Figure 19.Locating an Input Cell

3. Click and drag the Input cell into the project space, as shown in Figure 20.

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Figure 20. Input Cell

4. Open the IO folder.

a. Open the Output subfolder.

b. Locate an Output cell, as shown in Figure 21.

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Figure 21. Locating an Output Cell

5. Click and drag the Output cell into the project space, as shown in Figure 22.


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Figure 22. Input Cell and Output Cell

To have stereo inputs and outputs, one additional Output cell is required.

6. Select the Output1 cell.

a. Press Ctrl + C to copy the cell.

b. Then press Ctrl + V to paste the copy of the cell. There should now be two output cells, as shown in Figure 23.

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Figure 23. Stereo Input and Output

To control the volume of the output, a volume control is required.

7. Open the Volume Controls folder.

a. Open the Adjustable Gain subfolder.

b. Open the Shared Slider subfolder.

c. Open the Clickless SW Slew subfolder.

d. Locate the Single SW slew vol cell.

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Figure 24. Locating the Single Slew Volume Cell

8. Click and drag the Single SW slew vol cell into the project space, as shown in Figure 25.

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Figure 25. Stereo Input and Output with Slew Volume

To make the volume control stereo, follow these steps as illustrated in Figure 26.

9. Right click SW_vol_1, the volume control cell.

10. Select Grow Algorithm, 1. Volume (SW slew).

11. Select 1.


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Figure 26. Growing the Volume Control

The resulting volume control cell has two inputs and two outputs marked with the green and blue points in Figure 27.

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Figure 27. Stereo Volume Control

To add an equalizer, a filter is required. To add a filter, follow these steps (illustrated in Figure 28):

12. Open the Filters folder.

a. Open Second Order subfolder.

b. Open the Single Precision subfolder.

c. Open the 2 Ch subfolder.

d. Locate the Medium Size Eq cell.

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Figure 28. Locating the Medium Size Equalizer Cell

13. Click and drag the Medium Size Eq cell into the project space, as shown in Figure 29.

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Figure 29. Stereo Audio Flow with Volume Control and Single-Band Equalizer

To add more bands to the equalizer, follow Step 14 through Step 16 (illustrated in Figure 30) and adjust the filter parameters following Step 17 and Step 18.

14. Right-click Grow Algorithm.

15. Select 1. 2 Channel – Single Precision.

16. Select 2.

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Figure 30. Growing the Equalizer

17. Click the blue equalizer icon to alter filter parameters (see Figure 31).

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Figure 31. Filter Parameters Icon


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18. Configure the filter parameters for each band, as desired (see Figure 32).

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Figure 32. Filter Parameters

Figure 33. Completed Audio Path 19. For each cell, click the blue pin and drag a wire to the green pin to create an audio path from the input to the output for each channel, as shown in Figure 33.

20. Set the switches and jumpers to correspond to the default settings in Figure 35. A black rectangle corresponds to the position of a switch or jumper.

21. Connect an audio source to the audio input jack, J12, and a pair of headphones or powered speakers to the audio output jack, J4.

22. Click the Link Compile Download button to download the program to the ADAU144x IC.

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Figure 34. Link Compile Download

The device should now process audio in real time.


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Figure 35. Default Switch and Jumper Settings


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Default Switch and Jumper Setting Descriptions

The default setup represents the state of the board when it leaves the factory. With this configuration, the analog audio is routed from the input connectors to the codecs, in and out of

the DSP, back through the codecs, and to the output connectors. Descriptions with direction references are based on the orienta-tion of the board shown in Figure 35.

Table 1. Default Switch and Jumper Setting Descriptions Board Element Description Crystal Oscillator Circuit Used as a master clock source. LK1 connected. Regulator DVDD, IOVDD, AVDD Active. LK5, LK11, and LK13 connected. PVDD Active. Op Amps Use a 5 V supply. LK19 connected. USB Communications Active and in I2C mode. LK27 is in the up position. Note that the SPI functionality of the USB

communications interface has not yet been implemented, and users wishing to test SPI functionality should connect the EVAL-ADUSB2 (USBi) to the Aardvark header, J18.

PLLx Set to 010, 256 × fS mode. The S2 Switch 1, S2 Switch 2, and S2 Switch 3 are in the right, left, and right, positions, respectively.

CLKMODEx In Mode 01, with buffered oscillator output. The S2 Switch 4 and S2 Switch 5 are in the right and left positions, respectively.

SELFBOOT Inactive. The S2 Switch 6 is in the right position. ADRR0 Set to 0. The S2 Switch 7 is in the right position. CDATA Line Active. The S2 Switch 8 is in the right position. S/PDIF Receiver Set to RCA/coaxial connector. The S1 switch is in the right position. Codec 1 and Codec 2 Set as slaves to the ADAU144x. LK7 and LK9 are in the right position. Serial Ports on Codec 1 and Codec 2 Set as slaves to the ADAU144x. LK6 and LK8 are in the right position. Connection Between the Codecs

and the ADAU144x Enabled. The S6 and S7 switches are in the up position.

Op Amp Reference Set to FILTR. LK18 is connected, and LK17 is disconnected. Microphone Input Disabled. LK14 is in the up position. Self-Boot EEPROM Connected to the ADAU144x IC. LK15 and LK16 are connected. GPIO Interface Board Supply Set to 3.3 V. LK10 is set to 3.3 V. External Communications Interface Set to I2C mode. The S4 switch is set to I2C.


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MONITORING THE USB COMMUNICATIONS Use the Capture Window to view all communication transfers between the PC and the target IC (see Figure 38). For each write, the write mode, time of write, cell name (if applicable), parameter name, address, data (in decimal and hexadecimal), and length are shown.

Click the expand/collapse button in the leftmost column to view the full data write. Otherwise, for block writes where more than one memory location is written, only the first location is shown.

PROGRAMMING THE SELF-BOOT EEPROM After compiling a project, the registers and RAM contents of the ADAU144x can be written to a target EEPROM for self-boot. To use this functionality

1. Connect an E2Prom IC to the EVAL-ADAU144xEBZ in the Hardware Configuration window.

2. Verify that the EEPROM write protect pin is disabled on the target board.

3. Link-compile-download the project by clicking the Link Compile Download button.

4. Right-click the ADAU144x IC, and select Write Latest Compilation to E2PROM, as shown in Figure 36.

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Figure 36. Writing to the Self-Boot EEPROM

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Figure 37. Self-Boot EEPROM Download Progress Bar

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Figure 38. Output Capture Window


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HARDWARE DESCRIPTION INTEGRATED CIRCUITS (ICs)

U22

U7

U5

U6

U21U4U3

U2

U1

U18

U16

U17

U20

U19

LK29

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Figure 39. IC Layout


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Table 2. IC Descriptions Reference Functional Name Description U1 ADAU144x SigmaDSP Digital audio signal processor U2 24AA256-I/ST 256 kb serial EEPROM Self-boot memory U3 AD1938 audio codec ADC for Input 0 to Input 3; DAC for Output 0 to Output 7 U4 AD1938 audio codec ADC for Input 4 to Input 7; DAC for Output 8 to Output 15 U5 TOTX141P 15 Mbps optical transmitter S/PDIF output jack U6 TORX147L 15 Mbps optical receiver S/PDIF input jack U7 SC937-02 110 Ω AES/EBU transformer Transformer for electrical S/PDIF output U8 AD8608ARZ low noise op amp Filter op amp for Output 0 to Output 3 U9 AD8608ARZ low noise op amp Filter op amp for Output 4 to Output 7 U10 AD8608ARZ low noise op amp Filter op amp for Output 8 to Output 11 U11 AD8608ARZ low noise op amp Filter op amp for Output 12 to Output 15 U12 AD8608ARZ low noise op amp Filter op amp for Input 0 to Input 1 U13 AD8608ARZ low noise op amp Filter op amp for Input 2 to Input 3 U14 AD8608ARZ low noise op amp Filter op amp for Input 4 to Input 5 U15 AD8608ARZ low noise op amp Filter op amp for Input 6 to Input 7 U16 FT245BL USB to parallel FIFO interface USB to parallel communications interface U17 PIC16LF877-04/PT microcontroller Parallel to SPI/I2C communications interface U18 AT93C46-10SU-2.7 1 kb serial EEPROM USB vendor ID and product ID memory U19 ADP3336ARMZ low dropout voltage regulator Analog supply voltage regulator U20 ADP3339AKCZ low dropout voltage regulator Digital supply voltage regulator U21 ADM811RARTZ logic low reset output Master reset generator U22 AD8608ARZ low noise op amp Microphone balanced-to-unbalanced converter LK29 ASEP3JL-ND programmable oscillator Active 12.288 MHz oscillator

Detailed IC Descriptions

U1—ADAU144x SigmaDSP Main audio signal processor and connectivity hub in the system. It includes nine serial input ports and nine serial output ports, with a total I/O capability of 24 serial audio channels. In addi-tion, two pins are designated as S/PDIF input/output ports. Inside the DSP are eight asynchronous sample rate converters, each capable of using any available clock domain as an output sample rate. The SigmaDSP core runs at 172 MHz and can be programmed via USB by the SigmaStudio programming tool.

U2—24AA256-I/ST 256 kb Serial EEPROM

Self-boot memory. Has enough memory to store an entire pro-gram, including program RAM, parameter RAM, and register settings. The ADAU144x can optionally boot from this memory on power-up, reducing the need for a system microcontroller.

U3—AD1938 Audio Codec A four-ADC, eight-DAC audio codec that allows connection of analog audio signals to the board. The U3 handles Input 0 to Input 3 and Output 0 to Output 7. It is capable of running synchronously to the ADAU144x or using its own crystal oscil-lator circuit. Its serial ports can also act as either master or slave.

U4—AD1938 Audio Codec

A four-ADC, eight-DAC audio codec that allows connection of analog audio signals to the board. The U4 handles Input 4 to Input 7 and Output 8 to Output 15. It is capable of running syn-chronously to the ADAU144x or using its own crystal oscillator circuit. Its serial ports can also act as either master or slave.

U5—TOTX141P 15 Mbps Optical Transmitter

Optical transmitter for S/PDIF signals coming from the SPDIFO pin of the ADAU144x. It is always active.

U6—TORX147L 15 Mbps Optical Receiver Optical receiver for S/PDIF signals, which are then routed to the SPDIFI pin of the ADAU144x. It is selected by putting the S3 switch into the left position (opposite the RCA label on the silkscreen).

U7—SC937-02 110 Ω AES/EBU Transformer

Transformer that conditions the S/PDIF output signal from the SPDIFO pin on the ADAU144x and prepares it for output on Connector J2, the electrical S/PDIF output jack.

U8—AD8608ARZ Low Noise Op Amp Operational amplifier used to actively filter the analog outputs of the AD1938 codecs. The U8 handles Output 0 to Output 3.


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U9—AD8608ARZ Low Noise Op Amp

Operational amplifier used to actively filter the analog outputs of the AD1938 codecs. The U9 handles Output 4 to Output 7.


Operational amplifier used to actively filter the analog outputs of the AD1938 codecs. The U10 handles Output 8 to Output 11.

U11—AD8608ARZ Low Noise Op Amp Operational amplifier used to actively filter the analog outputs of the AD1938 codecs. The U11 handles Output 12 to Output 15.

U12—AD8608ARZ Low Noise Op Amp Operational amplifier used to actively filter the analog inputs of the AD1938 codecs. The U12 handles Input 0 to Input 1.

U13—AD8608ARZ Low Noise Op Amp Operational amplifier used to actively filter the analog inputs of the AD1938 codecs. The U13 handles Input 2 to Input 3.


Operational amplifier used to actively filter the analog inputs to the AD1938 codecs. The U14 handles Input 4 to Input 5.


Operational amplifier used to actively filter the analog inputs of the AD1938 codecs. The U15 handles Input 6 to Input 7.

U16—FT245BL USB to Parallel FIFO Interface Single-chip USB used to parallel the FIFO bidirectional data transfer interface. It enables communication between the ADAU144x and the SigmaStudio programming tool via the PIC16LF877 microcontroller.

Note that in the current revision of the board, this device is disabled. The evaluation kit includes the EVAL-ADUSB2EBZ to be used as a communication interface.

U17—PIC16LF877-04/PT Microcontroller

U17 is a microcontroller that serves as a parallel FIFO to the SPI or I2C bidirectional communications interface. It enables communication between the ADAU144x and the SigmaStudio programming tool via the FT245BL.

Note that in the current revision of the board, this device is disabled. The evaluation kit includes the EVAL-ADUSB2EBZ to be used as a communication interface.

U18—AT93C46-10SU-2.7 1 kb Serial EEPROM USB device identification memory that contains the USB vendor ID and product ID numbers, allowing the correct driver to be chosen and enabling communications to the USB port of the PC.

U19—ADP3336ARMZ Low Dropout Voltage Regulator U19 is the analog supply voltage regulator; it regulates the dc power supply to a 3.3 V analog supply.

U20—ADP3339AKCZ Low Dropout Voltage Regulator Digital supply voltage regulator; it regulates the dc power supply to a 3.3 V digital supply.

U21—ADM811RARTZ Logic Low Reset Output

Debounced reset signal generator that acts as a master reset for the board.


Operational amplifier used to take a balanced analog microphone input signal and convert it to an unbalanced signal.

LK29—ASEP3JL-ND Programmable Oscillator An active oscillator that generates a clock signal at 12.288 MHz; it is useful for simulating an external master clock source in the system.


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CRYSTAL RESONATORS

Y1

Y5

Y4

Y2 Y3

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Figure 40. Crystal Resonator Layout

Table 3. Crystal Resonator Descriptions Reference Name Description Y1 DSP crystal 12.288 MHz crystal for the ADAU144x Y2 Codec 1 crystal 12.288 MHz crystal for the AD1938 Codec 1 Y3 Codec 2 crystal 12.288 MHz crystal for the AD1938 Codec 2 Y4 Microcontroller crystal 6.000 MHz crystal for the PIC16LF877 microcontroller Y5 USB interface crystal 10.000 MHz crystal for the FT245BL USB interface


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TRANSISTORS

Q1

Q2

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Figure 41. Transistor Layout

Table 4. Transistor Descriptions Reference Name Description Q1 Voltage regulator transistor Darlington PNP transistor. Acts as a pass transistor for the DVDD supply. Q2 Microcontroller JTAG reset transistor Reset transistor. Required component of the JTAG microcontroller programming circuit.


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LINKS

25 26 10

27

24

86 18 17

7

9

12

23

14

19 20 21 22

1 2 3 4 28

5 13 11

15 16

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Figure 42. Link Layout


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Table 5. Link Descriptions Reference Functional Name Description LK1 Clock select, crystal oscillator circuit LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK1

connects the ADAU144x to its crystal oscillator circuit. LK2 Clock select, BNC LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK2

connects the ADAU144x to a master clock signal input on the SMA input header, J3. LK3 Clock select, external clock input LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK3

connects the ADAU144x to an external MCLK signal from the multipurpose pin interface, J20.

LK4 Clock select, FPGA board LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK4 connects the ADAU144x to an external MCLK signal coming from header, J23.

LK5 DVDD regulator circuit enable Connects a regulated DVDD supply from the collector of the pass transistor, Q1, to the ADAU144x.

LK6 Codec 1 master/slave Places the Codec 1 serial ports in either master or slave mode, which are marked by M or S on the silkscreen, respectively.

LK7 Codec 1 clock select Connects or disconnects Codec 1 from its crystal oscillator circuit. When discon-nected, the codec receives a master clock signal from the ADAU144x.

LK8 Codec 2 master/slave Places the Codec 2 serial ports in either master or slave mode, which are marked by M or S on the silkscreen, respectively.

LK9 Codec 2 clock select Connects or disconnects Codec 2 from its crystal oscillator circuit. When discon-nected, the codec receives a master clock signal from the ADAU144x.

LK10 Multipurpose board supply select Selects either a 3.3 V (DVDD) or 5 V supply for the optional external multipurpose board, which attaches to the J20 header.

LK11 AVDD enable Connects the AVDD supply to the ADAU144x. LK12 PVDD enable Connects the PVDD supply to the ADAU144x. LK13 IOVDD enable Connects the IOVDD supply to the ADAU144x. LK14 Microphone input select Allows the microphone to be input to Codec 2. By default, the jumper should be set

on LINE, which enables both channels on the J15 input jack. However, when set to MIC, the left channel of J15 is replaced by the microphone signal on J25.

LK15 EEPROM SCL connect Connects the SCL line of the self-boot EEPROM U2 to the ADAU144x. The jumper must be connected to program and read from the EEPROM.

LK16 EEPROM SDA connect Connects the SDA line of the self-boot EEPROM U2 to the ADAU144x. The jumper must be connected to program and read from the EEPROM.

LK17 Op amp reference select, VREF LK17 and LK18 select the reference level for the active filters. Connecting LK17 selects a OPVDD/2 reference from a voltage divider on the OPVDD supply.

LK18 Op amp reference select, FILT LK17 and LK18 select the reference level for the active filters. Connecting LK18 selects a reference output directly from the AD1938 codec.

LK19 Op amp supply select, 5 V LK19 to LK22 select the supply for the filter operational amplifiers. LK19 connects a 5 V supply.

LK20 Op amp supply select, DVDD LK19 to LK22 select the supply for the filter operational amplifiers. LK20 connects the op amps to the DVDD supply.

LK21 Op amp supply select, AVDD LK19 to LK22 select the supply for the filter operational amplifiers. LK21 connects the op amps to the AVDD supply.

LK22 Op amp supply select, GND LK19 to LK22 select the supply for the filter operational amplifiers. LK22 disables the op amps by connecting their supplies to ground.

LK23 Futures Connects a pin on the microcontroller, which is not yet implemented. LK24 Communication active signal output Connects the communications active signal to the multipurpose pin interface header, J20. LK25 Codec 1 external SPI latch connect Connects the latch signal for Codec 1 to the J18 and J19 external communications

headers, allowing the codec to be programmed independently. When using the Aardvark or Beagle communications interface in I2C mode, the jumper must be disconnected.

LK26 Codec 2 external SPI latch connect Connects the latch signal for Codec 1 to the external communications headers (J18 and J19) allowing the codec to be programmed independently. When using the Aardvark or Beagle communications interface in I2C mode, the jumper must be disconnected.


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Reference Functional Name Description LK27 Microcontroller communication mode select Selects either I2C or SPI communication mode for the microcontroller; however, only

I2C is supported by the firmware on the EVAL-ADAU144xEB. To communicate with the ADAU144x in I2C mode, connect an external I2C programmer to J19.

LK28 Clock select, active oscillator LK1, LK2, LK3, LK4, and LK28 select the master clock input to the ADAU144x. LK28 selects the ASEP3JL-ND programmable oscillator as the MCLK source.

SWITCHES

S4

S2

S3

S1S7

S6

0836

3-04

3

Figure 43. Switch Layout


Rev. 0 | of 44

Table 6. Switch Descriptions Reference Functional Name Description S1 S/PDIF input format select Selects between the optical or electrical S/PDIF receiver input. Note that both

transmitters are active at all times. When the switch is to the left, the optical receiver is enabled. When to the right, the electrical receiver is enabled.

S2 ADAU144x mode switch Sets multiple mode pins on the ADAU144x, including PLL mode, CLK mode, self-boot, and address. For more information on these particular modes, refer to the ADAU1442/ADAU1445/ADAU1446 datasheet. For each switch, the right position (the on position) corresponds to a Logic 0. The left position corresponds to a Logic 1.

S3 Master reset Triggers a single reset pulse from reset generator U21, and resets all major ICs on the board.

S4 Aardvark communication format select Selects between I2C and SPI mode for the Aardvark communication interface. When the switch is in the left position, I2C communications are enabled. When to the right, SPI communications are enabled.

S6 Codec Enable 1 Enables communication between the ADAU144x and the AD1938 Codec 1. When the switches are in the on position (up), communications are enabled, and signals travel freely between the two ICs. When in the off position (down), the signals are blocked. To use the J21, J22, and J23 headers to input audio data to the ADAU144x directly, make sure these switches are in the off position.

S7 Codec Enable 2 Enables communication between the ADAU144x and the AD1938 Codec 2. When the switches are in the on position (up), communications are enabled, and signals travel freely between the two ICs. When the switches are in the off position (down), the signals are blocked. To use the J21, J22, and J23 headers to input audio data to the ADAU144x directly, make sure these switches are in the off position.


Rev. 0 | of 44

CONNECTORS AND JACKS

J24

J13

J14

J15

J4

J5

J6

J7

J8

J9

J10

J11

J25

J12

J21

J22

J23

J2

J1

J20

J16

J17

J3

J19 J18

0836

3-04

4

Figure 44. Connectors and Jacks Layout


Rev. 0 | of 44

Table 7. Connector and Jack Descriptions Reference Functional Name Description J1 S/PDIF electrical coax input jack Electrical input jack for the S/PDIF signals. To be active, it must first be selected with

Switch S1. The signal input on this jack is accessible at the SPDIFI pin on the ADAU144x. J2 S/PDIF electrical coax output jack Electrical output jack for S/PDIF signals. This jack always needs to be active; it outputs the

signal directly from the SPDIFO jack of the ADAU144x. J3 Master clock input SMA receptacle Input jack for external master clock signals to the ADAU144x. It is selected by connecting

the jumper on LK2. J4 Analog Audio Output 0/

Analog Audio Output1 Stereo audio output from the AD1938 Codec 1, Channel 0 and Channel 1.

J5 Analog Audio Output 2/ Analog Audio Output 3

Stereo audio output from AD1938 Codec 1, Channel 2 and Channel 3.













J12 Analog Audio Input 0/ Analog Audio Input 1

Stereo audio input to AD1938 Codec 1, Channel 0 and Channel 1.







J16 Microcontroller programming header

Connects directly to the programming port on the PIC16LF877 microcontroller.

J17 USB connector Connects the EVAL-ADAU144xEBZ board to the USB port of a PC. J18 Aardvark programming header Allows communication via an Aardvark communication interface instead of the USB

connector. An EVAL-ADUSB2EBZ (also known as USBi) can be connected here, as well. When J18 is used, the USB connector of the board, J17, should be disconnected from the USB port of the PC.

J19 Beagle header Allows communication monitoring via a Beagle sniffer communication interface. J20 Multipurpose pin interface Connects to the included external GPIO daughter board, which allows control of the

ADAU144x via its MP pins. The GPIO board has several forms of interface circuitry, including potentiometers, pushbuttons, and LEDs.

J21 ADAU144x Interface Connector 1 Header that allows direct access to many of the ADAU144x pins. For more information, see Figure 58.

J22 ADAU144x Interface Connector 2 Header that allows direct access to many of the ADAU144x pins. For more information, see the schematic in Figure 58.

J23 ADAU144x Interface Connector 3 Header that allows direct access to many of the ADAU144x pins. For more information, see the schematic in Figure 58.

J24 Coaxial 5 V power jack Connector for a standard power supply. The supply should be between 5 V and 6 V, sourcing at least 1.5 A, and have a tip positive polarity.

J25 Microphone input jack Mono differential microphone input.


Rev. 0 | of 44

CIRCUIT SCHEMATICS ADAU144x SigmaDSP

4D

4PG

D

0E

4D

8D

7D

6D

5D

3D

2D

1DD

0D

8D

7D

5D

3D

2D

9AG

D

8D

7D

6D

5D

3D

2D

1DD

U1ADAU1442

C21

12345678

11 12

2

C216

TP2

C233

4 F

[5]

[5]

15 LRCLK012 BCLK0

10 LRCLK19 BCLK1

7 LRCLK26 BCLK2

4 LRCLK33 BCLK3

97 LRCLK496 BCLK4

93 LRCLK592 BCLK5

86 LRCLK685 BCLK6

82 LRCLK781 BCLK7

78 LRCLK874 BCLK8

71 LRCLK970 BCLK9

68 LRCLK1067 BCLK10

65 LRCLK1164 BCLK11

11 SDATA_IN08 SDATA_IN15 SDATA_IN2

99 SDATA_IN395 SDATA_IN491

SDATA_IN584 SDATA_IN680 SDATA_IN773 SDATA_IN8

46 SPDIFI

47 SPDIFO

20ADDR024 ADDR1/CDATA

21 CLATCH22 SCL/CCLK23 SDA/COUT

4PV

D

98SDATA_OUT094SDATA_OUT190SDATA_OUT283SDATA_OUT379SDATA_OUT472SDATA_OUT569SDATA_OUT666SDATA_OUT761SDATA_OUT8

58MP0/ADC057MP1/ADC1 56MP2/ADC255MP3/ADC336MP435MP534MP633MP719MP818MP917

MP10 16MP11

28 SELFBOOT

60PLL0 59PLL1

32PLL2

30CLKMODE0 29CLKMODE1

31RSVD

54RESET

42XTALI 41XTALO

53CLKOUT

43PLL_FILT

5N

4VDRIV

8AVD

9IO

DVD

7IO

DVD

3IO

DVD

2IO

DVD

9IO

DVD

7IO

DVD

4IO

DVD

2IO

DVD

10

DVD

7DVD

5DVD

0DVD

7DVD

5DVD

4N

8G

ND

6G

ND

2G

ND

1G

ND

8G

ND

6G

ND

3G

ND

1G

ND

C7

0.10µF

C8

0.10µF

C9

0.10µF

C10

0.10µF

C11

0.10µF

C12

0.10µF

C13

0.10µF

C14

0.10µF

+

C15

10uF

C1

0.10µF

C2

0.10µF

C3

0.10µF

C4

0.10µF

C5

0.10µF

C6

0.10µF

+

C16

10uF

R5

100r

R6

1k50

Y112.288 MHz

C20

22pF

22pF

LK1

LK3

LK2 J3

R7

OPEN

R8

100k

R9

OPEN

C17OPEN

C2333nF

C241n8F

12345678 9

10111213141516

S2

SW8DIP

R10 10k0

B

E C

Q1NJT4030PT3G

R111k00

LK5

R154

10k0

LK4

C206

100nF

+

C207

10uF C208

100nF

+

C209

10uF

LK LK

LK13

R16 10k0

L15

100nFC217

100nF

TP1

TP3

TP4

TP5

TP6 TP8TP7

+10uF

L3

C23

100n

OE

GNDOUTPUT

VDDLK29

12.288MHz programmable

LK28

R192

49R9

R191

10k0

DVDD

DVDD

DVDD

DVDD

DVDD

PVDD

PVDDDVDD

AVDD

[2,5,6]RESET

[2,5]CLKOUT

[2,5] LRCLK0[2,5] BCLK0

[5] LRCLK1[5] BCLK1

[5] LRCLK2[5] BCLK2

[2,5] LRCLK3[2,5] BCLK3

[2,5] SDATA_IN0[2,5] SDATA_IN1[2,5] SDATA_IN2[2,5] SDATA_IN3

[2,5]SDATA_OUT0[2,5]SDATA_OUT1[2,5]SDATA_OUT2[2,5]SDATA_OUT3[2,5]SDATA_OUT4[2,5]SDATA_OUT5[2,5]SDATA_OUT6[2,5]SDATA_OUT7

[5]MP0[5]MP1[5]MP2[5]MP3[5]MP4[5]MP5[5]MP6[5]MP7[5]MP8[5]MP9[5]MP10[5]MP11

MCLK_EXT

[2,5,6] CCLK/SCL[2,5,6] COUT/SDA

[1,5,6] SELFBOOT[1,5] ADDR0

[1,2,5,6] CDATA/ADDR1

[1,5,6] SELFBOOT

[5,6] CLATCH_1442[1,2,5,6] CDATA/ADDR1

[1,5] ADDR0

[5]SDATA_OUT8

[5] SDATA_IN4[5] SDATA_IN5[5] SDATA_IN6[5] SDATA_IN7[5] SDATA_IN8

[2,5] LRCLK4[2,5] BCLK4

[5] LRCLK5[5] BCLK5

[5] LRCLK6[5] BCLK6

[5] LRCLK7[5] BCLK7

[5] LRCLK8[5] BCLK8

[2,5] LRCLK9[2,5] BCLK9

[5] LRCLK10[5] BCLK10

[5] LRCLK11[5] BCLK11

[5]CLKMODE1[5]CLKMODE0[5]PLL2[5]PLL1[5]PLL0

[5]RSVD

FPGA_CLK

[5] SPDIFI

[5] SPDIFO

[1]PVDD_CONNECT

[1]PVDD_CONNECT

DVDD

0836

3-04

5

Figure 45. ADAU144x Circuit Schematic



Rev. 0 | of 44

S/PDIF TRANSMITTER AND RECEIVER

DVDD

46SPDIFI

47 SPDIFO

12

3S1

SW-SPDT-C

L2

J1

C18 10nF

R275r

R110k0

4 SHLD2

5 SHLD1

2 DGND1

3DVDD

1OUT

U6TORX147L

J2

C19100nF

L1

R4107r

R3

243r

1

4

5

8

2

6

U7

TRAFFO-SC937-02

5 CASE2

4 CASE1

1 DGND

2

3INPUT

U5TOTX141P

C22

100nF

C21510nF

DVDD

DVDD

HI

LO

[5] SPDIFI

[5] SPDIFO

0836

3-04

6

Figure 46. S/PDIF Transmitter and Receiver Circuit Schematics

SELF-BOOT EEPROM

22 SCL/CCLK23 SDA/COUT

1A0

2A1

3A2

4GND

8VCC

7WP

6SCL

5SDA

U2

E2PROM

LK15

LK16

C232

100nF

DVDD

0836

3-04

7

Figure 47. Self-Boot EEPROM Circuit Schematic


Rev. 0 | of 44

AD1938 AUDIO CODECS

+

C25

100nF

C26

100nF

C27

100nF

C28

100nFC29

100nF

+

C212

10uF

C213

10uF

TP9DVDD AVDD

A BLK6

R14 OPEN

R15 OPEN

R16 OPEN

R17 OPEN

R1810k0

R1910k0

R2010k0

R2110k0

DVDD

[1,2,5,6]RESET

[5,6] CLATCH_1938-1

[1,2,5,6] CCLK/SCL

[1,2,5,6] COUT/SDA

[1,2,5,6] CDATA/ADDR1

[1,5] LRCLK0[1,5] BCLK0

[1,5] LRCLK9[1,5] BCLK9[1,5] SDATA_IN1[1,5] SDATA_IN0

[1,5] SDATA_OUT0[1,5] SDATA_OUT1[1,5] SDATA_OUT2[1,5] SDATA_OUT3

123456789

10

20191817161514131211

S6SW10DIP

[3] IN0+[3] IN0-

[3] IN1+[3] IN1-

[3] IN2+[3] IN2-

[3] IN3+[3] IN3-

2MCLKI/XI 3MCLKO/XO

5AVD

D1

6OL3

7OR3

8OL4

9OR4

10PD/RST

11 DSDATA4

13DVD

D

14 DSDATA3

15 DSDATA2

16 DSDATA1

17 DBCLK

18 DLRCLK

19 ASDATA220 ASDATA1

21 ABCLK

22 ALRCLK

23 CDATA24 COUT26 CCLK27CLATCH

28OL1

29OR1

30OL2

31OR2

33AVD

D135FILTR

37AVD

D238CM

39 ADC1LP40 ADC1LN

41 ADC1RP42 ADC1RN

43 ADC2LP44 ADC2LN

45 ADC2RP46 ADC2RN

47LF

48AVD

D2

U3

AD1938

C345n6F

R12562r

C35390pF

AVDD

[4]OUT0

[4]OUT1

[4]OUT2

[4]OUT3

[4]OUT4

[4]OUT5

[4]OUT6

[4]OUT7

1AG

ND

4AG

ND

12DGND

25DGND

32AG

ND

34AG

ND

36AG

ND

TP10

C38

100nF

C39

100nF

C40

100nF

C41

100nFC42

100nF

+

C210

10uF

+

C211

10uF

TP11DVDD AVDD

10

11141516

1718

1920

2122

23242627

3940

4142

4344

4546

A BLK8

R24 OPEN

R25 OPEN

R26 OPEN

R27 OPEN

R2810k0

R2910k0

R3010k0

R3110k0

123456789

10

20191817161514131211

S7SW10DIP

DVDD

[3]IN4+[3] IN4-

[3]IN5+[3] IN5-

[3]IN6+[3] IN6-

[3]IN7+[3] IN7-

[1,2,5,6]RESET

[1,2,5,6] CCLK/SCL

[1,2,5,6] COUT/SDA

[1,2,5,6]CDATA/ADDR1

[1,5] BCLK3[1,5] LRCLK3

[1,5] BCLK4[1,5] LRCLK4[1,5] SDATA_OUT7[1,5] SDATA_OUT6[1,5] SDATA_OUT5[1,5] SDATA_OUT4

[1,5] SDATA_IN3[1,5] SDATA_IN2

[6] CLATCH_1938-2

R22562r

AVDD

[4]OUT8

[4]OUT9

[4]OUT10

[4]OUT11

[4]OUT12

[4]OUT13

[4]OUT14

[4]OUT15

1AG

ND

4AG

ND

5AVD

D1

6

7

8

9

PD/RST

DSDATA4

12DGND

13DVD

D

DSDATA3DSDATA2DSDATA1

DBCLKDLRCLK

ASDATA2ASDATA1

ABCLKALRCLK

CDATACOUT

25DGND

CCLKCLATCH

28

29

30

31

32AG

ND

33AVD

D134

AGND

35FILTR

36AG

ND

37AVD

D2

38CM

47LF

4 8AVD

D2

U4

AD1938

TP12

2MCLKI/XI 3MCLKO/XO

C475n6F

C48390pF

[1,2,5] CLKOUT

+

C43

10uF

C44

100nF

+

C45

10uF

C46

100nF

R23100r

Y312.288 MHz

C49

22pF

C50

22pF

ABLK9

FILTR_2

+

C30

10uF

C31

100nF

+

C32

10uF

C33

100nF

R13100r

Y212.288 MHz

C36

22pF

C37

22pF

ABLK7

[1,2,5] CLKOUT

[3]FILTR_1

0836

3-04

8

ADC1LPADC1LN

ADC1RPADC1RN

ADC2LPADC2LN

ADC2RPADC2RN

OL3

OR3

OL4

OR4

OL1

OR1

OL2

OR2

Figure 48. AD1938 Codecs Circuit Schematics




Rev. 0 | of 44

ANALOG AUDIO INPUTS

-+

1

65

L7

600Z R136

49k

9

6 54 1J1

4 STJA

CK

3.5S

MAL

L

TP19

+

C151

10u

F

+

C152

10u

F

C153

100n

F

R130

237r

R131

237r

C159

120p

F

R132

5k76

R133

5k76

R134

5k76

R135

5k76

131214

U14-

DAD

8608

9-

10+

8

U14-

CAD

8608

+

C160

10u

F

C161

100p

F

L8

600Z

C162

1n0F

NP0

C163

1n0F

NP0

C164

100p

F

R137

49k

9

TP20

TP45

[2]

IN5-

[2]

IN5+

[3]

VREF

[3]

VREF

+

C154

10u

F

+

C155

10u

F

C156

100p

F

+

C157

10u

F

2-

3+

1

U14-

AAD

8608

6-

5+

7

U14-

BAD

8608

R124

5k76

R125

5k76

R126

5k76

R127

5k76

C158

120p

F

R128

237r

R129

237r

C165

100p

F

C166

1n0F

NP0

C167

1n0F

NP0

C168

100n

F

[2]

IN4-

[2]

IN4+

[3]

VREF

[3]

VREF

+

C172

10u

F

+

C173

10u

F

L11

600Z

C174

100p

F

+

C175

10u

F

2-

3+

U15-

AAD

8608

-+7

U15-

BAD

8608

R138

5k76

R139

5k76

R140

5k76

R141

5k76

C176

120p

F

R142

237r

R143

237r

R149

5k76

+

C178

10u

F

C179

100p

F

L12

600Z

C183

100p

F

C184

1n0F

NP0

C185

1n0F

NP0

R150

49k

9

R151

49k

9

6 54 1J1

5 STJA

CK3.

5SM

ALL

ABLK14

TP21

TP22

[2]

IN6-

[2]

IN6+

[3]

VREF

[3]

VREF

[3]

VREF

[3]

VREF

[3]

MIC

_IN

-+-+8

+

C169

10u

F

+

C170

10u

F

C171

100n

F

R144

237r

R145

237r

C177

120p

F

R146

5k76

R147

5k76

R148

5k76

131214

U15-

DAD

8608

910U15-

CAD

8608

C180

1n0F

NP0

C181

1n0F

NP0

C182

100p

F

C186

100n

F

TP46

[2]

IN7-

[2]

IN7+

08363-049

Figure 49. Audio Input 0 to Audio Input 3 Circuit Schematics


Rev. 0 | of 44

-+

STJA

CK

3.5S

MALL

+

C151

10u

F

+

C152

10u

F

C153

100n

F

R130

237r

R131

237r

C159

120p

F

R132

5k76

R133

5k76

R134

5k76

R135

5k76

13-

12+

14

U14-

DAD

8608

9108

U14-

CAD

8608

+

C160

10u

F

C161

100p

F

L8

600Z

C162

1n0F

NP0

C163

1n0F

NP0

C164

100p

F

C168

100n

F

R137

49k

9

TP20

TP45

[2]

IN5-

[2]

IN5+

[3]

VREF

[3]

VREF

+

C154

10u

F

+

C155

10u

F

L7

600Z

C156

100p

F

+

C157

10u

F

2-

3+

1

U14-

AAD

8608

6-

5+

7

U14-

BAD

8608

R124

5k76

R125

5k76

R126

5k76

R127

5k76

C158

120p

F

R128

237r

R129

237r

C165

100p

F

C166

1n0F

NP0

C167

1n0F

NP0

R136

49k

9

6 54 1J1

4

TP19

[2]

IN4-

[2]

IN4+

[3]

VREF

[3]

VREF

2-

3+

1

+

C172

10u

F

+

C173

10u

F

L11

600Z

C174

100p

F

+

C175

10u

F

U15-

AAD

8608

6-

5+

7

U15-

BAD

8608

R138

5k76

R139

5k76

R140

5k76

R141

5k76

C176

120p

F

R142

237r

R143

237r

C183

100p

F

C184

1n0F

NP0

C185

1n0F

NP0

C186

100n

F

R150

49k

9

6 54 1J1

5 STJA

CK3.

5SM

ALL

ABLK14

TP21

[2]

IN6-

[2]

IN6+

[3]

VREF

[3]

VREF

[3]

MIC

_IN

+

C169

10u

F

+

C170

10u

F

C171

100n

F

R144

237r

R145

237r

C177

120p

F

R146

5k76

R147

5k76

R148

5k76

R149

5k76

13-

12+

14

U15-

DAD

8608

9-

10+

8

U15-

CAD

8608

+

C178

10u

F

C179

100p

F

L12

600Z

C180

1n0F

NP0

C181

1n0F

NP0

C182

100p

F

R151

49k

9

TP22

TP46

[2]

IN7-

[2]

IN7+

[3]

VREF

[3]

VREF

08363-050

Figure 50. Audio Input 4 to Audio Input 7 Circuit Schematics










Rev. 0 | of 44

Opamp VREF select Opamp Supply select Opamp supply bypassing

LK17

LK18

R18749k9

R18849k9

+C21910uF

LK19

LK20

LK22

+C22010uF

C221100nF

C222100nF

C223100nF

C224100nF

C225100nFLK21

TP13

TP14

+5VA

DVDD

AVDD

[3]VREF

[2]FILTR_1

[3,4]OPVDD

[3,4]OPVDD

[3,4]OPVDD

0836

3-05

1

Figure 51. Audio I/O Filter Supply Circuit Schematics

-

+

-

+

6

5

4

1J25

STJACK3.5SMALL

R16610k0

R16710k0

C197100nF

C214

100nF

[3,4]OPVDD

2

31

U22-A

AD8606

R189

237r

R190

237r

6

57

U22-B

AD86064

V-

8V+

U22-CAD8606

[3] VREF[3]MIC_IN

[3,4]OPVDD

0836

3-05

2

Figure 52. Microphone Input Circuit Schematic




Rev. 0 | of 44

ANALOG AUDIO OUTPUTS

J

14

AD

8608

C59

470p

F

+

C60

47u

F16V

R40

49k

9

R41

604r

C61

3n3F

R42

4k75

C62

150p

F

9-

10

+8

U8-C

AD

8608

R43

4k75

R44

4k75

13

-

12

+U

8-D

C63

150p

F

R45

4k75

C64

3n3F

R46

604r

R47

49k

9

+

C65

47u

F16V

C66

470p

F

6 54

51

STJA

CK

3.5

SM

ALL

TP25

TP26

C51

470p

F

+

C53

47u

F16V

R35

49k

9

R34

604r

C54

3n3F

R32

4k75

C52

150p

F

2-

3+

1

U8-A

AD

8608

R33

4k75

R37

4k75

6-

5+

7

U8-B

AD

8608

C56

150p

F

R36

4k75

C58

3n3F

R38

604r

R39

49k

9

+

C57

47u

F16V

C55

470p

F

6 54

41

STJA

CK

3.5

SM

ALL

TP23

TP24 TP40

[2]

OU

T0

[2]

OU

T1

[2]

OU

T2

[2]

OU

T3

08363-053

Figure 53. Audio Output 0 to Audio Output 3 Circuit Schematics






Rev. 0 | of 44

54

J1

7

C67

470p

F

+

C68

47u

F16V

R48

49k

9

R49

604r

C69

3n3F

R50

4k75

C70

150p

F

2-

3+

1

U9-A

AD

8608

R51

4k75

R52

4k75

6-

5+

7

U9-B

AD

8608

C71

150p

F

R53

4k75

C72

3n3F

R54

604r

R55

49k

9

+

C73

47u

F16V

C74

470p

F

6

6

STJA

CK

3.5

SM

ALL

TP27

TP28

TP39

[2]

OU

T4

[2]

OU

T5

C75

470p

F

+

C76

47u

F16V

R56

49k

9

R57

604r

C77

3n3F

R58

4k75

C78

150p

F

9-

10

+8

U9-C

AD

8608

R59

4k75

R60

4k75

13

-

12

+14

U9-D

AD

8608

C79

150p

F

R61

4k75

C80

3n3F

R62

604r

R63

49k

9

+

C81

47u

F16V

C82

470p

F

6 54

J1

STJA

CK

3.5

SM

ALL

TP29

TP30

[2]

OU

T6

[2]

OU

T7

08363-054







Rev. 0 | of 44

+

C83

470p

F

+

C84

47uF

16V

R64

49k9

R65

604r

C85

3n3F

R66

4k75

C86

150p

F

2-

3+

1

U10-

A

AD

8608

R67

4k75

R68

4k75

6-

5+

7

U10-

B

AD

8608

C87

150p

F

R69

4k75

C88

3n3F

R70

604r

R71

49k9

+

C89

47uF

16V

C90

470p

F

6 54 1

TP31

TP32 TP41

[2]

OU

T8

[2]

OU

T9

16V

9

C92

47uF

R72

49k

9

R73

604r

C93

3n3F

C96

3n3F

R78

604r

R79

49k

9

+

C97

47uF

16V

6 54

J1

STJA

CK

3.5

SM

ALL

TP33

TP34

8J

STJA

CK

3.5

SM

ALL

C91

470p

F

R74

4k75

C94

150p

F

9-

10

+8

U10-

C

AD

8608

R75

4k75

R76

4k75

13

-

12

+14

U10-

D

AD

8608

C95

150p

F

R77

4k75

C98

470p

F

[2]

OU

T10

[2]

OU

T11

08363-055







Rev. 0 | of 44

C103

150p

F

-+

1J

C99

470p

F

+

C100

47u

F16V

R80

49k

9

R81

604r

C101

3n3F

R82

4k75

C102

150p

F

2-

3+

1U

11-

A

AD

8608

R83

4k75

R84

4k75

6-

5+

7U

11-

B

AD

8608

R85

4k75

C104

3n3F

R86

604r

R87

49k

9

+

C105

47u

F16V

C106

470p

F

6 54

01

STJA

CK

3.5

SM

ALL

TP35

TP36 T

P42

[2]

OU

T12

[2]

OU

T13

C107

470p

F

+

C108

47u

F16V

R88

49k

9

R89

604r

C109

3n3F

R90

4k75

C110

150p

F

9-

10

+8

U11-

C

AD

8608

R91

4k75

R92

4k75

13

12

14

U11-

D

AD

8608

C111

150p

F

R93

4k75

C112

3n3F

R94

604r

R95

49k

9

+

C113

47u

F16V

C114

470p

F

6 54

11J

1

STJA

CK

3.5

SM

ALL

TP37

TP38

[2]

OU

T14

[2]

OU

T15

Opam

psu

pply

bypass

ing

C226

100n

FC

227

100n

FC

228

100n

FC

229

100n

F

[3]

OPVD

D

08363-056







Rev. 0 | of 44

EXTERNAL CONNECTORS

R171

100r

R172

100r

R173

100r

R174

100r

R175

100r

R176

100r

R177

100r

R178

100rR179

100r

R180

100r

R181

100r

R182

100r

1 2 3 4 5 6 12345678

J20-50

J20-49

J20-48

J20-47

J20-46

J20-45

J20-44

J20-43

J20-42

J20-41

J20-40

J20-39

J20-38

J20-37

J20-36

J20-35

J20-34

J20-33

J20-32

J20-31

J20-30

J20-29

J20-28

J20-27

J20-26

J20-25

J20-24

J20-23

J20-22

J20-21

J20-20

J20-19

J20-18

J20-17

J20-16

J20-15

J20-14

J20-13

J20-12

J20-11

J20-10

J20-9

J20-8

J20-7

J20-6

J20-5

J20-4

J20-3

J20-2

J20-1

LK24

LK23

R170200r

D4

LED

YELLOWComms Active

TP136

[1,5,6]SELFBOOT

[6]SPI/I2C

[6]FUTURE0

[6]COMMS_ACTIVE

[1,2,5,6]COUT/SDA

[2,6]CLATCH_1938-1

[1,5,6]CLATCH_1442


[1,2,5,6]CCLK/SCL

[1,2,5,6]RESET

[1]MCLK_EXT

[1,2,5]CLKOUT

[1,5]MP0

[1,5]MP1

[1,5]MP2

[1,5]MP3

[1,5]MP4

[1,5]MP5

[1,5]MP6

[1,5]MP7

[1,5]MP8

[1,5]MP9

[1,5]MP10

[1,5]MP11

A BLK10

R183 1M00 R184 1M00

DVDD DVDD

DVDD+5V

0836

3-05

7

Figure 57. Multipurpose Pin Interface Schematic


Rev. 0 | of 44

TP130

TP131

J21-1

J21-2

J21-3

J21-4

J21-5

J21-6

J21-7

J21-8

J21-9

J21-10

J21-11

J21-12

J21-13

J21-14

J21-15

J21-16

J21-17

J21-18

J21-19

J21-20

J21-21

J21-22

J21-23

J21-24

J21-25

J21-26

J21-27

J21-28

J21-29

J21-30

J21-31

J21-32

J21-33

J21-34

J21-35

J21-36

J21-37

J21-38

J21-39

J21-40

J21-41

J21-42

J21-43

J21-44

J21-45

J21-46

J21-47

J21-48

J21-49

J21-50

TP59

TP60

TP61

TP62

TP63

TP64

TP65

TP66

TP67

TP68

TP69

TP70

TP71

TP72

TP73

TP74

TP75

TP76

TP77

TP78

TP79

[1,2]LRCLK0

[1,2]BCLK0

[1,2]SDATA_IN0

[1]LRCLK1

[1]BCLK1

[1,2]SDATA_IN1

[1]LRCLK2

[1]BCLK2

[1,2]SDATA_IN2

[1,2]LRCLK3

[1,2]BCLK3

[1,2]SDATA_IN3

[1,2]SDATA_OUT0

[1,2]LRCLK4

[1,2]BCLK4

[1]SDATA_IN4

[1,2]SDATA_OUT1

[1]LRCLK5

[1]BCLK5

[1]SDATA_IN5

[1,2]SDATA_OUT2

J22-1

J22-2

J22-3

J22-4

J22-5

J22-6

J22-7

J22-8

J22-9

J22-10

J22-11

J22-12

J22-13

J22-14

J22-15

J22-16

J22-17

J22-18

J22-19

J22-20

J22-21

J22-22

J22-23

J22-24

J22-25

J22-26

J22-27

J22-28

J22-29

J22-30

J22-31

J22-32

J22-33

J22-34

J22-35

J22-36

J22-37

J22-38

J22-39

J22-40

J22-41

J22-42

J22-43

J22-44

J22-45

J22-46

J22-47

J22-48

J22-49

J22-50

TP80

TP81

TP82

TP83

TP84

TP85

TP86

TP87

TP88

TP89

TP90

TP91

TP92

TP93

TP94

TP95

TP96

TP97

TP98

TP99

TP100

TP132

TP133

[1]BCLK6

[1]SDATA_IN6

[1,2]SDATA_OUT3

[1]LRCLK7

[1]BCLK7

[1]SDATA_IN7

[1,2]SDATA_OUT4

[1]LRCLK8

[1]BCLK8

[1]SDATA_IN8

[1,2]SDATA_OUT5

[1,2]LRCLK9

[1,2]BCLK9

[1,2]SDATA_OUT6

[1]LRCLK10

[1]BCLK10

[1,2]SDATA_OUT7

[1]LRCLK11

[1]BCLK11

[1]SDATA_OUT8

[1]LRCLK6 J23-1

J23-2

J23-3

J23-4

J23-5

J23-6

J23-7

J23-8

J23-9

J23-10

J23-11

J23-12

J23-13

J23-14

J23-15

J23-16

J23-17

J23-18

J23-19

TP101

TP102

TP103

TP104

TP105

TP106

TP107

TP108

TP109

TP110

[1,5]MP1

[1,5]MP2

[1,5]MP3

[1,5]MP4

[1,5]MP5

[1,5]MP6

[1,5]MP7

[1,5]MP8

[1,5]MP9

[1,5]MP0

J23-20

J23-21

J23-22

J23-23

J23-24

J23-25

J23-26

J23-27

J23-28

J23-29

J23-30

J23-31

J23-32

J23-33

J23-34

J23-35

J23-36

J23-37

J23-38

J23-39

J23-40

J23-41

J23-42

J23-43

J23-44

J23-45

J23-46

J23-47

J23-48

J23-49

J23-50

J23-51

J23-52

J23-53

J23-54

J23-55

J23-56

J23-57

J23-58

J23-59

J23-60

TP119

TP120

TP121

TP122

TP123

TP124

TP125

TP126

TP127

TP128

TP129

TP134

TP135

TP111

TP112

TP113

TP114

TP115

TP116

TP117

TP118

[1,5]MP10

[1,5]MP11

[1]PLL0

[1]PLL1

[1]PLL2

[1]CLKMODE0

[1]CLKMODE1

[1,5,6]SELFBOOT

[1]ADDR0


[1,5,6]CLATCH_1442

[1,2,5,6]CCLK/SCL

[1,2,5,6]COUT/SDA

[1]FPGA_CLK

[1]SPDIFI

[1]SPDIFO

[1,2,5]CLKOUT

[1,2,5,6]RESET

[1]RSVD

0836

3-05

8

Figure 58. ADAU144x Interface Connector Schematic


Rev. 0 | of 44

SW

-DPD

T-SLI

DE

Aardvark Header

Beagle Header

12

3 45

6

S4

1 23 45

109876

J18

HEADER10

1 23 45

109876

J19

HEADER10

LK25

LK26

[1,2,5,6] CCLK/SCL[1,2,5,6] COUT/SDA

[1,5,6] CLATCH_1442[1,2,5,6]CDATA/ADDR1

[2,5,6] CLATCH_1938-1

[2,6] CLATCH_1938-2

0836

3-05

9

Figure 59. Aardvark and Beagle I2C and SPI Communications Headers Circuit Schematics


Rev. 0 | of 44

USB CONTROL INTERFACE

22pF

1C

S2

CLK

3D

I4

DO

8VC

C6

NC

7N

C

5GND

U18

93C

46

R158

10k0

R159

2k00

+5V

1VC

C

2D

-

3D

+

4G

ND

5SH

6SH

J17

USB

R155

28r

R156

28r

R157

10k0

L13

600Z

C192

100nF

C198

22pF

C199

22pF

Y4

6M

Hz

+C201

10uF

+5V

3V3O

UT

USBD

PU

SBD

M

XTIN

RESET

RSTO

UT

XTO

UT

EEC

SEESK

EED

ATA

TEST

D0

D1

D2

D3

D4

D5

D6

D7

NO

TES

1. ALL

CO

MPO

NEN

TS I

N T

HIS

SCH

EM

ATI

C,

EXCEPT

TH

E T

EST

POIN

TS (

TPx)

, ARE N

OT

PO

PULA

TED

.WR

RD

TXE

RXF

SI/

WU

PW

REN

VCCIOVCCVCC

AVCC

GND

GND

AGND

FT245BL

6 78

2745

28

32 1 2

31

25

24

23

22

21

20

19

18

16

15

14

12

11

10

1326330

17

9

29

U16

C188

100nF

C189

100nF

C190

100nF

C191

100nF

R160

10k0

R161

475r

TP54

+5V

RESET

J16-5

J16-4

J16-3

J16-2

J16-1

C193

22pF

C194

R163

2k00

Y5

10M

Hz

R168

10k0

E

B

C

Q2

R169

2k00

BA

LK27

DVD

D

DVD

D

DVD

D

[1,2

,5,6

]

[1,5

]SELF

BO

OT

[5]

SPI/

I2C

L14DVD

D

R164

2k00

R165

2k00

TP47

TP48

TP49

TP50

TP51

TP52

C195

100nF

C196

100nF

+

C200

10uF

287

34331312

296

U17

D0

D1

D2

D3

D4

D5

D6

D7

RA0/A

N0

RA1/A

N1

RA2/A

N2/V

REF-

RA3/A

N3/V

REF+

RA4/T

OC

KI

RA5/A

N4/S

S+

OSC

1/C

LKIN

OSC

2/C

LKO

UT

MC

LR

RE0/A

N5

RE1/A

N6

RE2/A

N7

RC

0/C

LATC

H1

RC

1/C

LATC

H2

RC

2/C

LATC

H0

RC

3/S

CK

/SC

LR

C4/S

DI/

SD

AR

C5/S

DO

RC

6/T

XR

C7/R

X

RB0/I

NT

RB1

RB2

RB3

RB4/C

LATC

H3

RB5/C

LATC

H4

RB6

38

39

40

41 2 3 4 5

19

20

21

22

23

24

30

31

18

25

26

27

32

35

36

37

42

43

44

1

8 910

11

14

15

16

17

RB7

VDDVDD

NCNCNCNC

GNDGND

PIC

16F877

TP53

DVD

D

[1,5

,6]

CLA

TC

H_1442

[2,5

,6]

CLA

TC

H_1938-1

[1,2

,5,6

]C

DATA/A

DD

R1[1

,2,5

,6]

CO

UT/S

DA

[1,2

,5,6

]C

CLK

/SC

L

[5]

FU

TU

RE0

[5]

CO

MM

S_AC

TIV

E

[2,6

]C

LATC

H_1938-

2

08363-060

Figure 60. USB Control Interface Circuit Schematic


Rev. 0 | of 44

RESET GENERATOR

ADM811RARTZ-REEL7

S3

C187

100nF

R152100k

4VCC

3 MR 1GND

2RESET/RESET

U21

DVDD

[1,2,5,6]RESET

0836

3-06

1

Figure 61. Reset Generator Circuit Schematic

POWER SUPPLY

2

1SM

B15

T3G +

GN

3.3 V Regulated Supplies

DVDD = 3.3 V

AVDD = 3.3 V

3 IN2OUT

1D 4OUT

U20ADP3339AKCZ-3.3-R7

+

C20210uF

C20510uF

D1

MBR0530T1G

D

A15V

2

1

3J24

RAPC722X R153200r

D3BLUEAVDD

C203100nF

C204100nF

7 IN18 IN26 SD

4GND

1OUT1 2OUT2 3OUT3 5FB

U19

ADP3336ARMZ-REEL7

C218

10nF

R18578k7

R186140k

+

C23010uF

C231100nF

TP55 TP56

TP57

TP58

DVDD

AVDD

+5VA

0836

3-06

2

Figure 62. Voltage Regulator Circuit Schematic

http://www.analog.com/ADM811

http://www.analog.com/ADP3336



Rev. 0 | of 44

ORDERING INFORMATION BILL OF MATERIALS

Table 8. Bill of Materials (BOM) Qty. Reference Value Description Manufacturer Part No. Vendor Vendor No. 66 C1 to C14, C19,

C22, C25 to C29, C31, C33, C38 to C42, C44, C46, C118, C127, C135, C150, C153, C168, C171, C186 to C192, C195 to C197, C203, C204, C206, C208, C214, C216, C217, C221 to C229, C231, C232, C234

0.10 μF Multilayer ceramic, 50 V, X7R (0603)

Panasonic EC ECJ-1VB1H104K Digi-Key PCC2398CT-ND

16 C121, C122, C130, C131, C144, C145, C148, C149, C162, C163, C166, C167, C180, C181, C184, C185

1.0 nF Multilayer ceramic, 50 V, NP0 (0603)

Panasonic EC ECJ-1VC1H102J Digi-Key PCC2151CT-ND

1 C24 1.8 nF Multilayer ceramic, 50 V, NP0 (0603)

TDK Corporation C1608C0G1H182J Digi-Key 445-1296-1-ND

2 R8, R152 100 kΩ Chip resistor, 1%, 125 mW thick film (0603)

Panasonic EC ERJ-3EKF1003V Digi-Key P100KHCT-ND


100 pF Multilayer ceramic, 50 V, NP0 (0603)

Panasonic EC ECJ-1VC1H101J Digi-Key PCC101ACVCT-ND

15 R5, R13, R23, R171 to R182

100 Ω Chip resistor, 1%, 100 mW thick film (0603)

Panasonic EC ERJ-3EKF1000V Digi-Key P100HCT-ND

1 R4 107 Ω Chip resistor, 1%, 100 mW thick film (0603)


18 R1, R18 to R21, R28 to R31, R154, R157, R158, R160, R162, R166 to R168, R191

10.0 kΩ Chip resistor, 1%, 125 mW thick film (0603)

Panasonic EC ERJ-3EKF1002V Digi-Key P10.0KHCT-ND

3 C18, C215, C218

10 nF Multilayer ceramic, 50 V, X7R (0603)



Rev. 0 | of 44

Qty. Reference Value Description Manufacturer Part No. Vendor Vendor No. 43 C15, C16, C30,

C32, C43, C45, C116, C119, C120, C125, C128, C129, C133, C134, C136, C137, C139, C142, C151, C152, C154, C155, C157, C160, C169, C170, C172, C173, C175, C178, C200, C202, C205, C207, C209 to C213, C219, C220, C230, C233

10 μF Alum electrolytic capacitor FC, 105°C, SMD_B

Panasonic EC EEE-FC1C100R Digi-Key PCE3995CT-ND

8 C117, C126, C140, C141, C158, C159, C176, C177



1 R186 140 kΩ Chip resistor, 1%,100 mW thick film (0603)

Panasonic EC ERJ-3EKF1403V Digi-Key P140KHCT-ND




1 R11 1.00 kΩ Chip resistor, 1%, 125 mW thick film (0603)


1 R6 1.50 kΩ Chip resistor, 1%,100 mW thick film (0603)


1 D2 15 V TVS Zener 15 V, 600 W, SMB ON Semiconductor 1SMB15AT3G Digi-Key 1SMB15AT3GOSCT-ND

2 R170, R153 200 Ω Chip resistor, 1%,100 mW thick film (08603)


10 C20, C21, C36, C37, C49, C50, C193, C194, C198, C199



18 R101, R102, R108, R109, R114 to R117, R128 to R131, R142 to R145, R189, R190



1 R3 243 Ω Chip resistor, 1%,100 mW thick film (0603)


1 U2 256 kb I2C CMOS serial EEPROM Microchip 24AA256-I/ST Digi-Key 24AA256-I/ST-ND

2 R155, R156 28.0 Ω Chip resistor, 1%, 125 mW thick film (0603)

Panasonic EC ERJ-3EKF28R0V Digi-Key P28.0HCT-ND

5 R159, R163 to R165, R169

2.00 kΩ Chip resistor, 1%,100 mW thick film (0603)



Rev. 0 | of 44

Qty. Reference Value Description Manufacturer Part No. Vendor Vendor No. 16 C54, C58, C61,

C64, C69, C72, C77, C80, C85, C88, C93, C96, C101, C104, C109, C112

3.3 nF Multilayer ceramic, 50 V, X7R (0603)


1 C23 33 nF Multilayer ceramic, 50 V, X7R (0603)


2 C35, C48 390 pF Multilayer ceramic, 50 V, NP0 (0603)




Panasonic EC ECJ-1VC1H471J Digi-Key PCC2147CT-ND

1 R161 475 Ω Chip resistor, 1%, 125 mW thick film (0603)



47 μF Alum electrolytic capacitor, FC, 105°C, SMD_D

Panasonic EC EEE-FC1C470P Digi-Key PCE4000CT-ND

22 R35, R39, R40, R47, R48, R55, R56, R63, R64, R71, R72, R79, R80, R87, R88, R95, R136, R137, R150, R151, R187, R188



32 R32, R33, R36, R37, R42 to R45, R50 to R53, R58 to R61, R66 to R69, R74 to R77, R82 to R85, R90 to R93



2 C34, C47 5.6 nF Multilayer ceramic, 50 V, X7R (0603)


2 R12, R22 562 Ω Chip resistor, 1%, 125 mW thick film (0603)


16 R124 to R127, R132 to R135, R138 to R141, R146 to R149



16 R34, R38, R41, R46, R49, R54, R57, R62, R65, R70, R73, R78, R81, R86, R89, R94



1 R2 75.0 Ω Chip resistor, 1%, 100 mW thick film (0603)


1 R185 78.7 kΩ Chip resistor, 1%, 100 mW thick film (0603)


2 U3, U4 AD1938YSTZ Four-ADC, eight-DAC with PLL, 192 kHz, 24-bit CODEC

Analog Devices, Inc. AD1938YSTZ Analog Devices

AD1938YSTZ





Rev. 0 | of 44

Qty. Reference Value Description Manufacturer Part No. Vendor Vendor No. 1 U22 Low noise rail-to-rail

CMOS op amp Analog Devices AD8606ARZ Analog

Devices AD8606ARZ

8 U8 to U15 Low noise rail-to-rail CMOS op amp

Analog Devices AD8608ARZ Analog Devices

AD8608ARZ

1 U1 SigmaDSP Analog Devices ADAU144x Analog Devices

ADAU144x

1 U21 Microprocessor voltage supervisor, logic low reset output

Analog Devices ADM811RARTZ-REEL7 Analog Devices

ADM811RARTZ-REEL7

1 U19 Adjustable low dropout voltage regulator

Analog Devices ADP3336ARMZ-REEL7 Analog Devices

ADP3336ARMZ-REEL7

1 U20 High accuracy, low dropout, 3.3 V dc voltage regulator

Analog Devices ADP3339AKCZ-3.3-R7 Analog Devices

ADP3339AKCZ-3.3-R7

1 U18 1 kb (128 × 8 bits or 64 × 16 bits)

Serial EEPROM, 1 kB, 2.7 V Atmel AT93C46-10SU-2.7 Digi-Key AT93C46-10SU-2.7-ND

1 C17 Open Do not stuff N/A1 N/A1 N/A1 N/A1

1 J3 SMA receptacle straight PCB mount

Amp-RF Division 901-144-8RFX Digi-Key ARFX1231-ND

1 S4 DPDT slide DPDT slide switch vertical E-Switch EG2207 Digi-Key EG1940-ND

3 L1 to L3 Chip ferrite bead, 600 Ω @ 100 MHz

Steward HZ0805E601R-10 Digi-Key 240-2399-1-ND

1 U16 USB to parallel FIFO interface FTDI FT245BL Mouser Electronics

895-FT245BL

1 Q1 TRANS PNP, BIPO 3 A, 40 V, SOT-223

PNP Darlington transistor ON Semiconductor NJT4030PT3G Digi-Key NJT4030PT3GOSCT-ND

1 Y5 10.000 MHz Crystal 10.000 MHZ, SMT, 18 pF Citizen America Corp

HCM49-10.000MABJ-UT Digi-Key 300-8543-1-ND

3 Y1 to Y3 12.288 MHz Crystal 12.288 MHZ, SMT, 18 pF Citizen America Corp


1 Y4 6.000 MHz Crystal 6.000 MHZ, SMT, 18 pF Citizen America Corp


2 J18, J19 2 × 5 10-way shroud polarized header

3M N2510-6002RB Digi-Key MHC10K-ND

2 J21, J22 50-pin (2 rows × 25 columns)

50-pin header unshrouded, 0.10" dual row

Sullins Electronics Corp

PBC25DAAN Digi-Key S2011E-25-ND

1 J16 1 × 5 5-way unshrouded header single row


PBC05SAAN; also cut PBC36SAAN

Digi-Key S1011E-05-ND

1 J23 60-pin (2 rows × 30 columns)

60-pin header unshrouded, 0.10" dual row


PBC30DAAN Digi-Key S2011E-30-ND

21 LK1 to LK5, LK11 to LK13, LK15 to LK26, LK28

2-pin header unshrouded jumper, 0.10"; use shunt Tyco 881545-2


PBC02SAAN; or cut PBC36SAAN


7 LK6 to LK10, LK14, LK27

3-position SIP header Sullins PBC03SAAN; or cut PBC36SAAN


1 D3 Blue clear Blue clear, 25 millicandela, 470 nm (1206)

Lumex Opto SML-LX1206USBC-TR Digi-Key 67-1701-1-ND

1 D4 Yellow diffused Yellow clear, 6.0 millicandela, 585 nm (1206)

Lumex Opto SML-LX1206YC-TR Digi-Key 67-1358-1-ND

1 D1 Schottky Schottky 30 V, 0.5 A, SOD123 diode

On Semiconductor MBR0530T1G Digi-Key MBR0530T1GOSCT-ND

1 U17 8 kb × 14 MCU Flash 4 MHz, 8 kb × 14 TQFP44

Microchip Technology

PIC16LF877-04/PT Digi-Key PIC16LF877-04/PT-ND

13 J4 to J15, J25 Stereo mini jack, TH CUI, Inc. SJ-43514 Digi-Key CP-43514-ND

1 Q2 NPN general-purpose transistor ON Semiconductor MMBT3904LT1G Digi-Key MMBT3904LT1GOSCT-ND

1 R183 1.00 MΩ Resistor network bussed seven resistors

Bourns, Inc. 4606X-101-105LF Digi-Key 4606X-1-105LF-ND
















Rev. 0 | of 44

Qty. Reference Value Description Manufacturer Part No. Vendor Vendor No. 1 R10 10.0 Ω Resistor network

bussed seven resistors Bourns, Inc. 4608X-101-103LF Digi-Key 4608X-1-103LF-ND

1 R184 1.00 MΩ Resistor network bussed seven resistors

Bourns, Inc. 4608X-101-105LF Digi-Key 4608X-1-105LF-ND

10 R7, R9, R14 to R17, R24 to R27

Open Do not stuff

1 J202 50-pin 50-pin plug right angle DIN dual row

Hirose Electronic Co., Ltd

PCN10-50P-2.54DS(72) Digi-Key H11159-ND

2 J1, J2 RCA jack PCB TH mount right angle orange

Connect-Tech Products Corp.

CTP-021A-S-ORANGE Connect-Tech Products Corp.

CTP-021A-S-ORANGE

1 J24 Mini power jack, 0.08" right angle through hole

Switchcraft, Inc. RAPC722X Digi-Key SC1313-ND

1 U7 110 Ω AES/EBU transformer Scientific Conversion, Inc.

SC937-02 Scientific Conversion

SC937-02

1 S1 SPDT SPDT slide switch PC mount E-Switch EG1218 Digi-Key EG1903-ND

2 S6, S7 10-position 10-position tape seal DIP switch

CTS Corp 219-10LPST Digi-Key CT21910LPST-ND

1 S2 8× SPST eight-section SPST SMD switch raised act

CTS Corp 219-8LPST Digi-Key CT2198LPST-ND

1 S3 SPST-NO Tact switch 6 mm gull wing Tyco/Alcoswitch FSM6JSMA Digi-Key 450-1133-ND

1 U6 15 Mbps 15 Mbps fiber optic receiving module with shutter

Toshiba TORX147L(F,T) Digi-Key TORX147LFT-ND

1 U5 15 Mbps optical transmitter Toshiba TOTX141P(F,T) Digi-Key TOTX141PFT-ND

1 J17 USB 4-pin B-type receptacle Tyco Electronics/AMP

292304-1 Mouser Electronics

571-292304-1

1 LK29 12.288 MHz oscillator

ASEP series oscillator Abracon ASEP3JL-ND Digi-Key ASEP3JL-ND

1 R192 49.9 Ω Chip resistor, 1%, 100 mW thick film (0603)


4 6-32 thread size × 1/4" screw

Digi-Key H554-ND

4 6-32 thread size × 1/4" standoff

Digi-Key 1903CK-ND

17 Shunt Shunt LP Tyco 881545-2 Digi-Key A26242-ND 1 N/A means not applicable. 2 Install in top of board backwards.

ESD CAUTION


Rev. 0 | of 44

NOTES

Trademarks and registered trademarks are the property of their respective owners. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems.

©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG08363-0-4/10(0)

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