XR·2211FSK Dell1odulator/Tone Decoder

The XR-22ll is a monolithic phase-locked loop (PLL) system especially designed for data communications. It is particularlywell suited for FSK modem applications. It operates over a wide supply voltage range of 4.5 to 20V and a wide frequencyrange of 0.01 Hz to 300 kHz. It can accommodate analog signals between 2 mV and 3V, and can interface with conventionalDTL, TTL and ECL logic families. The circuit consists of a basic PLL for tracking an input signal within the pass band, aquadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation.External components are used to independently set center frequency, bandwidth, and output delay.

Power SupplyInput Signal LevelPower DissipationCeramic Package:Derate above TA = +25°C

Plastic Package:Derate above T A = +25° C

20V3Vrms

Wide Frequency RangeWide Supply Voltage RangeDTL/TTL/ECL Logic CompatibilityFSK Demodulation, with Carrier-DetectionWide Dynamic RangeAdjustable Tracking Range (± 1% to ±80%)Excellent Temp. Stability

0.01 Hz to 300 kHz4.5V to 20V

750 mW6mVtC625 mW

5.0mWtC

FSK DemodulationData SynchronizationTone DecodingFM DetectionCarrier Detection

Part NumberXR-22 1 1MXR-22llCNXR-22lICPXR-2211NXR-2211P

PackageCeramicCeramicPlasticCeramicPlastic

Operating Temperature-55°C to +125°CO°C to +75°CO°C to +75°C

_40°C to +85°C- 40°C to +85°C

1TIMINGCAPACITOR

J

LOOP.-OET.OUT.

REF.VOLTAGEOUT.

rLOCK 0OETECTOUTPUTS

L Q

ELECTRICAL CHARACTERISTICSTest Conditions: V+ = +12V, TA = +25°C, RO= 30 Kil, Co = 0.033 JlF. See Fig. 2 for component designation

XR-2211/2211M XR-2211CCHARACTERISTICS UNITS CONDITIONS

MIN. TYP. MAX. MIN. TYP. MAX.

GENERALSupply Voltage 4.5 20 4.5 20 VSupply Current 4 7 5 9 mA Ro L 10 Kil. See Fig. 4

OSCILLATOR SECTIONFrequency Accuracy ±1 ±3 ±1 % Deviation from fO = I/ROCOFrequency Stability Rl = 00Temperature ±20 ±50 ±20 ppmfC See Fig. 8.Power Supply 0.05 0.5 0.05 %fV V+ = 12 ± 1V. See Fig. 7.

0.2 0.2 %fV V+ = 5 ± 0.5V. See Fig. 7.Upper Frequency Limit 100 300 300 kHz RO = 8.2 Kil, Co = 400 pFLowest PracticalOperating Frequency 0.01 0.01 Hz RO = 2 Mil, Co = 50 JlF

Timing Resistor, RO See Fig. 5.Operating Range 5 2000 5 2000 KilRecommended Range 15 100 15 100 Kil See Fig. 7 and 8.

LOOP PHASE DETECTOR SECTIONPeak Output Current ±150 ±200 ±300 ±100 ±200 ±300 JlA Measured at Pin 11.Output Offset Current ±1 ±2 JlAOutput Impedance 1 1 MilMaximum Swing ±4 ±5 ±4 ±5 V Referenced to Pin 10.

QUADRATURE PHASE DETECTOR Measured at Pin 3.Peak Output Current 100 150 150 JlAOutput Impedance 1 1 MilMaximum Swing 11 11 Vpp

INPUT PREAMP SECTION Measured at Pin 2.Input Impedance 20 20 KilInput SignalVoltage Required to Cause Limiting 2 10 2 mV rms

VOLTAGE COMPARATOR SECTIONSInput Impedance 2 2 Mil Measured at Pins 3 and 8.Input Bias Current 100 100 nAVoltage Gain 55 70 55 70 dB RL = 5.1 KilOutput Voltage Low 300 300 mV Ie = 3 mAOutput Leakage Current .01 .01 JlA Vo = 12V

INTERNAL REFERENCEVoltage Level 4.9 5.3 5.7 4.75 5.3 5.85 V Measured at Pin 10.Output Impedance 100 100 il

Figure 1. Functional Block Diagram of a Tone and FSK DecodingSystem Using XR-22 I 1.

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SUPPLY VOLTAGE, V+ (VOLTS) 101Hz) lolHl1

Figure 4. Typical Supply Current vs Y+ Figure 5. YCO Frequency vs Timing Figure 6. YCO Frequency vs Timing(Logic Outputs Open Circuited). Resistor Capacitor

1.02

fo• ~ kHz.,0 I

6 :. V6R:;' 10RO U ~ 1'\.0 10K

1.01 :~ ~ )(~!! ./>- ./

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RO'50K~~0 1.00 >-.• 4:: V~ " ~(" ffi -~ :> 0.. 0." S 7 -::::::: 50K::; {V ::

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8 300K 0z '0.1 kHz0 .• 7 -10

4 8 8 10 12 14 18 18 20 22 24 -50 26 0 26 50 75 100 126V+CVOlTS) TEMPERATURE ("CI

Figure 7. Typical fO vs Power Supply Characteristics. Figure 8. Typical Center Frequency Drift vsTemperature

Signal Input (Pin 2): Signal is ac coupled to this terminal.The internal impedance at Pin 2 is 20 Kn. Recommendedinput signal level is in the range of 10 mVrms to 3 Vrms.

Quadrature Phase Detector Output (Pin 3): This is the high-impedance output of quadrature phase detector, and is inter-nally connected to the input of lock-detect voltage-comparator.In tone detection applications, Pin 3 is connected to groundthrough a parallel combination of RD and CD (See Fig. 2) toeliminate the chatter at lock-detect outputs. If the tone-detect section is not used, Pin 3 can be left open circuited.

Lock-Detect Output, Q (Pin 5): The output at Pin 5 is at"high" state when the PLL is out of lock and goes to "low"or conducting state when the PLL is locked. It is an open-collector type output and requires a pull-up resistor, RL, toV+ for proper operation. At "low" state, it can sink up to5 mA of load current.

Lock-Detect Complement, Q (Pin 6): The output at Pin 6 isthe logic complement of the lock-detect output at Pin 5.This output is also an open-collector type stage which cansink 5 mA of load current at low or "on" state.

FSK Data Output (Pin 7): This output is an open-collectorlogic stage which requires a pull-up resistor, RL, to V+ forproper operation. It can sink 5 mA of load current. Whendecoding FSK signals, FSK data output is at "high" or offstate for low input frequency; and at "low" or on state forhigh input frequency. If no input signal is present, the logicstate at Pin 7 is indeterminate.

FSK Comparator Input (Pin 8): This is the high-impedanceinput to the FSK voltage comparator. Normally, an FSK post-detection or data filter is connected between this terminal andthe PLL phase-detector output (Pin II). This data filter isformed by RF and CF of Fig. 2. The threshold voltage of thecomparator is set by the internal reference voltage, VR' avail-able at Pin 10.

Reference Voltage, YR (Pin 10): This pin is internally biasedat the reference voltage level, VR: VR = V+/2 - 650 mY.The dc voltage level at this pin forms an internal reference forthe voltage levels at pins 5, 8, II and 12. Pin 10 must be by-passed to ground with a 0.1 p.F capacitor, for proper operationof the circuit.

Loop Phase Detector Output (Pin 11): This terminal providesa high-impedance output for the loop phase-detector. ThePLL loop filter is formed by R I and C I connected to Pin II(See Fig. 2). With no input signal, or with no phase-errorwithin the PLL, the dc level at Pin II is very nearly equal toVR' The peak voltage swing available at the phase detectoroutput is equal to ±VR.

YCO Control Input (Pin 12): vca free-running frequencyis determined by external timing resistor, RO' connected fromthis terminal to ground. The vca free-running frequency,fO' is:

where Co is the timing capacitor across Pins 13 and 14. Foroptimum temperature stability, RO must be in the range of10 Kn to 100 Kn (See Fig. 8).

Th15 terminal is a low-impedance point, and is internallybiased at a dc level equal to YR' The maximum timing currentdrawn from Pin 12 must be limited to ~ 3 mA for properoperation of the circuit.

YCO Timing Capacitor (Pins 13 and 14): vca frequency isinversely proportional to the external timing capacitor, CO'connected across these terminals (See Fig. 5). Co must benon-polar, and in the range of 200 pF to 10 p.F.

VCO Frequency Adjustment: vca can be fine-tuned byconnecting a potentiometer, R X, in series with RO at Pin 12(See Fig. 9).

YCO Free-Running Frequency, fO: XR-2211 does not have aseparate vca output terminal. Instead, the vca ou tputsare internally connected to the phase-detector sections of thecircuit. However, for set-up or adjustment purposes, vcafree-running frequency can be measured at Pin 3 (with CDdisconnected), with no input and with Pin 2 shorted toPin 10.

DESIGN EQUATIONS(See Fig. 2 for Definition of Components)

1. vca Center Frequency, fO:

fO= I/ROCO Hz

2. Internal Reference Voltage, VR (measured at Pin 10)

VR = V+/2 - 650 mV

3. Loop Low-Pass Filter Time Constant, T:

T = RI CI

4. Loop Damping,~:

~ = 1/4 jCoCI

5. Loop Tracking Bandwidth, ±t:J.f/fO:t:J.f/fO = RO/RI

6. FSK Data Filter Time Constant, TF:TF = RFCF

7. Loop Phase Detector Conversion Gain, Kcb: (Kcb is thedifferential de voltage across Pins 10 and 11, per unit ofphase error at phase-detector input)

Ktj> = - 2V R/1T volts/radian

8. vca Conversion Gain, KO: (KO is the amount of changein vca frequency, per unit of (Ie voltage change at Pin II):

KO = -lfVRCOR 1 Hz/volt

9. Total Loop Gain, KT:

KT = 21TKtj>KO = 4/CORI rad/sec/volt

10. Peak Phase-Detector Current, IA:

IA = VR (volts)/25 mA

APPLICATIONS INFORMATIONFSK DECODING:

Figure 9 shows the basic circuit connection for FSK decoding.With reference to Figures 2 and 9, the functions of externalcomponents are defined as follows: RO and Co set the PLLcenter frequency, RI sets the system bandwidth, and CI setsthe loop filter time constant and the loop damping factor.CF and RF form a one-pole post-detection filter for the FSKdata output. The resistor RB (= 510 Kn) from Pin 7 to Pin 8introduces positive feedback across FSK comparator tofacilitate rapid transition between output logic states.

Recommended component values for some of the mostcommonly used FSK bands are given in Table I.

vcoFINE TUNE

AO

5 KnA, AX

c, -=-

Oesign Instructions:

The circuit of Fig. 9 can be tailored for any FSK decodingapplication by the choice of five key circuit components:RO, R I, CO' C I and CF· For a given set of FSK mark andspace frequencies, f I and f2, these parameters can pe cal-culated as follows:

a) Calculate PLL center frequency, fO:

fl + f2fO= --

2

b) Choose value of timing resistor RO, to be in the rangeof 10 Kn to 100 Kn. This choice is arbitrary. Therecommended value is RO '='" 20 Kn. The final valueof RO is normally fine-tuned with the series potentiom-eter, R X-

c) Calculate value of Co from design equation (I) or fromFig. 6:

Co = I/ROfOd) Calculate RI to give a ~f equal to the mark-spacedeviation:

RI = RO (fO/(fl - f2)]

e) Calculate CI to set loop damping. (See Design Equa-tion No.4).

Normally, ~ "'" 1/2 is recommended.

Then: CI = CO/4 for ~ = 1/2

f) Calculate Data Filter Capacitance, CF:

For RF = 100 Kn, RB = 510 Kn, the recommendedvalue of CF is:

CF "'" 3/(Baud Rate) pF

Note: All calculated component values except RO can berounded-off to the nearest standard value, and RO can bevaried to fine-tune center frequency, through a seriespotentiometer, RX. (See Fig. 9).

Design Example:

75 Baud FSK demodulator with mark/space frequencies of1110/1170 Hz:

Step I: Calculate fO: fO = (I 110 + 1170) (1/2) = 1140 HzStep 2: Choose RO = 20 Kn (18 Kn fixed resistor in series

with 5 Kn potentiometer)Step 3: Calculate Co from Fig. 6: Co = 0.044 pFStep 4: Calculate RI: RI = RO (2240/60) = 380 KnStep 5: Calculate CI: CI = CO/4 = 0.011 pF

Note: All values except RO can be rounded-off to neareststandard value.

FSK BAND COMPONENT VALUES

300 Baud Co = 0.039 pF CF = 0.005 pFfl = 1070 Hz CI = 0.01 pF RO = 18 Knf2 = 1270 Hz RI = 100 Kn

300 Baud Co = 0.022 pF CF = 0.005 pFfl = 2025 Hz CI = 0.0047 pF RO = 18 Knf2 = 2225 Hz RI = 200 Kn

1200 Baud Co = 0.027 pF CF = 0.0022 pFfl = 1200 Hz CI = 0.01 pF RO = 18 Kn-£2 = 2200 Hz RI =30Kn

Recommended Component Values for Commonly Used FSKBands (See Circuit of Fig. 9)

FSK DECODING WITH CARRIER-DETECT:

The lock-detect section of XR-2211 can be used as a carrier-detect option, for FSK decoding. The recommended circuitconnection for this application is shown in Fig. 10. Theopen-collector lock-detect output, Pin 6, is shorted to data.output (Pin 7). Thus, data output will be disabled at "low"state, until there is a carrier within the detection band of thePPL, and the Pin 6 output goes "high", to enable the dataoutput.

The minimum value of the lock-detect filter capacitance CDis inversely proportional to the capture range, ±~fc. This isthe range of incoming frequencies over which the loop canacquire lock and is always less than the tracking range. It isfurther limited by CI. For most applications, ~fc > ~f/2.For RD = 470 Kn, the approximate minimum value of CDcan be determined by:

CD (pF) ~ 16/capture range in Hz.

Figure 10. External Connectors for FSK Demodulation withCarrier-Detect Capability.Note: Data Output is "Low" When No Carrier is Present.

With values of CD that are too small, chatter can be observedon the lock-detect output as an incoming signal frequencyapproaches the capture bandwidth. Excessively-large valuesof CD will slow the response time of the lock-detect output.

TONE DETECTION:Figure II shows the generalized circ~t connection for tonedetection. The logic outputs, Q and Q at Pins 5 and 6 arenormally at "high" and "low" logic states, respectively.When a tone is present within the detection band of the PLL,the logic state at these outputs become reversed for theduration of the input tone. Each logic output can sink 5 mAof load current.Both logic outputs at Pins 5 and 6 are open-collector typestages, and require external pull-up resistors RLl and RL2,as shown in Fig. II.With reference to Figs. 2 and II, the (unctions of the ex-ternal circuit components can be explained as follows: ROand Co set VCO center frequency; RI sets the detectionbandwidth; CI sets the low pass-loop filter time constantand the loop damping factor. RLl ~nd RL2 are the respec-tive pull-up resistors for the Q and Q logic outputs.

LOGICOUTPUT 0-l LOGIC

OUTPUT.to

Design Instructions:The circuit of Fig. II can be optimized for any tone-detectionapplication by the choice of the 5 key circuit components:RO, RI, CO'CI and CD' For a given input the tone frequency,fS' these parameters are calculated as follows:a) Choose ROto be in the range of 15 Kil. to 100 Kil.This choice is arbitrary.

b) Calculate Co to set center frequency, fOequal to fS:(See Fig. 6). Co = I/ROfS

c) Calculate RI to set bandwidth ±~f: (see design Equa-tion No.5):

RI = RO(fO/~f)Note: The total detection bandwidth covers the frequencyrange of fO± ~f.d) Calculate value of CI for a given loop damping factor:CI = CO/16t2

Normally t ::::::112 is optimum for most tone-detector appli-cations, giving CI = 0.25 CO,Increasing CI improves the out-of-band signal rejection, butincreases the PLL capture time.e) Calculate value of filter capacitor CD' To avoid 'chatterat the logic output, with RD = 470 Kil, CD must be:CD(.uF) ~ (I6/capture range in Hz)

Increasing CD slows down the logic output response time.

Design Examples:Tone detector with a detection band of I kHz ± 20 Hz:a) Choose RO= 20 K11(18 K11in series with 5 K11potentiometer).

b) Choose Co for fO= I kHz: From Fig. 6: Co = 0.05 IJF.c) Calculate Rf RI = (RO)(1000/20) = I Mil.d) Calculate CI: for t = 1/2, CI = 0.25, Co = 0.013 IJF.e) Calculate C.D:CD = 16/38 = 0.42IJF.f) Fine-tune center frequency with 5 Kil potentiometer, RX'

ADJUSTMENT PROCEDUREWith the input open-circuited, the loop phase detector out-put voltage is essentially undefined and VCO frequency maybe anywhere within the lock range. There are several waysthat fOcan be monitored:I. Short pin 2 to pin 10 and measure fOat pin 3 with CDdisconnected;

2. Open RI and monitor pin 13 or 14 with a high-impedanceprobe; or

3. Remove the resistor between pins 7 and 8 and find theinput frequency at which the FSK output changes state.

NOTE: Do NOT adjust the center frequency of the XR -2211by monitoring the timing capacitor frequency v'ith everythingconnected and no input signal applied.

'2 " -=-RO

R1V+-=- RF

'00 Kn

c,I-=-

Figure 12. Linear FM Detector Using XR-2211 and an External Op.Amp. (See section on Design Equations, for Component Values)

LINEAR FM DETECTION:XR-2211 can be used as a linear FM detector for a wide rangeof analog communications and telemetry applications. Therecommended circuit connection for this application isshown in Fig. 12. The demodulated output is taken from theloop phase detector output (Pin II), through a post detectionfilter made up of RF and CF, and an external buffer ampli-fier. This buffer amplifier is necessary because of the highimpedance output at Pin II. Normally, a non-inverting unitygain op amp can be used as a buffer amplifier, as shown inFig. 12.The FM detector gain, i.e., the output voltage change per unitof FM deviation, can be given as:Vout = RI VR/l 00 ROVolts/%devia tion

where VR is the internal reference voltage. (VR = V+/2 -650 mV). For the choice of external components R I, Ro,CD, CI and CF, see section on Design Equations.