exceptions - basavaraj talawar · breakpoint (programmer-requested interrupt) ... processor state,...
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Exceptions
Outline
● Exception Handling● Precise and Imprecise exceptions● Exceptions in OoO pipelines
Exceptions
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions● I/O device request
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions● I/O device request● Invoking OS service from a user program
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions● I/O device request● Invoking OS service from a user program● Breakpoint (programmer-requested interrupt)
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions● I/O device request● Invoking OS service from a user program● Breakpoint (programmer-requested interrupt)● Integer arithmetic overflow/FP arithmetic anomaly
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions● I/O device request● Invoking OS service from a user program● Breakpoint (programmer-requested interrupt)● Integer arithmetic overflow/FP arithmetic anomaly● Page fault
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions● I/O device request● Invoking OS service from a user program● Breakpoint (programmer-requested interrupt)● Integer arithmetic overflow/FP arithmetic anomaly● Page fault● Undefined or unimplemented instruction
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions● I/O device request● Invoking OS service from a user program● Breakpoint (programmer-requested interrupt)● Integer arithmetic overflow/FP arithmetic anomaly● Page fault● Undefined or unimplemented instruction● Hardware malfunctions, Power failure
Events that requestattention of the processor
Events that requestattention of the processor
Exceptions
Precise Exception Handling
LD
Precise Exception Handling
LD
On exception, flush all prior stagesOn exception, flush all prior stages
Exception Handling
Exception Handling● Save the address of the offending instruction in
the exception program counter (EPC)– SEPC in RISC-V
Exception Handling● Save the address of the offending instruction in
the exception program counter (EPC)● Transfer control to the operating system at some
specified address.
Exception Handling● Save the address of the offending instruction in
the exception program counter (EPC)● Transfer control to the operating system at some
specified address.● Handle the exception
– Providing some service to the user program– Taking some predefined action in response to an
overflow– Stopping the execution of the program and reporting
an error
Exception Handling● Save the address of the offending instruction in the
exception program counter (EPC)● Transfer control to the operating system at some
specified address.● Handle the exception
– Providing some service to the user program– Taking some predefined action in response to an overflow– Stopping the execution of the program and reporting an
error● OS can terminate or may use EPC to restart
program
Communicating Exception Cause to OS
● A register records the cause of exception– Supervisor Exception Cause (SCAUSE) Register
●
Communicating Exception Cause to OS
● A register records the cause of exception– Supervisor Exception Cause (SCAUSE) Register
● Vectored Interrupts
Communicating Exception Cause to OS
● A register records the cause of exception– Supervisor Exception Cause (SCAUSE) Register
● Vectored Interrupts– Cause of the exception determines offset to jump– Added to a Vector Table Base register
Communicating Exception Cause to OS
● A register records the cause of exception– Supervisor Exception Cause (SCAUSE) Register
● Vectored Interrupts– Cause of the exception determines offset to jump– Added to a Vector Table Base register
RISC-V Exception Handling● SEPC, SCAUSE● Single entry point for Exception handler
– 0000 0000 1C09 0000hex
RISC-V Exception Handling● SEPC, SCAUSE● Single entry point for Exception handler
– 0000 0000 1C09 0000hex
● For the pipeline, handling Exceptions are similar to handling Control Hazards–
–
–
–
RISC-V Exception Handling● SEPC, SCAUSE● Single entry point for Exception handler
– 0000 0000 1C09 0000hex
● For the pipeline, handling Exceptions are similar to handling Control Hazards– SEPC saves instruction causing Exception’s PC – SCAUSE is filled– Flush all previous stages and the exception instruction– Load Exception handler address to PC
RISC-V Exception Handling Pipeline
RISC-V Exception Handling Pipeline
Exception Handling Example
Hardware malfunction exception occurs in the add instruction.
Exception Handling Example
IF ID
IF
Exception Handling Example
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID
IF ID
IF
IF ID
IF
E
Exception Handling Example
Exception Handling Example
Outline
● Exception Handling● Precise and Imprecise exceptions
Multi-cycle Operations Pipeline
Precise Exceptions
● Out of order completion● Can't ignore exceptions
– Virtual Memory, IEEE 754● Fast mode vs. Slow mode with precise
exceptions● Store results of earlier operations in a buffer
– History file, Future file.
DIV.D F0, F2, F4
ADD.D F10, F10, F8
SUB.D F12, F12, F14
Stopping and Restarting Execution● Trap instruction, Turn off writes, Save PC, Save
processor state, (Disable Exceptions), Exception handler, RFE
● Precise exceptions
Pipeline stage Problem exceptions occurring
IFPage fault on IF, misaligned memory access; memory protection violation
ID Undefined or illegal opcode
EX Arithmetic exception
MEMPage fault on data fetch; misaligned memory access; memory protection violation
WB None
Precise Exceptions
LD IF ID EX MEM WB
DADD IF ID EX MEM WB
● Multiple exceptions in the same cycle● Early exception by a later instruction● Instruction Status Vector: Check before commit
Precise Exceptions
● Instruction Status Vector: Check before commit