exlru : a unified write buffer cache management for flash memory emsoft '11 liang shi 1,2,...

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ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2 , Jianhua Li 1,2 , Chun Jason Xue 1 , Chengmo Yang 3 and Xuehai Zhou 2 1 Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong 2 Department of Computer Science, University of Science and Technology of China, Hefei, China 3 Department of Electrical & Commputer Engineering, University of Delaware 2012. 01. 12 (Thu) Kwangwoon univ. SystemSoftware Lab. HoSeok Seo 1

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Background  Previous study for NAND flash & Access patterns  FAB, BPLRU, etc 3 Weak from sequential write patterns Weak from random write patterns

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Page 1: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

ExLRU : A Unified Write Buffer Cache Management for Flash Memory

EMSOFT '11

Liang Shi1,2, Jianhua Li1,2, Chun Jason Xue1, Chengmo Yang3 and Xuehai Zhou2 1Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong2Department of Computer Science, University of Science and Technology of China, Hefei, China3Department of Electrical & Commputer Engineering, University of Delaware2012. 01. 12 (Thu)

Kwangwoon univ. SystemSoftware Lab.

HoSeok Seo1

Page 2: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Introduction Propose

Write buffer management scheme for Flash memory

Purpose of write buffer? Increase the write performance Reduce the number of erase operations on flash memory

Why consider NAND Flash characteristics? Write operation time is longer than read operation NAND Flash has limited erase operation count Out-place-update

Page 3: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Background Previous study for NAND flash & Access patterns

FAB, BPLRU, etc

Weak from sequen-tial write patterns

Weak from random write patterns

Page 4: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Motivation Previous schemes is

Managed with the block-level information. Lack of the page-level information.

Result in inappropriate eviction decisions, as fol-lows:

Slow retirement of large cold blocks.- Block size is big, but pages is cold.

Early eviction of small hot blocks.- Block size is small, but pages is hot.

Cold page retention in heat-imbalanced blocks.- Few pages is hot, but most pages is cold.

Thus, ExLRU takes the page-level access in-formationand the characteristics of flash memory.

Page 5: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Cost Model of ExLRU The page-level information and the block-level infor-

mation

Page 6: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Cost Model of ExLRU Averaged Frequency of Pages (AFP)

Averaged Frequency of Block (AFB)

Unified eviction cost of block x (UC)

Page 7: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Cost Model of ExLRU Example

Cost is

Page 8: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Efficient ExLRU The cost model of ExLRU has the overhead of O(n).

Efficient ExLRU Proposed to reduce the overhead. Identify the block with UC value low enough, not the lowest. Pre-identify blocks during the idle time between two write

requests

Cost is

Page 9: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Efficient ExLRU Two processes

Scanning process and victim block selection process

(WR) (ER)

Page 10: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Efficient ExLRU In scanning process.

Work in time between two write requests, if the number of blocks in ER is smaller than a threshold Nmin.

Move blocks into ER, if UC < TUC

In victim block selection process. Select a block at LRU position of ER when the buffer is

full. If block miss in ER, UC values of blocks decrease. If hit in ER, re-compute UC, and move a block WR or

not. If page miss in ER, add pages a block, and re-compute

UC, and move a block MRU position of ER

Page 11: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Experimental Methodology Use event-driven Simulator SSD capacity : 8GB A page size : 2KB A block size : 64 pages FTL algorithm : FAST Trace : Financial, PC

Page 12: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Experimental Results Average Size and Number of Evicted Blocks

ExLRU_S : TUC is static ( 0.1 x 10-5 )ExLRU_D : TUC is dynamic

19.7% decrease 19.1% increase

Page 13: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Experimental Results Write and Erase Reduction in Financial trace

Best case10.4% decrease

Average3% decrease

Page 14: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Experimental Results Write and Erase Reduction in Financial trace

Page 15: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Parameter Sensitive Studies

Nmin : Min number of blocks of ERTUC : Max value for ERTSCAN. : Max number of blocks at scan

Page 16: ExLRU : A Unified Write Buffer Cache Management for Flash Memory EMSOFT '11 Liang Shi 1,2, Jianhua Li 1,2, Chun Jason Xue 1, Chengmo Yang 3 and Xuehai

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Conclusion This scheme is designed to improve the write per-

formance and reduce the number of erase opera-tions

Care about diverse type of access patterns.

Exploit the page-level information and the block size