EXP5: Digital Switch.

OBJECTIVES.

The purpose of this experiment is to acquaint you with the general operation of a Bipolar Junction Transistor(BJT) and the Junction Field Effect Transistor(JFET), and to demonstrate the BJTs operation as a switch.For the transistors to be working as a digital switch they have to be working in the digital regimen, that isworking on the cut-off and saturation regions for BJTs, and in the triode and cut-off regions for JFETs.

INTRODUCTION AND TEST CIRCUITS.

Before we start, let’s do a review on the transistor’s VI characteristic.

BJTs.

Since the transistor has three terminals we can plot more than one VI characteristic, however the most usedto understand its behavior and to help designing circuits is the VI characteristic that plots the CollectorCurrent (IC) versus the Collector Emitter Voltage (VCE), see fig. 5-1, actually there is a different curve forevery different value of Base Current (IB), that is why we see more than one curve. All of the above is tellingus that the operating point is going to be in function of IB and the load line, which is set up by externalelements such as resistors and power sources.

Figure 5-1: Collector current vs. Collector-Emitter voltage characteristic of a 2N3904 npn BJT transistor.

The resistors that are placed on the collector-emitter loop, see figure 5-2, will define the load line equation,eq 5-2.

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VCC = V (RC) + VCE (5-1)

V (RC) = ICRC

VCC = ICRC + VCE

IC = −VCE

RC+

VCC

RC(5-2)

Figure 5-2: Elements that generate the load line equation.

In figure 5-3 we can see the load line on top of the VI curves. To find the operating point , i.e. the collector-emitter voltage and the collector current, we need to know the value of the base current. Knowing the basecurrent means we can select one of all the curves we see in the figure. Then the operating point is theintersection of that VI curve with the load line.

Figure 5-3: Load line and the three different regions.

There are three different regions we can see once we set up the loadline.

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• Saturation Region: In this region the collector current does not have increments equally spaced forequally spaced increments in base current.

• Constant Current Region: In this region the collector current has increments equally spaced forequally spaced increments in base current.

• Cut-off Region: In this region the collector current is so small that we can consider it to be zero.

Now that we’ve learned the regions, it is important for us to know what regions a digital switch is supposeto work on.

Figure 5-4: Transfer characteristic for different ratios of RC/RB for an inverter configuration.

The digital regime, means that the transistor will have two states, the ”on” and ”off” states. Being thosestates the cut-off and the saturation regions, not necessarily in that order. Since we do not want the transistorto be in the constant current region we would like to have a input-output voltages transfer characteristicthat has a steep slope on that region, as shown in figure 5-4.

Figure 5-5: Inverter configuration.

The inverter and the voltage follower are two configurations that can be easily used as switch. Figure 5-5shows the inverter configuration, this configuration is going to have zero volts at the output ”0” when youapply a voltage at the input ”1”, and the opposite it will have voltage at the output ”1” when you applyzero volts at the input ”0”. The relationship between input and output currents is shown in eq. 5-3. This

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equation should help you in the designing of your switch. Since you will know the characteristics of the load,i.e. the required voltage and current to operate the device, you will be able to find a suitable base resistorvalue so the levels of current, needed to place the transistor in cut-off or saturation, can be set up.

vOUT = VCC − βFRC

RB(vIN − Vf ). (5-3)

JFETs

Figure 5-6: Drain current vs. Drain-Source voltage characteristic of a JFET transistor.

For the JFET we will have the same; a family of VI curves. Since the terminals are labeled different thanthe BJT, The voltages and currents involved now are the Drain current ID, Drain to Source Voltage VDS

and the Gate to Source Voltage VGS . The VI curves for the JFET are shown in figure 5-6. Note that forthis particular transistor the maximum current is achieved for VGS = 0. This particular kind of transistors,n-channel JFETs, are not designed to work with positive VGS voltages, so keep that in mind.

Figure 5-7: Elements that generate the load line equation.

Similar to BJTs the resistors that are placed on the drain-source loop, see figure 5-7, will define the load line

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equation, eq 5-5.

VDD = V (RD) + VDS (5-4)

V (RD) = IDRD

VDD = IDRD + VDS

ID = −VDS

RD+

VDD

RD(5-5)

Figure 5-8: Load line and the three different regions.

In figure 5-8 we can see the load line on top of the VI curves. To find the operating point , i.e. the drain-source voltage and the drain current, we need to know the value of the gate-source voltage. Knowing thegate-source voltage means we can select one of all the curves we see in the figure. Then the operating pointis the intersection of that VI curve with the load line.

There are three different regions we can see once we set up the loadline.

• Triode Region: In this region the drain current behavior is highly nonlinear.

• Constant Current Region: In this region the drain current behaves linear. However we will not seeequally spaced increments of drain current due to equally spaced increments of gate-source voltage.

• Cut-off Region: In this region the drain current is so small that we can consider it to be zero.

Again as for the BJTs, the digital regime means that the transistor will have two states, the ”on” and ”off”states. Being those states the cut-off and the triode regions, not necessarily in that order. Since we do notwant the transistor to be in the constant current region we would like to have a input-output voltages transfercharacteristic that has a steep slope on that region, as shown in figure 5-9. Note the nonlinear behavior ofthe transfer characteristic in the constant current region due to the nonequally spaced increments in ID.

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Figure 5-9: Transfer characteristic for different values of RD for an inverter configuration.

We can see in the above figure that for some values of RD the transistor never reaches the triode region andthat the minimum VDS reached is considerably big, that limits its use as a switch.

Figure 5-10: Inverter configuration.

Figure 5-10 shows the inverter configuration, this configuration is going to have some ”low” voltage at theoutput ”0” when you apply zero volts at the input ”1”, and the opposite it will have some ”high” voltageat the output ”1” when you apply some negative voltage at the input ”0”. The relationship between inputand output voltages is shown in eq. 5-6. This equation should help you in the designing of your switch.However due to the shape of the VI curves and that there is a limit in the maximum positive VGS there is acompromise between getting a small VDS and having a big ID.

vOUT = VDD −KRD(vGS − VTR)2. (5-6)

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PREPARATION.

We will be using a BJT and a JFET, in the inverter and voltage follower configurations, to design a digitalswitch, see figure 5-11. Keep in mind that we would like the switch to comply with the main characteristic.

• Low ”on state” voltage at its terminals. Ideally zero.

Figure 5-11: Inverter and voltage follower configurations for BJT and JFET.

Use PSpice to do the following:

BJT.

1. Get the VI curves for the 2n3904 BJT.hint: Do a DC sweep with a secondary sweep. Use the primarysweep to sweep the value of VCE and the secondary to sweep the value of IB .

2. Suppose a 2k resistor is your load. i.e. RC = 2k, and that V cc = 10V . Plot the loadline. Use thisplot to show where the different regions are, label them. Give an approximation for the base currentranges that will make the transistor to be in the different regions.

3. Use Vf = 0.6 to find the value of RB needed to make the transistor work in the digital regime when a0v-5v square wave is applied as input. Use the following equations:

• For the inverter,

ib =Vin − Vf

RB(5-7)

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• For the voltage follower,

ib =Vin − Vf − icRC

RB + RC(5-8)

4. Get the input-output voltage transfer characteristic. Identify and label the three different regions herealso. Give the input voltage range for the three different regions.

5. Use a square wave at the input and do a transient analysis to find the waveform of Vout, label the ”on”level and the ”off” level.

JFET.

1. Get the VI curves for the 2n3819 BJT.

2. Suppose a 2k resistor is your load. i.e. RD = 2k and that V dd = 10V . Plot the loadline. Use this plotto show where the different regions are, label them. Give an approximation for the gate-source voltageranges that will make the transistor to be in the different regions.

3. Get the input-output voltage transfer characteristic. Identify and label the three different regions herealso. Give the input voltage range for the three different regions.

4. Use a -5V to 0V square wave at the input and do a transient analysis to find the waveform of Vout,label the ”on” level and the ”off” level.

PROCEDURE.

Now that you know the procedure on how to design a switch, your goal in this experiment is to design aswitch that can light a led in series with a 1k resistor using the two configurations, the inverter and thevoltage follower. Hint: You have to replace RC for the BJT’s circuits and RD for the JFET’scircuits with the LED in series with the 1k resistor.

While you are doing the design, you will need to get the following curves and show how you use them forthe design.

• VI characteristics of the transistors used.

• VI characteristic of the LED in series with the resistor.

• Once you have your circuit working use the oscilloscope and the function generator set up with a relativesmall frequency, so we can see the LED turning on and off, and the appropriate levels to capture thewaveform for the voltage VCE for the BJT and the voltage VDS for the JFET. Use scopegrab to capturethe waveforms.

ANALYSIS.

Make sure you include a comparison between BJT and JFET performance such that you can use it to decidewhich one is better as a switch.

Answer the following:

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1. What is the main difference between the design of an inverter and the design of a voltage follower.?

2. Based on the voltage seen in VCE and VDS when the switch is closed, what transistor is better suitedto work as a switch?

3. If we change the LED and the 1k resistor by a 0.5K resistor in the JFET circuits, will the transistorbe able to go to triode region?

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