experiment electronics umc 0.18µm radiation hardness studies - update - sven löchner 13 th cbm...

Experiment Electronics

UMC 0.18µm radiation hardness studies

- Update -

Sven Löchner

13th CBM Collaboration MeetingGSI Darmstadt

March 12th, 2009

March 12th, 2009 13th CBM Collaboration Meeting - Sven Löchner 2Experiment Electronics

Additional Talks & DocumentsAdditional Talks & Documents

Reference to further talks:

• EE-Gruppenmeeting (7.7.2008)GRISU Statusreport

• CBM-XYTER Family Planning Workshop (5.12.2008)UMC 0.18μm radiation hardness studies

• IT/EE-Palaver (20.1.09) Untersuchung von Strahlungseffekten in anwendungs-spezifischen integrierten Schaltungen (ASIC) Strahlungseffekte

Link: http://wiki.gsi.de/cgi-bin/view/EE/GRISU


Reminder: GRISU projectReminder: GRISU project

Project objectives:

• Characterisation of UMC 0.18µm CMOS process concerning the vulnerability against Single Event Effects (SEE), especially Single Event Upsets (SEU) and Single Event Transients (SET)– SEU cross section for different Flip-Flop designs and layouts

– Characterisation of the critical charge Qcrit respectively the Linear Energy Transfer (LETcrit )

– SET sensitivity of the UMC 0.18µm process

• Single Transistor measurements– Comparison of transistor models by simulation– Total Ionising Dose (TID)

Characterisation of the UMC 0.18µm process under irradiation, especially leakage currents, threshold shifts, annealing, ...


GRISU test ASICGRISU test ASIC

Test structures for TID

measurements

Test structures for SEU measurements

Test structures for SET measurements, Qcrit

Ring oscillator for TID / SEU measurements

GRISU chip

• UMC 0.18µm process

• 1.5 x 1.5 mm²

• 64 pads– 28 core pads– 36 pads


SEE Building BlocksSEE Building Blocks

3 different building blocks for SEE characterisation:

• Test structures for SEU measurements– 8 different types of flip-flops implemented, e.g. oversized flip-

flops, flop-flops with Dual Interlock Cell (DICE) architecture, ...

• Test structures for SET and Qcrit measurements

– Different inverter chains=> Qcrit,sim from 20 ... 1000fC

• 2 ring oscillator test structure


•X6 cave at GSI

Low Energy testing siteLow Energy testing site

• Installation of a test facility for ASIC irradiation with heavy ions at X6 cave at GSI (in cooperation with bio physics group)

• Beam monitoring via ionisation chamber

• Dosimetry setup available

• Irradiation of DUT in air

• Easy access

Disadvantages of setup:

• Only one ion source during beam time

• “Fixed” LET range for ion source


SEE Tests at GSISEE Tests at GSI

SEE test with heavy ions at GSI:

• X6 experimental site

• 11.4 MeV/u

• 7 irradiation tests so far– C-12 (3x)– Ar-40– Ni-58– Ru-96– Xe-132

• LET in the range of 1...62 MeV·cm²/mg (SiO2) Q = 8..1300 fC


LET testing rangeLET testing range

Overview of the LET testing range for the applied heavy ions test


Cross-section (Weibull-Fit)Cross-section (Weibull-Fit)

C-12 Ar-40 Ni-58 Ru-96 Xe-132

LETcrit = 1.93 MeV cm²/mg

σsat = 1.48·10-8 cm²/bit


Cross-section (DF)Cross-section (DF)

LET = 4 MeV cm²/mg


DDual ual IInterlock nterlock CeCell (DICE)ll (DICE)

DICE (Dual Interlock Cell) memory technologies are (more or less) immune against SEU flips.

Reference: T. Calin, M. Nicolaidis, R. VelazcoUpset Hardened Memory Design for Submicron CMOS TechnologyIEEE Transactions on Nuclear Science, Vol. 43, No. 6, December 1996


Layout DICE LatchLayout DICE Latch


Layout Sense Amp. DICE FF Layout Sense Amp. DICE FF


SEE SummarySEE Summary

• Setup of a heavy ion test environment for ASIC irradiation– defined LET value within a range from 1...62 MeV·cm²/mg (SiO2)

• Measurement of SEE cross-section for different design cells

• No SET observed on clock lines capacitance of clock lines high

Not really understood:

• Higher sensitivity of DICE cells than expected Heavy ion micro beam scan setup

Maybe on a next chip iteration:

• Triple redundant testing (SEU / SET improvement)


GRISU 2 – test structuresGRISU 2 – test structures

• Access to single transistors via core pads– small pad geometry– close to neighbour test pads

• 16 test structures– NMOS– PMOS– zero-Vt and low-Vt– special transistor layouts (e.g. enclosed, finger)

• Automatic measurement of transistor characteristics– Output characteristic (Uds – Ids)– Transfer characteristic (Ugs – Ids)


TTotal otal IIonizing onizing DDose (TID) testsose (TID) tests

• TID testing with X-rays– Irradiation facility at Institute for Experimental Nuclear Physics,

University of Karlsruhe– 60keV X-ray– 100 ... 600krad/h

• 9 GRISU chips tested– Total dose between 800krad and 2500krad(SiO2)– Operating dose rate between 200krad/h and 580krad/h– Two radiation test modes

• single transistor test structure measurementsleakage current, threshold shift, characteristics

• complete chip measurementstransition times, total power consumption


TID tests – complete chipTID tests – complete chip

• Power consumption (Pads)– Increase of power consumption by factor of 100 after 1.5Mrad

Leakage current of ESD protection diodes

– Good annealing at room temperature back to pre-radiated value after 6 weeks

• Power consumption (Core)– Increase by factor of 2 after 1.5 Mrad– Also good annealing at room temperature

back to pre-radiated value after 6 weeks

• Transition times of minimum size inverter (ring oscillator)– Gets slightly faster up to 250krad– Beyond 250krad noticeable slower

unbalanced NMOS / PMOS ration of inverter

– Good annealing at room temperature


TID tests – single transistorsTID tests – single transistors

Measurements of the transistor characteristics and calculation of

the threshold voltages for different dose levels

• In total 6 chips are irradiated

• Total dose up to 2.5Mrad

• Dose rate between 200krad/h and 580krad/h


TID tests – single transistorsTID tests – single transistors

• Threshold voltage (Vth)– Almost no further threshold shift after 1Mrad observed– Larger NMOS Vth shift for smaller W– Constant Vth for enclosed transistors (as expected)– More or less no Vth shift for PMOS transistors

• Leakage current– No significant increase up to 200krad– Scales with gate length L (NMOS)– Zero-Vt: already high leakage current for pre-radiated transistor

(≈ 0.5µA)– No increase in leakage for enclosed and PMOS transistors

• Annealing– Recovery of Vth in the order of 20-40% after 6 weeks– Leakage more or less back to pre-radiated values after 6 weeks


TID summaryTID summary

• UMC process shows good annealing at room temperature(at least at high dose rates)

• Simulation models slightly differs from measured characteristics (especially between small and large Ugs)

Still to be done

• Second irradiation campaign with low dose rates

• Long term test with a gamma source


Thank you


Additional TransparenciesAdditional Transparencies


SSingle ingle EEvent vent EEffects (SEE)ffects (SEE)

SEE: two types of categories

• Cause of permanent damages (hard errors)

• Induce of temporary malfunctions (soft errors)

Only soft errors are analysed, especially:• Single Event Upsets (SEU)

Bit flips, e.g. change of states in the digital logic

• Single Event Transient (SET)Temporary change of the signal level in the circuit, e.g. a glitch


LLinear inear EEnergy nergy TTransfer (LET)ransfer (LET)

• Minimum amount of particle energy induced to a semi-conductor device at which a SEE appears is called LETcrit

• The unit of LET is typical MeV·cm²/mg (related to Si for MOS)

de

QLET

Si

critcrit

eV6.3 d - sensitive depth of penetration

- material density (Si: 2.33g/cm3)

Typical values for 0.18µm process technology:

• d = 0.5 ... 2µm

• Qcrit = 30 ... 60fC

=> LETcrit between 1.5 and 12 MeV·cm²/mg


Charge collectionCharge collection

cross-section through an ASIC charge collection under the gate


GRISU 2 – test structures GRISU 2 – test structures

4 groups with each 4 single transistor test structures

NMOS transistors W = 0,24 µm L = 1,80 µm W/L = 0,13W = 2,40 µm L = 0,18 µm W/L = 13,33W = 0,24 µm L = 0,18 µm W/L = 1,33W = 2,40 µm L = 1,80 µm W/L = 1,33

Zero-Vt transistors W = 2,40 µm L = 3,00 µm W/L = 0,80W = 0,24 µm L = 0,30 µm W/L = 0,80

Low-Vt transistors W = 0,24 µm L = 0,24 µm W/L = 1,00W = 2,40 µm L = 2,40 µm W/L = 1,00

Enclosed transistors W = 2,28 µm L = 0,18 µm W/L = 12,67W = 6,70 µm L = 1,80 µm W/L = 3,72

Enclosed Zero-Vt W = 4,48 µm L = 0,30 µm W/L = 14,93Finger transistor (10x) W = 10*0,24 µm L = 0,18 µm W/L = 13,33

PMOS transistors W = 2,40 µm L = 1,80 µm W/L = 1,33W = 0,24 µm L = 0,18 µm W/L = 1,33

Enclosed PMOS transistor W = 6,70 µm L = 1,80 µm W/L = 3,72Finger transistor (10x) W = 10*0,24 µm L = 0,18 µm W/L = 13,33


GRISU 2 – test structuresGRISU 2 – test structures

Output characterisation of a minimum size NMOS transistor (0.24 / 0.18) at Ugs = 0.6V (left) and Ugs = 1.5V (right)

Discrepancies between measurements and simulations.


Vth – simulation vs. measurementVth – simulation vs. measurement

Threshold measurement for all test structures.

Tendency to higher threshold values for all test structures is

visible.