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ESD

company confidential

ESD = Electro Static Discharge

Issues in ESD:

ESD circuit protection measures = use of ESD protection

structures (on-chip protection)

ESD Qualification = standardized tests, part of the productqualification

external ESD protection = adequate handling, ESD safe

working place

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Mission: ESD/ Latch-up Protection Development

Satisfy the market demands for ESD and latch-up robustness

Minimum chip area for ESD and latch-up measures

Verified rules available in the first design phase of products

Provide IFX IO-libraries and ICs with state of

the art ESD and Latch-up protection rules

Provide IFX IO-libraries and ICs with state of

the art ESD and Latch-up protection rules

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General ESD Objectives

2 kV HBM hardness according to EIA/JESD22-A114-B

(MIL-Std. 883D, method 3015.7).

500 V CDM hardness according to EOS/ESD association

Standard DS5.3 - 1993

ESD optimized process and optimized protection structures at

process freeze.

Verified protection structures and IO libraries at processrelease.

Stable ESD quality during production.

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General Latch-up Objectives

Latch-up hardness according to EIA/JEDEC Standard No.78,

class II (maximum ambient operating temperature)

I-Test for signal pins: +-100 mA

Overvoltage test for power supply pads: > 1.5 max. Vsp (not

exceeding absolute maximum ratings)

Latch-up optimized process and optimized guardring rules at

process freeze. Verified rules and IO libraries at process release.

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Mission: ESD/Latchup Qualification

Testing and classification of theESD/Latchup sensitivity of IFX devices

according to the state of the art standards

Testing and classification of theESD/Latchup sensitivity of IFX devices

according to the state of the art standards

State of the art, competitive ESD/Latchup classification of products

Influence on international ESD/Latchup standards

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Mission: External ESD Protection

Providing and maintaining an ESD protection

system for all Infineon semiconductor

locations according to the state of the artstandards

Providing and maintaining an ESD protection

system for all Infineon semiconductor

locations according to the state of the artstandards

Preparation of internal ESD instructions(personnel, rooms, packaging)

Training and support of the Local ESD Representatives

Maintenance of the ESD information system(products, test equipment, standards, literature, problems)

Influence on international ESD standards

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Contact Persons

Tel. Fax. PC-mail sun-mail

ESDLU Development

Dr. Gossner Coordination 22384 27115 yes gossner

ESDDr. Bieger Transfers/Consulting BiCMOS/Bipolar 25554 27115 yes

Dr. Esmark C11N, ESD simulation 25929 27115 yes esmark

Dr. Szatkowsky C9FLx 25384 27115 yes szat

Dr. Streibl B9C, B7HF/C; HF CMOS 26646 27115 yes mstreibl

Dr. Wendel C13, C12, C11FL 27116 27115 yes mwendel

Mr. Zngl Transfers/Consulting CMOS 23349 27115 yes zaengl

Latch-up

Dr. Bargstdt-Franke LU Simulation/Guidelines/Consulting 21440 27115 yes bsilke

ESDLU/IO circuit Testlab (no product qualification tests -> RTC)

Dr. Stadler coordinator 22716 28555 yes wstadler

Dr. Brodbeck test methods, standards 23016 28555 yes brodbeck

Ext. ESD Protection Guidelines - Audits - Training - Standards

Mr. Grtner ESD coordinator (external ESD) 23754 22570 yes ESD.Coordinator

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For further information: http://lib.muc.infineon.com/esdlu