extraction and simulation of complex silicon interposer ... · • name and size of gds/lef file:...

© 2012 ANSYS, Inc. November 19, 2012 1 Apache Design, a subsidiary of ANSYS Apache Design, a subsidiary of ANSYS

Extraction and simulation of complex silicon interposer structures with measurement correlation

11/15/2012 Sooyong Kim Area Technical Manager

© 2012 ANSYS, Inc. November 19, 2012 2 Apache Design, a subsidiary of ANSYS 2

Project Background • Interest in tool arose from experience supporting electrical power distribution in 3D

IBM interposer module – Simple model (two pins) vs. entire interposer – Difficulties in model extraction (Several tools) – Large run times/capacity issues even for simple models – No direct IR drop data across interposer – No direct dynamic simulations – Strategic tool for future 3D designs

• Redhawk from Apache team in Ansys for interposer/chip carrier electrical analysis & 3D modules – IR drop (DC analysis/ EM analysis) – Dynamic (Transient analysis) – Power model extraction (SPICE parasitic model, CPM ) – Point to point resistance Check

© 2012 ANSYS, Inc. November 19, 2012 3 Apache Design, a subsidiary of ANSYS

Apache Power and Noise Platforms

RPM (RTL Power Model) Activity, cycle-to-cycle Block power

CPM (Chip Power Model) Distributed RLC, current Power, signal, EMI, thermal

CMM (Custom Macro Model) Hierarchical model IP protection

PowerTheater / PowerArtist

Totem Sentinel RedHawk


Chip/Chip Carrier/Package Software

• Apache software addresses entire module (Tool A) • Packaging level software (Tool B) • Chip level software (Tool C)

Tool A

Tool B

Tool C


Initial Test Cases

• Hendrix (200mm) and Beyonce (300mm) silicon interposer test vehicles • Same design – different cross section & TSVs • Four identical quadrants for 4 chips


Beyonce Design (Top Right) & Pins For Measurements

3

4

1 2

5


Beyonce DC resistance measurements*

D

A

B

C

E 1 2 3 4 5A 0.737 2.000 0.213 2.079 0.786B 0.725 2.028 0.214 2.127 0.805C 0.646 2.059 0.221 2.150 0.859D 0.710 2.060 0.218 2.150 0.815E 0.673 2.083 0.227 2.183 0.830

Tool used Keithley 2700Tool # 1076534

cal date 2012-04-03cal due 2013-04-03

interposer position tested net (ohm)

Tested interposer location

* From J. Audet


Redhawk to Measurements Comparison

Redhawk (Ohms)

Measured (Ohms)

Difference (Ohms)

0.566 0.673 - 0.107

1.879 2.083 - 0.204

0.336 0.227 +0.109

1.976 2.183 - 0.207

0.884 0.830 +0.054


Redhawk Dynamic Simulations

• No need for separate tool for static vs. dynamic • Graph shows effect of having decaps vs no caps on interposer • Die Power Model ( CPM ) created , open spice format

PAD current at VDD


Pad voltage at VDD


Hendrix Small Test Case Details • Results for dynamic simulation • Name and size of gds/lef file: hendrix_vdd_grn.gds (28KBytes),

hendrix_3_18_09.def (8.3MBytes) • Machine run: bucksport (Linux64) in IBM EFK • Linux OS: Redhat v5.2 • Processor: AMD Opteron 252 - 2 2.6 GHz • Total physical memory: 10G • Run time used by Redhawk: 8 mins 0 secs. • Memory used by Redhawk: 1.324 GBytes • Diskspace used by Redhawk: 362 Mbytes • Improvement in model size/run time vs. existing

8 mins vs. 1 week runtime


Hendrix/Beyonce Large Test Case Details • Results for dynamic simulation

– (static simulation a bit smaller than this)

• Name and Size of gds file: hendrix_mike.gds (2.48M), hendrix_3_18_09.def (3G)

• Machine run: ae256 Linux64 in Ansys CA • Linux OS: Redhat v5.2 • Processor: AMD Opteron 6128HE 4 – 2.0GHz • Total Physical memory: 256G • Run time used by Redhawk: 45 hrs 42 mins 20 secs • Memory used by Redhawk: 48.2G • Diskspace used by Redhawk: 14G

– Beyonce test case (a bit larger): 69G memory and 68 hrs run time

• Tool can handle large data volumes but large run times/memory requirements

Static DC/EM analysis Dynamic analysis CPM ( Chip Power model generation ) in one shot


Simplified User Experience Multi-pane, Multi-canvas Based Power Analysis


Enabling 3D/2.5D Designs Shared P/G network and SSN in multiple designs Needs simultaneous multi-die simulation for shared noise Concurrent analysis: (a) Full-layout visibility of all IC / interposer (b) hierarchical capacity

Model based analysis: (a) Inclusion of CPM for some dies (b) Interposer modeling


C4 PG Bump

L Metal

C Metal On die Decap

Leaf Tx R Metal R Pkg L PKG R PCB

C Pkg On Board decap

VRM Global PDN view

C4 PG Bump

L Metal

C Metal On die Decap

Leaf Tx R Metal PCB/Pkg RLC,

S parameter From Sentinel

SoC Designers view

in RedHawk

C4 PG Bump

R Pkg L PCB R PCB

C Pkg On Board decap

CPM From RedHawk

VRM PCB Designers

view in Sentinel

Only Common reference point

Model Based CPS Convergence


Chip on-die Power Grid RLC

Transistor current/cap/ESR

Open SPICE netlist format

Multi-domain, distributed model

DC to multi-GHz validity

Advanced chip excitation modes

Silicon correlated

Apache

Package/Board Model

Chip Power Model

ASIC Vendors

Apache Ecosystem

System Houses

What is CPM?


Static (Iavg, R) Frequency domain (RLC) Time-domain (I(t), RLC)

Modes

CHIP DATA

Layout (Early to Sign-off)

Library

CHIP ANALYSIS

Static Dynamic VCD

Dynamic VectorLess

Chip Power Model

What is CPM?


Traditional Die Model

RedHawk (SoC)

Layout

Chip Power Model

RLC reduction: billions of parasitics to thousands of Spice elements

Distributed with full couplings

Apache CPM™

Library

Chip

Cur

rent

Ch

ip P

aras

itics

Traditional die model

Single Lumped Model

Apache CPM™

CPM Benefits Against Traditional Models


Multi-die Analysis Framework

Memory Logic

Silicon Interposer


Apache Design Inc. ( Subsidiary of Ansys )

www.apache-da.com www.ansys.com

Extraction and simulation of complex silicon interposer structures with measurement correlation�Project BackgroundApache Power and Noise PlatformsChip/Chip Carrier/Package SoftwareInitial Test CasesBeyonce Design (Top Right) & Pins For MeasurementsBeyonce DC resistance measurements*Redhawk to Measurements ComparisonRedhawk Dynamic SimulationsPad voltage at VDDHendrix Small Test Case DetailsHendrix/Beyonce Large Test Case DetailsSimplified User Experience�Multi-pane, Multi-canvas Based Power AnalysisEnabling 3D/2.5D Designs Model Based CPS ConvergenceWhat is CPM?What is CPM?CPM Benefits Against Traditional ModelsMulti-die Analysis FrameworkApache Design Inc. ( Subsidiary of Ansys )

extraction and simulation of complex silicon interposer ... · • name and size of gds/lef file:...

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