Extreme Low-Power Mixed Signal IC Design

Armin Tajalli � Yusuf Leblebici

Extreme Low-Power MixedSignal IC Design

Subthreshold Source-Coupled Circuits

ABC

Armin TajalliEcole Polytechnique Federale

de Lausanne (EPFL)Microelectronic Systems Lab. (LSM)Station 11, 1015 LausanneSwitzerlandarmin.tajalli@epfl.ch

Yusuf LeblebiciEcole Polytechnique Federale

de Lausanne (EPFL)Microelectronic Systems Lab. (LSM)Station 11, 1015 LausanneSwitzerlandyusuf.leblebici@epfl.ch

ISBN 978-1-4419-6477-9 e-ISBN 978-1-4419-6478-6DOI 10.1007/978-1-4419-6478-6Springer New York Dordrecht Heidelberg London

Library of Congress Control Number: 2010934294

c� Springer Science+Business Media, LLC 2010All rights reserved. This work may not be translated or copied in whole or in part without the writtenpermission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York,NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use inconnection with any form of information storage and retrieval, electronic adaptation, computer software,or by similar or dissimilar methodology now known or hereafter developed is forbidden.The use in this publication of trade names, trademarks, service marks, and similar terms, even if they arenot identified as such, is not to be taken as an expression of opinion as to whether or not they are subjectto proprietary rights.

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Springer is part of Springer Science+Business Media (www.springer.com)

To my father, Hossein, my mother, Maryam,my wife, Paris, my little daughter, Ayrine andmy family: Azin, Ali, and Alaleh.

–Armin Tajalli

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Applications of Widely Adjustable Circuits and Systems . . . . . . . . . . . . 2

1.1.1 Performance Scalability and Requirements . . . . . . . . . . . . . . . . . 51.2 Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2.1 Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.2.2 Analog Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3 Organization .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Subthreshold MOS for Ultra-Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.1 MOS Technology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2 Device Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.1 I–V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.2 Second Order Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Design Considerations in Subthreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.3.1 PVT Variation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.3.2 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4 Ultra-Low-Power Design Using Subthreshold MOS .. . . . . . . . . . . . . . . . 292.4.1 MOS Transistor Leakage Mechanisms . . . . . . . . . . . . . . . . . . . . . . 302.4.2 Leakage Reduction Techniques .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.5 Impacts of Variation on Subthreshold CMOS Operation .. . . . . . . . . . . . 372.5.1 Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.5.2 Energy Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452.5.3 Optimal Design with Technology Scaling . . . . . . . . . . . . . . . . . . . 492.5.4 Supply Voltage and Threshold Voltage

Scaling for Optimal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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viii Contents

Part I Scalable and Ultra-Low-Power Digital Integrated Circuits

3 Subthreshold Source-Coupled Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.2 Conventional SCL Topology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.2.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633.2.2 Tradeoffs in Design of Strong-Inversion SCL Gates. . . . . . . . 67

3.3 Ultra-Low-Power Source-Coupled Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.3.1 High-Valued Load Device Concept . . . . . . . . . . . . . . . . . . . . . . . . . . 703.3.2 STSCL Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.4 Design Issues and Performance Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.4.1 Power-Speed Tradeoffs in STSCL . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.4.2 Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793.4.3 Replica Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833.4.4 Minimum Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843.4.5 Global Process and Temperature Variation .. . . . . . . . . . . . . . . . . 863.4.6 Effect of Mismatch on Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873.4.7 Minimum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893.5.1 Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893.5.2 Ring Oscillator and Frequency Divider. . . . . . . . . . . . . . . . . . . . . . 903.5.3 Multiplier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.6 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4 STSCL Standard Cell Library Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.2 Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

4.2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1004.2.2 Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1014.2.3 Cell Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1014.2.4 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1034.2.5 LEF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1044.2.6 Template Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

4.3 Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1054.3.1 Series–Parallel Tail Bias Transistors . . . . . . . . . . . . . . . . . . . . . . . . .1064.3.2 Constant Area Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

4.4 Demonstration Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1084.4.1 FIR Filter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1084.4.2 Sample FIR Filter Demonstrator Circuit . . . . . . . . . . . . . . . . . . . .109

4.5 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

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5 Subthreshold Source-Coupled Logic Performance Analysis . . . . . . . . . . . .1155.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1155.2 Comparison with the CMOS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

5.2.1 Ultra-Low-Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1165.2.2 Power-Speed Tradeoff in STSCL . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175.2.3 Performance Analysis of CMOS Logic Circuits . . . . . . . . . . . .1185.2.4 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

5.3 Performance Improvement Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1225.3.1 Compound Logic Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1235.3.2 Using Source-Follower Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1255.3.3 Pipelining Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

5.4 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1335.4.1 STSCL with Source-Follower Buffer . . . . . . . . . . . . . . . . . . . . . . . .1335.4.2 Pipelined Adder Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1345.4.3 Pipelined Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

5.5 Conclusions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

6 Low-Activity-Rate and Memory Circuits in STSCL . . . . . . . . . . . . . . . . . . . . .1416.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1416.2 Power Efficiency in Low Activity Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

6.2.1 STSCL Topology Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1426.2.2 CMOS Topology Performance .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1446.2.3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

6.3 Low-Leakage CMOS SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1466.4 Low Stand-By Current STSCL Memory Cell . . . . . . . . . . . . . . . . . . . . . . . .149

6.4.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1496.4.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1516.4.3 Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1526.4.4 Leakage Current Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

6.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1536.6 Observations and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Part II Scalable and Ultra-Low-Power Analog Integrated Circuits

7 Widely Adjustable Continuous-Time Filter Design. . . . . . . . . . . . . . . . . . . . . . .1617.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1617.2 Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

7.2.1 Low Power Folded-Cascode Amplifier . . . . . . . . . . . . . . . . . . . . . .1627.2.2 Widely Adjustable Two-Stage Amplifier . . . . . . . . . . . . . . . . . . . .164

7.3 Transconductor-C Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1667.3.1 Proposed Biquadratic Filter Topology .. . . . . . . . . . . . . . . . . . . . . .1667.3.2 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1707.3.3 Sixth Order gm-C Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

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7.4 MOSFET-C Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1717.4.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1727.4.2 High-Valued Pseudo-Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1727.4.3 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1757.4.4 Second Order MOSFET-C Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

7.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1787.5.1 MOSFET-C Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1787.5.2 gm-C Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1807.5.3 Figure of Merit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

7.6 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

8 Scalable Folding and Interpolating ADC Design. . . . . . . . . . . . . . . . . . . . . . . . . .1878.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1878.2 Previous Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1878.3 Folding and Interpolating Analog-to-Digital Converter .. . . . . . . . . . . . .189

8.3.1 Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1898.3.2 Building Blocks and Design Tradeoffs . . . . . . . . . . . . . . . . . . . . . .192

8.4 Design of FAI ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1988.4.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1998.4.2 Ultra Low Power Resistor Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . .2028.4.3 Comparator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2048.4.4 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

8.5 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2098.5.1 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2098.5.2 FAI ADC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

8.6 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

9 Widely Adjustable Ring Oscillator Based †� ADC . . . . . . . . . . . . . . . . . . . . .2159.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2159.2 Background .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

9.2.1 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2159.2.2 Improving the Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

9.3 Performance Scalability in Ring Oscillator Based �† ADCs . . . . . . .2189.3.1 Frequency Domain Adjustability . . . . . . . . . . . . . . . . . . . . . . . . . . . .2189.3.2 Dynamic Range Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

9.4 Top Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2239.4.1 Sources of Non-Ideality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2239.4.2 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

9.5 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2289.5.1 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2289.5.2 Logic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2319.5.3 Current-Mode Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

Contents xi

9.6 High Order Modulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2339.6.1 Analysis and Modeling .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2339.6.2 Behavioral Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

9.7 Simulations and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2409.8 Conclusion and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

10 Wide Tuning Range PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24310.1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24310.2 Wide Tuning Range PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

10.2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24410.2.2 Wide Tuning Range CPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24610.2.3 Design Issues with Wide Tune PLLs . . . . . . . . . . . . . . . . . . . . . . . .249

10.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25010.3.1 Proposed PLL Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25010.3.2 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25210.3.3 Frequency Divider and Phase-Frequency

Detector (PFD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25310.3.4 Transconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

10.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25410.5 Conclusions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

11 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26111.1 Main Contributions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26211.2 Perspectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267

List of Figures

1.1 Generic mixed-mode integrated system with a dynamicpower management for digital part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 A mixed-mode integrated system with dynamic powermanagement for the entire system .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Conceptual timing diagram for two systems, one withoutbattery management system and the other one with asystem controlling the power dissipation with respect tothe battery voltage and data throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Conceptual diagram to explain the acceptable frequencytuning range. Here, B0 represents the nominal biasingcondition and Bopt is the optimum bias point to maximizethe performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5 Power-efficient frequency-scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.6 (a) Simulated tuning range of a CMOS (8�8) Cary–Save

multiplier achieved by adjusting the power supplydesigned in CMOS 0.18 �m. The tuning range can beextended even more by increasing the supply voltage(VDD) above 0.5 V. (b) Simulated power-delay product thiscircuit versus supply voltage in different corner cases . . . . . . . . . . . . . . . . . . . 7

1.7 Programmable continuous-time integrator uses switchablecapacitors and transconductors to adjust the cutoff frequency . . . . . . . . . . . 8

1.8 A simplified switched-capacitor integrator. The capacitorCS and the switches S1 and S2 are resembling a resistance.The charge transfer of this resistance depends on theclock frequency as well as the size of CS (samplingcapacitance). Therefore, the cutoff frequency of theentire circuit depends on clock frequency and the size ofsampling capacitor as indicated in (1.3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.9 Companding technique for implementing high DR circuits [29] . . . . . . . . 10

2.1 Exponential increase of number of transistors on asingle chip thanks to the CMOS technology scaling andcomparison to the prediction made in [8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

xiii

xiv List of Figures

2.2 (a) Structure of NMOS and PMOS devices. Symbol for(b) NMOS and (c) PMOS devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3 Bias current dependence on temperature variations. In thisfigure, the bias current is normalized to the nominal biascurrent at T D 27ıC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4 Expected offset voltage at the input of a differential paircircuit by technology scaling when minimum size devicesare utilized. Data values are extracted from [13] . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.5 Dependence of bias current, transconductance, and gm=I

on gate overdrive voltage: VGS � VT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.6 ITRS predictions for device scaling and power dissipation

at 2001 [29] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.7 Leakage current sources in a MOS device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.8 I–V characteristics of an NMOS transistor and effect of

subthreshold slope factor on off current of the device . . . . . . . . . . . . . . . . . . . . 332.9 Stacking technique to reduce the leakage current. . . . . . . . . . . . . . . . . . . . . . . . . 372.10 Variation on: (a) ION current, (b) IOFF current, and

(c) delay of a NAND gate implemented in 65 nm CMOStechnology. (d) Typical value of � D ION=IOFF . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.11 A sample CMOS inverter and the corresponding Butterflycurve used for estimating NM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.12 Comparing the estimated static noise margin basedon (2.69) and transistor level simulation results. (a)The calculated VTC based on (2.69) including processvariations. (b) Static noise margin in comparison to thetransistor level simulations (c) Input–output crossoverpoint, XC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.13 (a) Parameter D versus �. (b) NM0 based on analysis incomparison to the NM0 value calculated using (2.75). Thisgraph also shows the lower limit on NM when processvariation is included. Here, VDD D 0:4 V and VT D 0:5 V .. . . . . . . . . . . . . . 43

2.14 (a) Noise margin of a subthreshold inverter biasedwith VDD D VT 0 in course of technology scaling. Thedegradation of noise margin due to process variation hasbeen also shown. (b) Minimum NMOS transistor lengthto have a positive noise margin in presence of processvariation. The results have been shown with and withoutincluding the DIBL effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.15 (a) A chain of N identical CMOS gates. Note that the typeof logic gate used in the chain is arbitrary. (b) Modelingthe current waveform .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.16 Comparing noise margin resulted from transistor levelsimulations with the results from (2.91) in 65 nm technology . . . . . . . . . . . 48

List of Figures xv

2.17 (a) Optimum energy consumption by technology scaling(˛ D 0:1=N , N D 20, CL0 D 5 fF). (b) Correspondingoperating frequency for optimum energy consumption.(c) Supply voltage in which energy consumption canbe minimized. This figure also shows the minimumacceptable supply voltage to keep the noise marginpositive. (d) Ratio of the optimum supply voltage to devicethreshold voltage by technology scaling. (e) Scaled devicelength to have a positive NM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.18 (a) Optimum energy consumption by technology scaling(˛ D 0:9=N , N D 20, CL0 D 5 fF). (b) Correspondingoperating frequency for optimum energy consumption.(c) Supply voltage in which energy consumption canbe minimized. This figure also shows the minimumacceptable supply voltage to keep the noise marginpositive. (d) Ratio of the optimum supply voltage to devicethreshold voltage by technology scaling. (e) Scaled devicelength to have a positive NM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.19 Minimum energy consumption in different technologynodes when both supply voltage and threshold voltageare optimized. The optimum values for supply voltageand threshold voltage are also shown. Here, ˛ D 0:9=N .The bottom figure shows the nominal, the best, and theworst case operating frequency of the circuits in minimumenergy consumption point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.20 Minimum energy-delay product in different technologynodes when both supply voltage and threshold voltageare optimized. The optimum values for supply voltageand threshold voltage are also shown. Here, ˛ D 0:9=N .The bottom figure shows the nominal, best, and worstcase operating frequency of the circuits in minimum EDP point . . . . . . . . 55

3.1 Design space for (a) static CMOS and (b) STSCL logic styles . . . . . . . . . . 623.2 A conventional SCL-based inverter/buffer circuit. The

switching part can be composed of a complex network ofNMOS source-coupled pairs to implement more complexlogic functions [7, 13]. The load resistances, RL, can beimplemented using PMOS devices biased in triode region.. . . . . . . . . . . . . . 63

3.3 Replica bias circuit used to control the resistivity of theload devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.4 SCL-based buffer chain to drive the load capacitance CL

at the desired data rate. The load resistance of the stage (i )is RL;i and Ci is the total capacitance seen by RL;i . . . . . . . . . . . . . . . . . . . . . 68

xvi List of Figures

3.5 Current consumption in an SCL buffer chain for differentnumber of stages n and different voltage swing valuesat the intermediate nodes (Vsw;i ) based on (3.27). In thissimulation, CL D 2 pF, Vsw;in D 0:4 V and it is assumedthat CIN should be smaller than 50fF. Inside the gray area,it is not possible to achieve the desired CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.6 (a) Conventional PMOS load device, (b) proposed loaddevice, (c) I–V characteristics of the conventional PMOSload (dotted) in comparison to the proposed device (solidline), (d) measured I–V characteristics of the proposedload device in comparison to the BSIM model (all dataobtained using 0.18 �m CMOS technology) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.7 Cross-section view of the proposed PMOS load device,showing the parasitic components that contribute to itsoperation in subthreshold regime .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.8 A very high-valued floating resistor composed of twoback to back PMOS devices: (a) circuit schematic and(b) measured I–V characteristics of the controlled floatingresistor in CMOS 0.18 �m .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.9 A subthreshold SCL gate and its replica bias circuit usedto control the output voltage swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.10 DC transfer characteristics of a STSCL gate designedin 0.18-�m CMOS and biased with ISS D100 pA,VSW D 200 mV: (a) voltage transfer characteristic and(b) DC differential voltage gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.11 Mask layout of a 3-input XOR gate showing the areaoccupied by the major components in CMOS 0.18 �m.Note that the PMOS load device with their isolated n-wellsoccupy a relatively small area compared to the NMOSlogic network and biasing transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.12 Measured gate delay for different tail bias currents in0.18-�m CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.13 DC transfer characteristics of an STSCL circuit designedin 0.18-�m CMOS technology. (a) Differential DC gainversus desired VSW and tail bias current. (b) Noise marginand output voltage swing versus VSW and tail bias current . . . . . . . . . . . . . . . 80

3.14 Mismatch effect on STSCL gate performance. Variationon gain, NM, voltage swing, and input referred offset areshown. The value of NM depends highly on the outputvoltage swing. Here, VSW D 200 mV and ISS D 100 pA for200 runs of Monte Carlo simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.15 Correlation between (a) variation on NM and offsetvoltage and (b) variation on NM and output voltage swing,based on Monte Carlo simulations in CMOS 65 nm. . . . . . . . . . . . . . . . . . . . . . 82

List of Figures xvii

3.16 Current of the load device when VSG D 0 V versustemperature for CMOS 130, 90, and 65 nm technologies.This current is mainly due to the forward-biasedsource-bulk PN junction of the PMOS load device .. . . . . . . . . . . . . . . . . . . . . . 85

3.17 (a) Variation on gate delay due to the temperaturevariations in 0.18 �m. (b) Delay variation over differentcorner cases for CMOS 65 nm .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.18 Delay variation due to the device mismatch based on(3.73). Here, it is assumed that AVT D 5[mV��m] and gatearea of PMOS load and tail bias NMOS devices are bothequal to S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.19 (a) Simulated DC transfer characteristics and DC gainof an STSCL gate biased at ISS D 1 nA. (b) Measuredtransfer characteristics of an STSCL adder stage for twodifferent supply voltages (VDD D 0:6 V and 1.0 V) anddifferent bias currents (ISS D 1; 10, and 100 nA). The testcircuit has been implemented in 0.18-�m CMOS . . . . . . . . . . . . . . . . . . . . . . . . 90

3.20 Microphotograph of the test circuits: (a) ring oscillatorand (b) frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.21 Measured oscillation frequency versus power dissipationof the 8-stage ring oscillator based on the proposed STSCLtopology for VDD D 0:3, 0.4, and 1.0 V. Correspondingpower-speed curves for a CMOS ring oscillator is shown as well . . . . . . . 92

3.22 (a) STSCL latch circuit schematic and (b) the topology ofthe divide-by-8 circuit used for measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.23 (a) Measured maximum frequency of operation versuspower dissipation of the divide-by-8 frequency dividershown in Fig. 3.22 for VDD D 0.4 V and 1.0 V. (b)Simulated maximum operating frequency of STSCLdivider in different technologies (CMOS 90, 130, and 180 nm) . . . . . . . . . 93

3.24 Photomicrograph of the measured STSCL-based (8�8) bitCarry–Save multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.25 (a) Measured total propagation delay of the proposedSTSCL multiplier versus tail bias current (ISS) fordifferent supply voltages in comparison to the simulationresults. (b) Comparing the power-delay product versusdelay for two (8 � 8) bit Carry–Save multiplier circuitsbuilt with conventional CMOS and STSCL components .. . . . . . . . . . . . . . . . 95

4.1 Sample layout of an STSCL gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1024.2 The template for placing the cell and fat pins [1, 2] . . . . . . . . . . . . . . . . . . . . . .1034.3 Footprints of the 1-level and the 2-level networks [1] . . . . . . . . . . . . . . . . . . . .1054.4 Improving the cell driving strength by multiplying the tail

bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1064.5 Scaling the tail bias current using parallel and series configurations . . . .107

xviii List of Figures

4.6 Scaling driving strength by changing the bias voltages . . . . . . . . . . . . . . . . . .1084.7 Signal flow graph of an FIR filter with N D M C 1 taps . . . . . . . . . . . . . . . .1084.8 The layout of STSCL buffer/inverter gates with different

driving strengths in CMOS 0.18 �m [2–5]. To scale thedriving strength of a cell, number of parallel PMOS loadsneeds to be increased proportional to the driving strength.Also, the number of series NMOS tail bias transistorsneeds to be reduced up to driving strength of �4, and thenfor higher current driving, the number of parallel NMOSdevices needs to be increased .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

4.9 The layout of the proposed FIR filter implemented inCMOS 0.18 �m technology based on STSCL and CMOS topologies. . .110

4.10 (a) Simulated power consumption versus operationfrequency of the STSCL and the CMOS FIR filtersin 0.18 �m CMOS. Dashed lines are representing theestimated power consumption based on the methodologyintroduced in Chaps. 2 and 5. Here, the supply voltage ofSTSCL circuit is set to be 0.5 V. (b) Simulated leakagecurrent of the CMOS FIR filter in different supply voltage values . . . . . .111

4.11 Layout of AND2, full adder (FA), and XOR2 (from left toright) implemented in CMOS 90 nm. The same cell is usedfor different driving capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

4.12 Layout of the proposed FIR filter implemented in CMOS90 nm using STSCL (left), and CMOS (right) topologies . . . . . . . . . . . . . . . .112

5.1 Simulated turn-on to turn-off current ratio (� D ION=IOFF)of a static CMOS inverter gate implemented in 65-nmCMOS technology in different corner cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

5.2 (a) A chain of CMOS gates with logic depth of N .(b) Current drawn from supply source by one of the gates . . . . . . . . . . . . . . .119

5.3 Power consumption of a chain of CMOS gates versusactivity rate (˛) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

5.4 Variation of the critical activity rate (˛C ) as a function ofVDD for different technology nodes .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

5.5 Peak current and leakage current of a CMOS inverter gateas a function of VDD in 65-nm technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

List of Figures xix

5.6 (a) Simulated power consumption versus operationfrequency for CMOS and STSCL XOR gates with logicdepth of N D 20. Note that CMOS power consumptioncannot be reduced beyond a certain level due to leakage.(b) Maximum logic depth for which STSCL topologyexhibits less power consumption compared to the CMOStopology based on (5.9) (dashed lines) in comparison tothe simulation results. The results are shown for both lowVT (top) and high VT devices (bottom) in 65-nm CMOStechnology. XOR logic gates are used for this comparison.Here, VDD;STSCL D 400 mV and VSW D 200 mV .. . . . . . . . . . . . . . . . . . . . . . . .122

5.7 Measured power consumption versus operating frequencyfor two (8�8) STSCL and CMOS array multipliers. Thesimulations for both topologies are plotted for differentprocess corners and temperatures.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

5.8 (a) Compound STSCL gate (AND operation followed byXOR gate). (b) Performance improvement in an (8�8)multiplier circuit using compound STSCL gates . . . . . . . . . . . . . . . . . . . . . . . . .124

5.9 (a) Generic STSCL gate uses source follower buffer at theoutput (SCLSFB) to improve the power–delay product ofthe gate. (b) Design of standard library cells with differentdriving strengths based on SCLSFB topology. CM standsfor the total parasitic capacitance seen by each output nodeof the STSCL core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

5.10 (a) Total delay improvement using source-follower bufferat the output of STSCL circuit in equal total powerconsumption based on transistor level simulations. Datapoints with a delay ratio of larger than unity representdelay improvement (reduction). (b) Transient simulationresults: output waveforms (top) and supply current(bottom) for an SCLSFB topology (ISS D 10 nA).(c) Delay reduction (�d ) for different �I values comparedto the �d;Max calculated based on (5.20) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.11 Pipelining technique for improving the activity rate inSTSCL topology. (a) Single stage pipelined gate andtiming diagram. (b) Multi-stage pipelined logic . . . . . . . . . . . . . . . . . . . . . . . . . .131

5.12 (a) STSCL full adder and keeper stage. Here, the tailcurrent bias VBN is switched according to CK (or CK)while VBN0 is kept as a constant bias. (b) Simulatedoutput of the pipelined FA chain showing the holding andtracking modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

xx List of Figures

5.13 (a) Photomicrograph of the test chip implementedin 0.18-�m technology. (b) Measured oscillationfrequency of STSCL ring oscillator in comparison to thesimulation results at different temperatures. (c) Total delayimprovement for total bias current per stage of 1 nA and10 nA. Each ring oscillator is constructed of 8 delay cells.Data points with a delay ratio of larger than unity representdelay improvement (reduction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

5.14 (a) Test chip photomicrograph. Measured output ofthe pipelined full adder chain in comparison to the(b) input data and (c) reference clock. Here, VDD D 1 V,VSW D 0:2 V, ISS D 1 nA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

5.15 (a) Measured delay versus tail bias current: total delayof simple adder chain and stage delay in pipelined adderchain. In both cases, the delay figure corresponds to thetime period between two consecutive inputs. The effectiveoperating frequency improves by a factor of 14 withpipelining. (b) Measured power–delay product for the twoadder topologies. The pipelined adder topology achievesa very significant reduction of PDP, over a wide range ofoperating frequencies. (c) Power–frequency improvementachieved by pipelining technique .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

5.16 (a) Section of the parallel multiplier where the signal flowis regulated using two-phase micro-pipelining techniquefor improving the performance of SCL gates. Note thatevery FA stage output is followed by a keeper/latchstage. (b) Eye diagram of the output of the multipliercircuit. This plot shows the output after SCL-to-CMOSlevel converter circuit. Input is a 27 � 1 pseudo randombit stream (PRBS). Here, the period of input data isTp D 1:5 �s, ISS D 10 nA, and ISS;L D 100 pA; i.e., thekeeper stages dissipate only 1% of the power dissipated bythe FA stages. (c) Power–frequency improvement that canbe achieved in the (8�8) carry-save multiplier circuit, byusing shallow pipelining with keeper-latch stages . . . . . . . . . . . . . . . . . . . . . . . .137

6.1 Simulated power consumption of a chain of gates in 65-nmCMOS technology based on static CMOS (solid line) andSTSCL topologies (dashed line). Variation of the powerconsumption due to the process corners and temperaturevariation is shown with standard-VT (a) and high-VT (b)CMOS. Operating conditions: VDD.CMOS/ D 300 mV andVDD.STSCL/ D 400 mV .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

List of Figures xxi

6.2 (a) Conventional 6 transistor SRAM cell and (b) leakagepaths in this configuration. (c) 10T SRAM for subthresholdoperation [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

6.3 Schmitt trigger based SRAM bitcell introduced in [17]operating at VDD D 160 mV .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

6.4 (a) Schematic of a STSCL inverter. (b) The core ofthe proposed memory cell based on STSCL topology.(c) Completed memory cell. In this schematic, M10 isshared among all the memory cells on a word line to save area . . . . . . . . .150

6.5 (a) Circuit schematic, and (b) timing diagram of theSTSCL-based SRAM cell. (c) Simulated butterfly curve ofa cell in CMOS 65 nm (showing different corner cases) forVDD D 500 mV and VSW D 200 mV.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

6.6 Sense amplifier used to reconstruct the data at the outputof memory cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

6.7 Leakage detector and bias current generator circuit schematic . . . . . . . . . .1536.8 The chip photomicrograph of the ultra low stand-by

(leakage) current SRAM array (1 kb block) fabricated withconventional 0.18-�m CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

6.9 Measured (a) butterfly curves and (b) statisticaldistribution of the SNM, for the proposed SRAM cell(ICORE D 10 pA, VSW D 200 mV, and VDD D 500 mV) . . . . . . . . . . . . . . . . . .154

6.10 Measured variation of the SNM versus VSW (forICORE D 10 pA) and variations of SNM versus tail biascurrent (ICORE) for VSW D 200 mV.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

6.11 Variation of the idle power consumption (per cell) versusoperating frequency, comparing this work with the SRAMcell presented in [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

7.1 A conceptual block diagram of a widely adjustablemixed-mode integrated circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

7.2 (a) Simplified replica bias circuit. (b) Conventional foldedcascode amplifier circuit topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

7.3 Modified current mirror schematic to be used in very lowbias current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

7.4 (a) Circuit schematic of the amplifier. (b) Simulatedunity gain bandwidth (UGBW) and phase margin of theamplifier for different current bias values. In this plot,IC is the reference current value used to change the filtercutoff frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

xxii List of Figures

7.5 (a) Single stage differential operational transconductanceamplifier (OTA) can be used as a widely adjustabletransconductor. Typical I/V characteristics of thedifferential pair OTA also is shown. (b) Maximum voltageswing at the input of differential pair OTA to have anonlinearity less than 5% at the output current (nominal.W=L/ D 1:0 �m/0.4 �m) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

7.6 Biquadratic gm-C filter: (a) conventional topology and(b) modified topology with improved linearity performance.. . . . . . . . . . . .168

7.7 Comparing the linearity performance of the twobiquadratic filters shown in Fig. 7.6 based on behavioralmodeling. Here, it is assumed that the input differentialpair transistors are biased in subthreshold regime andtransconductance can be calculated using (7.15) . . . . . . . . . . . . . . . . . . . . . . . . .169

7.8 Linearized transconductance suitable for wide tuningrange applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

7.9 Tunable active-RC (MOSFET-C) filter using a variableresistor. The power consumption of the amplifier isscalable with respect to the filter cutoff frequency.. . . . . . . . . . . . . . . . . . . . . . .172

7.10 High-valued resistance implementation based onsubthreshold PMOS device: (a) conventional PMOSdevice and its I/V characteristics, (b) proposed PMOSdevice and its I/V characteristics with extended linearityrange [9], (c) I/V characteristics of the devices shownin (a) and (b). (d) Measured I/V characteristics of theproposed floating resistor for VSD < 0 V, and VSD > 0 V.. . . . . . . . . . . . . . . .173

7.11 Proposed floating resistance: (a) circuit schematic,(b) measured I/V characteristics of the proposedconfiguration for different VC values, and(c) measured resistance of the proposedfloating resistor with respect to the gate-sourcevoltage of MN (VC D VGS;MN D VSG;MP1;2).Here, .W=L/pMOS D 0:24 �m=0:40 �m and.W=L/nMOS D 1:0 �m=0:40 �m .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

7.12 High-valued floating resistance with improved linearity . . . . . . . . . . . . . . . . .1757.13 Extreme high-valued resistance using negative VSG values . . . . . . . . . . . . . .1767.14 A second order MOSFET-C filter. All the resistors are

implemented using the proposed floating resistor shown inFig. 7.11a. Quality factor of this filter can be tuned throughR2 independent to the cutoff frequency. In this design,R1 D R3 D R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

7.15 Chip photomicrograph of the proposed filters implementedin 0.18 �m CMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

List of Figures xxiii

7.16 Measured MOSFET-C filter characteristics: (a) frequencytransfer characteristics. (b) cutoff frequency versus tuningcurrent in comparison to the simulation results, and(c) Q tuning by changing R2 value at IC D 1 nA. . . . . . . . . . . . . . . . . . . . . . . .179

7.17 Measured (a) third order intermodulation intercept pointand (b) noise of the proposed MOSFET-C filter . . . . . . . . . . . . . . . . . . . . . . . . . .180

7.18 Measured gm-C filter characteristics: (a) frequencytransfer characteristics and (b) cutoff frequency versustuning current in comparison to the simulation results . . . . . . . . . . . . . . . . . . .181

7.19 Measured: (a) third order intermodulation interceptpoint (IP3) and (b) noise of the proposed gm-C, fordifferent filter cutoff frequencies. (c) Third order harmonicdistortion (HD3) of the proposed gm-C filter in comparisonthe conventional topology when IC D 1 nA, and fin D fc=4 . . . . . . . . . . .181

7.20 FOM comparison to some other reports versus normalizedfilter area (area is normalized to the order of the filter). Thedata points used in this figure are extracted from [11] and [12] . . . . . . . . . .183

8.1 Topology of a SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1888.2 Topology of a FAI ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1908.3 Performance improvement of the reported FAI ADCs

versus time and technology nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1918.4 Ideal resistor ladder to generate reference voltages . . . . . . . . . . . . . . . . . . . . . . .1938.5 (a) INL degradation due to the mismatch on resistors

of reference voltage ladder simulated in MATLAB.(b) ˛Ladder as a function of ADC resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

8.6 Differential pair based pre-amplifier and comparator:(a) pre-amplifier, (b) a comparator consisting ofpre-amplification and latch stages, and (c) a simple modelfor the proposed three stage circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

8.7 Comparator offset effect on INL of the ADC deducedfrom MATLAB behavioral modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

8.8 Minimum achievable FOM using flash topology for ADCbased on behavioral modeling. This figure also shows thepower consumption (excluding encoder part) and the totalinput capacitance of the ADC as a function of Nb . . . . . . . . . . . . . . . . . . . . . . . .199

8.9 Folding scheme: four folders are used to generate fourfolded signals. Each two consecutive folded signals can beused to generate interpolated signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

8.10 Sample folder circuit (NF D 3) uses nonlinear transconductors . . . . . . . .2008.11 (a) Current mode interpolator. (b) Merged folder and

interpolator stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2028.12 Inherent INL of a current-mode interpolator biased in

subthreshold regime .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

xxiv List of Figures

8.13 Low power resistor ladder implementation: (a) idealresistor ladder used to generate reference voltages,(b) high-value resistance based on subthreshold PMOSdevice, (c) biasing the proposed high-value resistancewhere the resistivity can be adjusted through IRES, and(d) compact resistor ladder sharing the same biasingcircuitry for more than one resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

8.14 (a) High valued load resistance. (b) Decouplingthe parasitic capacitance of the well-substrate fromoutput node. (c) Subthreshold pre-amplifier stage. (d)Improvement of frequency response through parasiticcapacitance decoupling.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

8.15 Error correction and encoder using pipelined STSCLtopology. Waveforms of the bit synchronization block.MSB, MSB�1, and MSB�2 are the outputs. C00 is thesynchronization bit and CP1–CP8 are cycle pointers . . . . . . . . . . . . . . . . . . . . .206

8.16 Democratic cell and its layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2078.17 Cyclical code to binary code converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .2088.18 Control of power consumption with respect to the

operating frequency in the proposed subthresholdsource-coupled FAI ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

8.19 Maximum operation frequency of thedigital section as a function of tail biascurrent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

8.20 Photomicrograph of the proposed chip implemented in0.18-�m CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

8.21 Measured differential non-linearity (DNL) and integralnon-linearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

9.1 First order �† modulator topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2169.2 Timing operation of a ring oscillator based quantizer (ROQ) . . . . . . . . . . . .2179.3 (a) STSCL delay cell and replica bias circuit to generate

bias voltage for PMOS and NMOS transistors. (b) Sampledifferential ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

9.4 Implementation of ring oscillator based quantizer withoutthe need to counter as proposed in [6]. The topology ismodified to make it suitable for scalable DR ADCs . . . . . . . . . . . . . . . . . . . . . .221

9.5 (a) SNDR versus input signal amplitude based onbehavioral modeling of a first order R�† in MATLAB(here: Nd D 15, and OSR D 64). (b) SNDR versusnumber of delay elements in the ring oscillator(here: Ain=0:5, and OSR D 64) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

9.6 The effect of sampling clock jitter on SNDR based onbehavioral modeling in MATLAB for a first order R�† modulator . . . .225

9.7 Sampling the output of ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

List of Figures xxv

9.8 SNDR of a first order quantizer when: �OSC D 0:001td ,�CK D 0:001Ts, and �td D 0:01td . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

9.9 Effect of delay mismatch on first order quantizer based onbehavioral modeling in MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

9.10 Effect of oscillator jitter on first order quantizer based onbehavioral modeling in MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

9.11 A slice of the circuit showing part of ring oscillator anddigital part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

9.12 Schematic of a companding current-mode integratoradopted from [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

9.13 Circuit diagram of the current steering DAC anddifferential current-mode integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

9.14 Discrete-time and continuous-time �† modulators . . . . . . . . . . . . . . . . . . . . . .2349.15 Block diagram of a third order R�† modulator: (a) based

on DT integrators, (b) based on CT integrators. (c) Modelof a ROQ .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

9.16 Performance of a third order R�† based on behavioralmodeling in MATLAB: (a) Effect of sampling clockjitter on SNDR. (b) Effect of leaky integrator on SNDR.(c) Effect of DAC component mismatch on SNDR, withand without DWA. (d) Effect of delay element mismatchon SNR and SNDR. (e) Effect of ring oscillator jitter onsystem performance. (f) SNR and SNDR of the systemincluding all nonideal effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

9.17 (a) Chip phot and mask layout of the test chip fabricated in90-nm CMOS technology. (b) Mask layout of the quantizer circuit . . . . .240

9.18 Simulated supply current consumption of the R�†

modulator for ISS.nom/ D 1 nA. The variation on supplycurrent is about 15% of the total circuit current consumption . . . . . . . . . . .241

9.19 Measurement results in different sampling frequencies:(a) SNR and SNDR values and (b) Power dissipation ofthe modulator. Here: OSR D 64, AIN D �20 dB, VDD D 1:2 V .. . . . . . . . .241

10.1 Conventional charge-pump PLL (CPLL) topology .. . . . . . . . . . . . . . . . . . . . . .24410.2 Charge pump circuit with programmable bias current. . . . . . . . . . . . . . . . . . . .24810.3 (a) Transient loop response to the variation at the input

frequency of the PLL. (b) The effect of small loop filterbandwidth with discarding the desirable component at theoutput of PFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

10.4 Topology of the proposed self-biased adaptive bandwidth PLL . . . . . . . . .25110.5 Current-controlled ring oscillator structure uses STSCL

cells as delay stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25310.6 Simulated tuning range of STSCL ring oscillator with 8

and 24 delay elements designed in 0.13- �m CMOS technology .. . . . . . .253

xxvi List of Figures

10.7 Frequency divider circuit: (a) STSCL latch circuitschematic and (b) Frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

10.8 (a) Wide swing transconductor. (b) I–V characteristics ofthe transconductor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

10.9 Simulated transient response of the PLL in different frequencies . . . . . . .25510.10 Simulated transient response of the PLL when there is a

jump at the input frequency. In this simulation, the initialinput frequency is f1 D 1:12 MHz and then there is a jumpto f2 D f1=200 D 5:6 kHz. At the end of simulation,again there is a jump back to f1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

10.11 Mask layout of the proposed wide tuning range PLLimplemented in 0.13- �m CMOS technology andoccupying 300 �m� 200 �m area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

10.12 Measured rms supply current consumption versusoscillation frequency for two different loop-divider values . . . . . . . . . . . . . .257

List of Tables

4.1 Specifications of the FIR filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

6.1 Recently reported low-leakage SRAM cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1486.2 Performance summary for STSCL SRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . .156

7.1 Specifications of the Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

8.1 Reported ultra low power ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

9.1 Parameter definition in CCO-based R�† ADC . . . . . . . . . . . . . . . . . . . . . . . . . .2209.2 Predicted SNR for different sets of parameters (OSR D 128) . . . . . . . . . .237

10.1 Summary of the main design parameters of wide tuningrange CPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

xxvii

Acknowledgments

Many people have helped us in preparing this book. Professor Eric Vittoz (EPFL& CSEM, Switzerland) has kindly supported this work by his valuable hints andfeedbacks. His deep knowledge in the field of Microelectronics provided this op-portunity for us to understand and go deeper into the subject. Some parts of thiswork are mainly devoted to close collaboration with Prof. Elizabeth J. Brauer (NorthArizona University) and Prof. Massimo Alioto (University of Siena), and we wouldlike to appreciate them for their very useful hints and helps.

We would also like to appreciate all the people who have helped us accomplishthis work. Special thanks goes to Stephane Badel for his very valuable help duringphysical design of test chips; Milos Stanisavljevic, Michele Mercaldi, and BertrandRey for their contribution in design of multiplier circuit; Mohammad Beikahmadifor design of ADC encoder and standard cell libraries; Nikola Katic for behavioralmodeling of �† modulator; and Sylvain Hauser who provided the test setups forprototype measurements.

We would also like to appreciate Alain Vachoux and Alexandre Schmid fortheir kind technical support during this work. We are grateful to our colleaguesin Microelectronic Systems Laboratory (LSM) for the very nice time and fruitfuldiscussions and collaborations: Thomas Liechti, Vahid Majidzadeh Bafar, TorstenMahne, Milos Stanisavljevic, Hossein Afshari, Yuksel Temiz, Niel Joye, FengdaSun, and Alessandro Cevrero.

xxix

Acronyms

�† Delta-sigma modulatorADC Analog-to-digital data converterAmp, AMP AmplifierAMS Analog-mixed-signalASIC Application specific integrated circuitBJT Bipolar junction transistorsBMS Battery management systemBW BandwidthCAD Computer aided designCCO Current-controlled oscillatorCK, CLK Clock signalCML Current-mode logicCMOS Complementary MOSCPC Charge-pump circuitCT Continuous-timeDAC Digital-to-analog date converterDEM Dynamic element matchingDFF D-type flip-flopDIBL Drain-induced barrier loweringDPM Dynamic power managementDT Discrete-timeDR Dynamic rangeDRC Design rule checkDVS Dynamic voltage scalingDWA Dynamic weighted averagingEDP Energy-delay productFAI Folding and interpolating ADCFoM Figure of meritFIR Finite impulse response (digital filters)FN Fowler–NordheimFPAA Field programmable analog arrayFPGA Field programmable gate arraygm-C transconductance-C filter

xxxi

xxxii Acronyms

HDL Hardware design languageHVT High threshold voltage MOS deviceIC Integrated circuitIC Inversion coefficientIIR Infinite impulse response (digital filters)LER Line edge roughnessLSB Least significant bitLVS Layout versus schematic checkLVT Low threshold voltage MOS deviceMCML MOS current-mode logicMI Medium inversionMOS Metal-oxide-semiconductor solid-state deviceMOSFET Metal-oxide-semiconductor field-effect transistorMOSFET-C MOSFET-C filter continuous-time topologyMSB Most significant bitMTCMOS Multi-threshold CMOS technology/topologyNM Noise marginNRZ Nonreturn to zeroNTF Noise transfer functionOp Amp Operational amplifierOSR Over-sampling ratioOTA Operational transconductance amplifierPAR Place and routPdiss Power dissipationPDP Power-delay productPFD Phase-frequency detectorPLL Phase-locked loopPVT Process, voltage (supply), and temperature variationR�† Ring oscillator based delta–sigma modulatorRB Replica biasRCX Resistor/capacitor extractorRD Read signal in memoryRDF Random dopant fluctuationREF Reference (voltage, current, frequency, etc.)RMS Root mean squareROC Ring oscillator based quantizerRZ Return to zeroSA Sense amplifierSCE Short channel effectSCL Source-coupled logicSFB Source follower bufferSI Strong inversionSNDR Signal-to-noise and -distortion ratioSNM Static noise marginSNR Signal-to-noise ratio

Acronyms xxxiii

SRAM Static random access memorySTF Signal transfer functionSTSCL Subthreshold source-coupled logicUDSM Ultra-deep-sub-micron technologyULP Ultra-low powerVCO Voltage-controlled oscillatorVHDL Versatile hardware design languageVLSI Very large scale integrationVT , VTH Threshold voltage of MOS devicesWI Weak inversionWR Write signal in memoryWSN Wireless sensor networkXOR Exclusive-or logic gate