ez80f92 flash moduletable 1 lists the installed components of the ez80f92 flash module. table 1....

PS018906-0908

Product Specification

eZ80F920020MOD

eZ80F92 Flash Module

Copyright ©2008 by Zilog®, Inc. All rights reserved.www.zilog.com

http://www.ZiLOG.com

http://www.ZiLOG.com

DO NOT USE IN LIFE SUPPORT

LIFE SUPPORT POLICYZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used hereinLife support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

Document Disclaimer©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering.

eZ80 and eZ80Acclaim! are registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.

Warning:

PS018906-0908

eZ80F92 Flash ModuleProduct Specification

iii

Revision HistoryEach instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below.

DateRevision Level Description

Page Number

September 2008 06 Removed Preliminary. Updated as per latest template and style guide changes.

All

December 2003 05 Fixed incorrect conditional indicators. All

August 2003 04 Modified to remove [email protected] and other external hyperlinks to documentation.

All

February 2003 03 Fixed incorrect hyperlinks. All

January 2003 02 Modified references for eZ80Acclaim!®. All

PS018906-0908 Revision History

PS018906-0908 Table of Contents


iv

Table of ContentsArchitectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1eZ80F92 Flash Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

eZ80F92 Flash Module Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2eZ80F92 Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Mounting the Module onto the eZ80® Development Platform . . . . . . . . . . . . . . 18ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30


1

Architectural OverviewZilog’s eZ80F92 Flash Module is a low-cost, general-purpose compact module. It is spe-cially designed for the rapid development and deployment of embedded systems. This expandable module is powered by Zilog’s latest power-efficient, high-speed, optimized pipeline architecture eZ80F92 Microcontroller Unit (MCU). This MCU, the first device in Zilog’s eZ80Acclaim!® product line, features 128 KB of on-chip Flash memory and 8 KB of on-chip SRAM.

The eZ80F92 MCU is a high-speed, single-cycle instruction-fetch MCU, which can oper-ate with a clock speed of 20 MHz. It can operate in Z80®-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB).

The rich peripheral set of the eZ80F92 Flash Module makes it suitable for a variety of applications, including industrial control, IrDA connectivity, communication, security, automation, point-of-sale (POS) terminals.

The eZ80F92 Flash Module incorporates the eZ80F92 MCU. The eZ80F92 can be replaced with the eZ80F93 MCU, which features 64 KB of internal Flash memory and 4 KB of internal SRAM.

eZ80F92 Flash Module FeaturesThe key features of eZ80F92 Flash Module include:

• eZ80Acclaim! Flash MCU with factory-default operating clock frequency at 20 MHz

• 512 KB zero-wait-state onboard SRAM

• 128 KB on-chip Flash memory

• GoldCap backup for Real-Time Clock (RTC)

• Input/Output (I/O) connector provides 24 general-purpose 5 V-tolerant I/O pinouts

• Zilog’s industry-leading IrDA transceiver—Zilog’s ZHX1810

• I/O circuit Flash programming circuitry

• Onboard connector provides I2C 2-wire SDA/SCL interface

• Onboard connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data)

• Low-cost adaptation to carrier board via two 2 x 25 pin (2.54 mm) headers

• Horizontal or vertical mounting onto the eZ80® Development Platform

• Small footprint 64 x 64 mm

• 3.3 V power supply

• Standard operating temperature range: 0 ºC to +70 ºC

Note:

PS018906-0908 Architectural Overview


2

eZ80F92 Flash Module Bill of MaterialsTable 1 lists the installed components of the eZ80F92 Flash Module.

Table 1. Bill of Materials for the eZ80F92 Flash Module

Part Number Part Name Qty.Jumper Location Manufacturer

98C0873-001 FAB, eZ80F92/93 MODULE, Rev. A 1 — Prime Technologies

35-0180-12 IC, SRAM, 512K x 8, 12 ns, 3 V, 36-SOJ 1 U1 Alliance Semi. AS7C34096-12JC

35-0016-05 IC, 74LVC04, 3.3 V, GATE, 14-SOIC 1 U2 Texas Instruments SN74LVC04AD

35-0719-00 IC, MAX6328, RESET, SOT-23 1 U4 Maxim Inc. MAX6328UR29-T

ZHX1810 IC, IR Transceiver, low profile 1 U5 Zilog Inc. ZHX1810MV115THTR

35-0062-01 IC, 74LCX32, LV, QUAD, or 14-TSSOP

1 U6 Fairchild Semi. 74LCX32MTC

EZ80F92 IC, eZ80F92AZ020SC, 20 MHZ, 100 V QFP 1 U8 Zilog Inc. EZ80F92AZ020SC

48-1013-01 DIODE, TVS ARRAY, XCVR PROT, 8-SOIC

1 U9 Semtec LCDA15C-6

17-2005-70 CAP, 1, 000 pF, 50 V, ceramic chip, 0603 5 C3, C5, C21–23

Panasonic ECJ-1VC1H102J

17-2005-66 CAP, 0.1 µF, 16 V, ceramic chip, 0603 9 C4, C6–9, C13–15,

C18

Kemet Inc. C0603C104K5RAC

17-2005-54 CAP, 0.01 µF, 50 V, ceramic chip, 0603 1 C10 Panasonic ECJ-1VB1C103K

17-2005-83 CAP, 0.33 µF, 16 V, ceramic chip, 0603 1 C11 Panasonic ECJ-1VF1C334Z

17-2005-39 CAP, 560 pF, 50 V, ceramic chip, 0603 1 C12 Panasonic ECJ-1VC1H561J

17-2001-03 CAP, 12 pF, 50 V, ceramic chip, 0603 4 C16, C17, C20, C24

Panasonic ECJ-1VC1H120J

15-0100-01 CAP, 1.10 F, 5.5 V, GOLD, SD, COIN 1 C19 Panasonic EEC-SOHD104V

48-0030-04 Diode, Schottky, Power rectifier, SMT 1 D1 On Semiconductor MBR0520LT1



3

46-3001-03 Resistor, 10 kΩ, 1%, 1/16 W, 0603 SMT 9 R1, 11, 12, 17, 19, 29, 30, 34, 36

Sprague 420CK472X2PD

46-3000-00 Resistor, 0 Ω, 1%, 1/16 W, 0603 SMT 2 R2, C25 "

46-3000-71 Resistor, 2.21 kΩ, 1%, 1/16W, 0603 SMT 3 R3, R10, R33

"

46-3000-35 Resistor, 68 Ω, 1%, 1/16 W, 0603 SMT 1 R5 "

46-1005-03 Resistor, 2.7 Ω, 5%, 1/4 W, 1206 SMT 1 R6 "

46-3001-03 Resistor, 4.75 kΩ, 1%, 1/16 W, 0603 SMT 4 R7, 8, 13, 22

"

46-3000-27 Resistor, 33.2 Ω, 1%, 1/16 W, 0603 SMT 1 R9 "

46-3000-39 Resistor, 100 Ω, 1%, 1/16 W, 0603 SMT 5 R20, 21, 26, 28, 32

"

46-3000-80 Resistor, 4.99 kΩ, 1%, 1/16 W, 0603 SMT 1 R23 "

46-3000-07 Resistor, 8.2 Ω, 1%, 1/16 W, 0603 SMT 2 R24, R25 "

46-3001-51 Resistor, 1M Ω, 1%, 1/16 W, 0603 SMT 1 R27 "

23-0000-10 Internal crystal, 20.0000 MHz, SER/RESN, HC-49S

2 Y1, Y2 Fox Series HC-49S 20.0000 MHz

23-0006-00 Internal crystal, 32.768 kHz, SER/RESN, TF CASE

1 Y3 NDK MX-38

21-0055-02 Connector, HDR/PIN,. 025SQ, double row 2 JP1, JP2 "

Table 1. Bill of Materials for the eZ80F92 Flash Module (Continued)

Part Number Part Name Qty.Jumper Location Manufacturer



4

eZ80F92 Controller FeaturesThe key features of eZ80F92 include:

• The eZ80F92 device contains 128 KB of Flash memory and 8 KB of SRAM

• Single-cycle instruction fetch, high-performance, and pipelined eZ80® CPU core

• Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control

• Two Universal Asynchronous Receiver/Transceivers (UARTs) with independent baud rate generators and support for 9-bit operation

• Serial Peripheral Interface (SPI) with independent clock rate generator

• I2C with independent clock rate generator

• Infrared Data Association (IrDA)-compliant infrared encoder/decoder

• New Direct Memory Access (DMA)-like eZ80 CPU instructions for efficient block data transfer

• Glueless external memory interface with four chip selects, individual wait state gener-ators, and an external WAIT input pin—supports Intel- and Motorola-style buses

• Fixed-priority vectored interrupts (both internal and external) and interrupt controller

• RTC with an on-chip 32 kHz oscillator, selectable 50/60 Hz input, and separate VDDpin for battery backup

• Six 16-bit Counter/Timers with prescalers and direct input/output drive

• Watchdog Timer (WDT)

• 24 bits of general-purpose input/output (GPIO)

• JTAG and ZDI debug interfaces

• 100-pin LQFP package

• 3.0 V to 3.6 V supply voltage with 5 V tolerant inputs

• Standard operating temperature range: 0 ºC to +70 ºC

All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low.

Note:



5

Block DiagramFigure 1 displays a block diagram of the eZ80F92 Flash Module.

Figure 1. eZ80F92 Flash Module Functional Block Diagram

Gold Cap 32 kHz XTAL

XTAL/Osc

eZ80 CPUReal-Time Clock

BusController

IrDATransceiver

PD

PC

PB

WatchdogTimer

I C

Power-OnReset

ZDI/JTAG

UART

SPI6 Timer

512 KBSRAM

UART

50

-Pin

Co

nn

ecto

r

24-BitGPIO

8 KBSRAM

128 KBFlash

2

50-Pin Connector



6

Pin Description

Peripheral Bus ConnectorFigure 2 displays the pin layout of the eZ80F92 Flash Module’s I/O Connector (JP1) in the 50-pin package. Table 2 on page 7 lists the pins and their functions.

Figure 2. eZ80F92 Flash Module Peripheral Bus Connector Pin Configuration

A0

A2

A4

A6

A8

A10

CS2

D3

A17A5

V3.3_EXT

GND_EXT

A7

A22

A1

A18 A16

GND_EXT

RD

D5

GND_EXT

A9

A23CS1

A13

A11

D0

A19

D6

BUSACK

V3.3_EXT

CS0

INSTRD

A15

D1

A14

A3

D4

D7IOREQ

A21

GND_EXTMREQ

A12A20

DIS_FLASH

BUSREQWR

D2

DIS_ETH

JP1

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

PS018906-0908 Pin Description


7

Table 2. eZ80F92 Flash Module Peripheral Bus Connector Pin Identification*

Pin No. Symbol

Pull Up/Down* Signal Direction Comments

1 A6 Bidirectional

2 A0 Bidirectional

3 A10 Bidirectional

4 A3 Bidirectional

5 GND VSS/Ground (0 V).

6 VDD 3.3 V Supply Input Pin.

7 A8 Bidirectional

8 A7 Bidirectional

9 A13 Bidirectional

10 A9 Bidirectional

11 A15 Bidirectional






17 A2 Bidirectional

18 A1 Bidirectional



21 A4 Bidirectional


23 A5 Bidirectional


25 DIS_ETH PU 10 kΩ Input This pin is not used on the eZ80F92 Flash Module. However, it is connected to the pad of the CS8900 EMAC footprint.

26 DIS_FLASH PU 10 kΩ Input This pin is not used on the eZ80F92 Flash Module. However, it is connected to the pad of the external Flash footprint.



8


28 VDD 3.3 V supply input pin.



31 CS0 Output

32 CS1 Output

33 CS2 Output

34 D0 PU 4k7 Bidirectional








42 D6 Bidirectional

43 MREQ Bidirectional

44 IORQ Bidirectional


46 RD Bidirectional

47 WR Bidirectional

48 INSTRD Output

49 BUSACK Output

50 BUSREQ PU 2k2 Input

* External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive lev-els to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the eZ80CLK output can be de-activated via software in the eZ80F92 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except otherwise noted.

Table 2. eZ80F92 Flash Module Peripheral Bus Connector Pin Identification* (Continued)

Pin No. Symbol

Pull Up/Down* Signal Direction Comments



9

I/O ConnectorFigure 3 displays the pin layout of the eZ80F92 Flash Module’s I/O Connector (JP2) in the 50-pin package. Table 3 on page 9 lists the pins and their functions.

Figure 3. eZ80F92 Flash Module I/O Connector Pin Configuration

Table 3. eZ80F92 Flash Module I/O Connector Pin Identification*

Pin No. Symbol

Pull Up/Down

Signal Direction Comments

1 PB7 Bidirectional

2 PB6 Bidirectional

3 PB5 Bidirectional

4 PB4 Bidirectional

5 PB3 Bidirectional

6 PB2 Bidirectional

7 PB1 Bidirectional

PB1PB3

PB5PB7

PC1PC3PC5PC7

GND_EXT

PD1PD3PD5

PD7

DIS_IRDACS3

EZ80CLK

V3.3_EXT

FLASHWE

NMI

WAITGND_EXT

PB0PB2PB4PB6

GND_EXT

PC2PC4

RTC_VDD

PD0PD2PD4

PD6

GND_EXT

IICSCLIICSDA

TDITDOTRIGOUT

TCK TMS

RESET

GND_EXT

HALT_SLPV3.3_EXT

PC6

PC0

JP2

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50



10

8 PB0 Bidirectional


10 PC7 Bidirectional








18 PD7 Bidirectional




22 PD4 PD 4k7 Bidirectional





27 TDO Output JTAG Data Output pin.

28 TDI/ZDA Input JTAG Data Input pin.

ZDA Bidirectional ZDI Data I/O.


30 TRIGOUT Output Active High trigger event indicator.

31 TCK PU 10 kΩ Input JTAG Input. High on reset enables ZDI mode; Low on reset enables OCI debug.

32 TMS PU 10 kΩ Input JTAG Test Mode Select Input.

33 RTC_VDD RTC supply from GoldCap (or external battery).

34 EZ80CLK Output 20 MHz synchronous CPU clock output.

Table 3. eZ80F92 Flash Module I/O Connector Pin Identification* (Continued)

Pin No. Symbol

Pull Up/Down




11

35 SCL PU 4k7 Bidirectional I2C Bus Clock.


37 SDA PU 4k7 Bidirectional I2C Data Clock.


39 FlashWE PU 10 kΩ Input This pin has no function on the eZ80F92 Flash Module. It is pulled up to VDD and a connection is available on the external Flash memory pads.


41 CS3 Output Chip select for onboard or external devices; CMOS output 3.3 V.

42 DIS_IRDA PU 10 kΩ Input Low disables onboard IRDA transceiver to use PD0/PD1 UART pins externally.

43 RESET PU 2k2 Bidirectional Reset Output from module or push-button reset.

44 WAIT PU 2k2 Input Driving the WAIT pin Low forces the CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write opera-tion.



47 HALT_SLP Output, Active Low

A Low on this pin indicates that the CPU enters either HALT or SLEEP mode because of execution of either a HALT or SLP instruction.

48 NMI PU 10 kΩ Schmitt_Trigger Input, Active Low

The NMI input is a higher priority input than the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt_Trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being con-nected to the NMI input of the CPU.



Pin No. Symbol

Pull Up/Down




12

50 Reserved

* External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the eZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except otherwise noted.


Pin No. Symbol

Pull Up/Down




13

Onboard Component Description

Logic-Level I/Os

The I/O connector features 24 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the GPIO pins support dual mode functions (SPI, Timer I/O, UARTs, and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80F92 dual modes, refer to eZ80F92/eZ80F93 Product Specification (PS0153).

Onboard Battery Backup

An onboard 0.1 F capacitor (GoldCap) is used to bridge power outages of 2–4 hours if the power supply to the module is disconnected. The capacitor is charged to 3.1 V during nor-mal operation and is discharged through the on-chip RTC. The VRTC pin is available on the I/O connector of the module to connect external components to a power supply or to a larger GoldCap.

Do not connect a Lithium Battery to the GoldCap capacitor, because onboard charging circuitry for the capacitor can destroy the lithium battery.

Memory

The eZ80F92 Flash Module offers external SRAM memory and Flash memories. The wait states selectable in the eZ80F92 MCU’s support memory operations, as described in this section.

Wait StatesTo ensure that valid data is read from or written to slower memories, a number of wait states must be inserted into the memory or I/O access operations by the controller. The number of wait states that are required should be added by programming the chip select control registers. To calculate the minimum number of wait states required, see Table 4.

Table 4. Chip Frequency to Wait State Cycle Time Calculation

MHz Cycle Time

12 83.3 ns

20 50.0 ns

Caution:

PS018906-0908 Onboard Component Description


14

Static RAMThe eZ80F92 Flash Module features 512 KB of fast SRAM. Access speed is typically 50 ns, allowing zero-wait-state operation at 20 MHz. With the CPU at 20 MHz, SRAM can be accessed with zero wait states in eZ80® mode. CS1_CTL (chip select CS1) can be set to 08h (no wait states).

Flash MemoryThe eZ80F92 Flash Module allows NOR Flash memories between 4 megabits (512 KB) and 32 megabits (4 MB) to be added. The chips are housed in wide TSOP40 cases. Flash ROM access times are 55 ns to 150 ns; typically 90 ns. The Flash Boot Loader, applica-tion code, and user configuration data are held permanently in NOR Flash memory.

NOR Flash should be operated in Intel bus mode to satisfy setup and hold times and to prevent bus contention with a WRITE cycle that could possibly follow. For proper CPU operation at 20 MHz, first set the bus mode control register CS0_BMC (I/O address 0xF0h) to 82h, then set the Chip Select Control register CS0_CTL (I/O address 0xAAh) to 08h. These settings select Intel Bus Mode with two system clocks per bus cycle and zero wait states.

The eZ80F92 Flash Module features the following memory configurations:

• On-chip SRAM: 8 KB

• Off-chip SRAM: 512 KB

• On-chip Flash: 128 KB

• Off-chip Flash: 1 MB

IrDA Transceiver

An onboard IrDA transceiver (ZHX1810) is connected to PD0 (TX), PD1 (RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type 870 nm Class 1.

The receiver supply current is 90 µA to150 µA and the transmitter supply current is 260 mA when the LED is active. The IrDA transceiver is accessible via the IrDA control-ler attached to UART0 on the eZ80F92 device. The UART0 console and the IrDA trans-ceiver cannot be used simultaneously.

To use the UART0 for console or to save power, the transceiver can be disabled by the software or by an off-board signal when using the proper jumper selection. The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O con-nector Low. The shutdown is used for power savings. To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.



15

Reset Generator

The onboard Reset Generator Chip performs reliable Power-On Reset (POR). The chip generates a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80F92 Flash Module with a low-impedance output (for example, a 100 Ω push-button).

Serial Interface Ports

The controller contains two 16550-style UARTs with programmable baud rate generators. UART0 is typically used for console I/O, and initial boot code upload, or to connect remote peripherals that can be controlled and monitored via Ethernet. UART0 is con-nected to GPIO PD[0:3] on the I/O connector. There are no RS-232 level shifters on the eZ80F92 Flash Module.

Do not connect an RS-232 interface without level shifters.

UART1 can be used for modem attachment or as a communications port to a host com-puter, where the embedded Ethernet module emulates an AT-style modem for internet access. UART1 does not offer onboard RS-232 level shifters.

Note:



16

Physical Dimensions

The size of the eZ80F92 Flash Module PCB is 64 x 64 mm. See Figure 4.

Figure 4. Dimension Drawing

max.8.3 mm

2.54 mm1 1

Top View

Bus

Con

nect

or

I/O C

onne

ctor

8.5 mm

64 mm

63.5 mm

55.88 mm

9 mm

7 mm

6.2 mm2.7 mm IrDA



17

Figure 5 displays a top view of the eZ80F92 Flash Module.

Figure 6 displays a bottom view of the eZ80F92 Flash Module.

Figure 5. Top Layer

Figure 6. Bottom Layer



18

Mounting the Module onto the eZ80® Development Platform

The eZ80F92 Flash Module can be mounted in several positions. Depending on volume and area restrictions, it can be mounted horizontally or vertically with or without compo-nents between the connectors on the eZ80® Development Platform. Figure 7 displays examples.

Figure 7. Mounting Examples

Low Profile Mounting

64 mm 1 1

8.3 mmI/O

Carrier Board

H = 4.5 mm 1.7 mmBus

1

Stacked Mounting

1

Modem or Power Supply

Carrier Board

8.5 mmH = 4.5 mm

64 mm

50.5 mm max

63.5 mm

I/OBus



19

ESD/EMI Protection

The eZ80F92 Flash Module is a component that is intended to be part of a system design for end-user devices. Therefore, you must take precaution to use ESD protection on the I/O pins.

CMOS I/Os are ESD-sensitive and must be handled with care. Handling of the module should be performed in ESD-safe environments (for example, with a wrist-wrap attached). When developing applications, you must provide for proper ESD protection on external, user-accessible I/Os (for example, suppressor arrays for the I/Os).

The components are mounted on a multilayer PCB to provide a stable ground plane for onboard components. The module features several GND pins next to pins with higher switching frequency for short ground returns. If unused, the clock output can be separated from the module header by removing a series resistor on the module. Removing the series resistor further reduces electromagnetic emissions.

Absolute Maximum RatingsStresses greater than those listed in Table 5 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS).

Table 5. Absolute Maximum Ratings

Parameter Min Max Units

Standard operating temperature 0 +70 ºC

Storage temperature –45 +85 ºC

Operating Humidity (RH @ 50 ºC) 25% 90%

Operating Voltage (±5%) — 3.3 V

Caution:

Caution:



20

Power Supply

The eZ80F92 Flash Module requires a regulated external 3.3 V DC/0.5 A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3 V from 5 V or use the following switcher circuit to generate 3.3 V from unregulated 10 V to 28 V power supply.

Power connections conventional description is provided in the following table:

Figure 8 displays two power supply examples.

Connection Circuit Device

Power VCC VDD

Ground GND VSS

Figure 8. Power Supply Examples

To Module

Switcher 10—28V → 3.3V

V

10—28V

C1

1000uF

C2

100n

VIN 1 FB 4

VOUT 2

GND

3

ON/OFF

5

U1LM2575S-ADJ

D11A/30V

L1

330uH/1A

1%C3470uF/6.3V

R15k6

R23k3

3.3V

Low ESR

GND

1%

GND

V

4-6V

VI GND

VO

U1LM3940

LDO 5V → 3.3V

3.3V

GND

C3470uF/6.3V

Low ESRC1100n

GND

IN

CC

VDD

VDD


PS Schematics


21S circuiting devices are not

08 Connector

Headers

RTC_VDD

V3.3_EXTGND_EXT

D[0..7]

CLK_OUT

-RESET

IICSDAIICSCL

A[0..23]

-FLASHWE

PB[0..7]PC[0..7]PD[0..7]

-CS[0..3]

-DIS_IRDA

JTAG[1..4]

-RD-WR

-IOREQ-MREQ-INSTRD

-WAIT-HALT_SLP

-BUSACK-BUSREQ

-NMI

TDO

-DIS_FLASH

]

.4]

E

D

T

KQ

LP

3.3ND

018906-0908

chematicsFigure 9 through Figure 17 on page 29 displays the layout of the eZ80F92 Flash Module. Ethernet and external Flashloaded on the eZ80F92 Flash Module. However, these devices appear in the following schematics for reference.

Figure 9. eZ80F92 Flash Module Schematics—Top Level

07

09

03

04

05

02

06

Ethernet

CS8900ASD[0..7]

-ETHRD-ETHWR

-SLEEP-ACTIVE

ETHIRQ

SA[0..3]

IOCHRDY

CPU

eZ80

D[0..7]

A[0..23]

-RD-WR

IICSDAIICSCL

-RESET

CLK_OUT

-BUSREQ-BUSACK

-IOREQ-MREQ

-INSTRD

-WAIT-HALT_SLP

-NMI

PB[0..7]

PC[0..7]

PD[0..7]

JTAG[1..4]

-CS[0..3]

RTC_VDD

TDO

Power

PowerSupply

GND

V3.3

ROM

NOR-FlashD[0..7]

A[0..23]

-RD-WR

-CSFLASH

-RESFLASH

-FLASHWE

Peripherals

Reset

-RESETIRDA_TXDIRDA_RXD

IRDA_SD

Logic

CTRL-Logic

-RD

-WR

-ET

HR

D-E

TH

WR

D[0

..7]

SD

[0..7

]

A[0

..23]

SA

[0..3

]

ET

HIR

Q-S

LEEP

-AC

TIV

E

-DIS_IRDA

IRDA_SD

IRDA_TXDIRDA_RXD

-CSFLASH

-RESFLASH

PD[0..7]

-CS[0..3]

-RESET

-DIS_FLASH

IOC

HR

DY

-WAIT

RAM

SRAM

D[0..7]

A[0..23]

-RD-WR

-CS1

V3.3

GND

-RESETIRDA_TXDIRDA_RXDIRDA_SD

D[0..7]

A[0..23]

A[0..23]

-CSFLASH

-RESFLASH

-FLASHWE

-WR

-WR

-RD

-RD

D[0..7]

-CS1

-IOREQ-MREQ-INSTRD

-WAIT-HALT_SLP

-BUSREQ-BUSACK

-NMI

CLK_OUT

RTC_VDD

IICSDAIICSCL

PB[0..7]

PC[0..7]

JTAG[1..4]

D[0..7]

A[0..23]

-CS[0..3

JTAG[1.

-FLASHW

RTC_VD

-RESET

CLK_OU

-RD-WR

-NMI

-BUSAC-BUSRE

-IOREQ-MREQ-INSTRD

-WAIT-HALT_S

IICSCLIICSDA

PB[0..7]PC[0..7]PD[0..7]

ETHIRQ-SLEEP-ACTIVE

-CSFLASH

-WR

-RESET

-ETHWR

-AC

TIV

ESA[0..3]

PD[0..7]

-RESFLASH

IRDA_TXD

IRDA_SD

D[0

..7]

-ETHRD

-DIS_IRDA

-CS[0..3]

IRDA_RXD

SD[0..7]E

TH

IRQ

A[0

..23]

-RD

-SLE

EP VG

TDO

TDO

-DIS_FLASH

IOCHRDY

-WAIT

PS Schematics


22

GoldC

)

UT

XIN

VDD

VSS

0..7]

JTAG[1..4]

RTC_VDD

V3.3

C18100nF

0k

R31 0

D1TMM BAMINIME

R28100

C190,1FGOLDC

C2418pF

Y332.768kHzXTAL3

Y2 20 MHz

HC49SM

R27 100K

C1620pF

C1720pF

C2018pF

018906-0908

Figure 10. eZ80F92 Flash Module Schematics—100-Pin QFP eZ80F92 Device

====

eZ80=IIC-bus-master

(= JTAG0

PLACE CAPS CLOSETO PINS97,7,33,43

D[0..7]

A[0..23]

CLK_OUT

XO

CLK_OUT XOUT

-RESET

XIN

D0

D1

D2

D3

D4

D5

D6

D7

A0A1A2A3A4A5

A6A7A8A9A10A11A12A13A14

A15A16A17A18A19A20

A21

A22

A23

-CS0

-CS1

-CS2

-CS3

-CS[0..3]

D[0..7]

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PC[0..7]PB[0..7]

IICSCLIICSDA

-NMI

PD7PD6PD5PD4PD3PD2PD1PD0

TDOTDI JTAG1TRIGOUT JTAG2TCK JTAG3TMS JTAG4

RTC_VDDRTC_XOUTRTC_XIN

PD[

-BUSREQ-BUSACK-HALT_SLP

-IOR

EQ-M

REQ

-RD

-WR

-INST

RD

-WAI

T

IICSDA

IICSCL

PB[0..7]

PC[0..7]

PD[0..7]

A[0..23]

-CS[0..3]

-RESET

-IOREQ

-MREQ

-RD

-WR

-INSTRD

-WAIT

-HALT_SLP

-BUSACK

-BUSREQ

-NMI

JTAG[1..4]

RTC_XOUT

RTC_XIN

RTC_VDD

TDO

V3.3V3.3 V3.3

R29

1

C211nF

R32

220

C221nF

U8

eZ80F92

TQFP100

83

75

87 8284869697100

35

85

74

17

54

66

73

99

49

9820

81

64

8889909192939495 80

72

79

65

78

29

77

45

76

30

63

71

50

62

53

70

60

36

69

21

68

59

67

31

55

58

7

3733

61

46

1

51

22

5657

26 3427 3228

52

38 48

2

8

39 4740

3

23

4

4341

5

24

42 44

6

9

25

10

18

111213

19

141516

PC7/

RI1

PD7/RI0

VDD

PC6/

DC

D1

VSS

XOU

T

VDD

VSS

PHI

D0

XIN

PD6/DCD0

A14

BUSACK

TDO

PD5/DSR0

SCL

INST

RD

SDA

A15

PC5/

DSR

1

TRIGOUT

PB0/

T0_I

NPB

1/T1

_IN

PB2/

SSPB

3/SC

KPB

4/T4

_OU

TPB

5/T5

_OU

TPB

6/M

ISO

PB7/

MO

SI

PC4/

DTR

1

PD4/DTR0

PC3/

CTS

1

TDI (ZDA)

PC2/

RTS

1

CS0

PC1/

RxD

1

IOR

EQ

PC0/

TxD

1

CS1

TCK (ZCL)

PD3/CTS0

WAI

T

TMS

BUSREQ

PD2/RTS0/IR_SD

RTC_VDD

D1

PD1/RxD0/IR_RXD

A16

PD0/TxD0/IR_TXD

RTC_XOUT

VDD

CS2

HALT_SLP

RTC_XIN

VDD

D2

VDD

VSS

MR

EQ

A0

RESET

A17

VDDVSS

A21

VSS

A22

CS3

A23

NMI

D3

WR

A1

VSS

D4

RD

D5

A2

A18

A3

VDD

D6

A4

A19

D7

VSS

A5

A6

A20

A7

VDD

A8A9A10

VSS

A11A12A13

C231nF

D[0..7]

A[0..23]

IICSCL

IICSDA

CLK_OUT

PB[0..7]

PC[0..7]

PD[0..7]

-CS[0..3]

-RESET

-IOREQ

-MREQ

-RD

-WR

-INSTRD

-HALT_SLP

-BUSACK

-WAIT

-BUSREQ

-NMI

JTAG[1..4]

RTC_VDD

TDO

PS Schematics


23

4.7k

VSS

VDD

D0D1D2D3D4D5D6D7

V3.3

GND

RN1

018906-0908

Figure 11. eZ80F92 Flash Module Schematics—36-Pin SRAM Device

A19/A20/A21/A22/A23not used here

A0A1A2A3-CS1D0D1

D2D3-WR

A4 A5A6 A7

A16A15A14A13-RDD7D6

D5D4

A12A11

A10A9A8

A18

A17

A[0..23]

D[0..7]

-CS1-RD-WR

U1

512kx8 SRAMSOJ36.400

31

35

6

34

533

7

3243

24

2

25

23

26

36

2930

1

22

28

13

27

21

8

1112

1817

10

1920

161514

9

OE

A18

CE

A17

A4A16

I/O0

A15A3A2

A14

A1

I/O4

A13

I/O5

N.C.

I/O6I/O7

A0

A12

VSS

WE

VDD

A11

I/O1

I/O2I/O3

A9A8

VSS

N.C.A10

A7A6A5

VDD

C7100nFU2E

74LVC04/SO

11 10

U2F

74LVC04/SO

13 12

U2D

74LVC04/SO

9 8

D[0..7]

A[0..23]

-CS1-RD-WR

PS Schematics


24

VSS

VDD

VDD

-FLASHWE

V3.3

GND

R110K

018906-0908

Figure 12. eZ80F92 Flash Module Schematics—NOR Flash Device

Intel-Type

A20/A21 used for16/32Mbit-FlashPin37=N.C.

for 4Mbit-Flashes

Note: Must be pulled ’low’externally for programming.

A22/A23not used here

========

U3 IS NOT POPULATED

A[0..23]

D[0..7]

-CSFLASH-RD-WR

-RESFLASH

-CSFLASH-RD-WR

VPP

A13A14

A19

A4

A0

A3

A6

A[0..23]

A7

A2

A11A10

A18

A1

A17

A9A8

A16

A5

A15

A20

-RESFLASH

A12

-FLASHWE

A21

D4DFLASH4D3DFLASH3D2DFLASH2D1DFLASH1

D6DFLASH6D5DFLASH5

D7DFLASH7

D0DFLASH0

D[0..7]

-WP

U2A

74LVC04/SO

12

U3

MT28F008B3VGTSOP40.20MM

25212620271928183217331634153514

87

36654321

401337 38

222491012

11

29

23 3930 31

DQ0A0DQ1A1DQ2A2DQ3A3DQ4A4DQ5A5DQ6A6DQ7A7

A8A9A10A11A12A13A14A15A16A17A18A19 N.C.

CEOEWERPWP

VPP

N.C.

VS

SV

SS

VD

DV

DD

R2

0R

C8100nF

D[0..7]

A[0..23]

-CSFLASH-RD-WR

-RESFLASH

-FLASHWE

PS01 Schematics


25

TX+ <-> 1TX- <-> 2RX+ <-> 3RX- <-> 6

y

TD-

TD+

GND

15C-6150

5

6

7

8

J1

HFJ11-1041HALOFASTJACK

123456

8

2020603

R212200603

8906-0908

Figure 13. eZ80F92 Flash Module Schematics—Module

device addresses:00300h bis 0030Fh

=

int. Pull-Up

yellow

90 degree,stackeddual-LED

ESD protection arra

green

placenearJ1

through holesolder pad

don’t stuff

don’tstuff

VSS

VDD

SD

0S

D1

SD

2S

D3

SD

4S

D5

SD

6S

D7

SD[0..7]

SA0SA1SA2SA3

TD-

RXD- RD-

TXD-

TXD+

RXD+

SA[0..3]

RXD-RXD+

TXD-TXD+

CTDCRD

ETHIRQ

ETHIRQ

-ETHWR -ETHWR

-SLEEP

-LANLED-ACTIVE

SD[0..7]

SA[0..3]

-SLEEP

-LANLED-LINKLED

-ETHRD-ETHRD

TD+

RD+

RD+

-LINKLED

RD-

-LANLED

VDD

VSS CASE

V3.3

GND

GND

V3.3

GND

C15100nF

U7

CS8900A-CQ3

TQFP100

71 72 73 7465 66 67 6858 59 6051 52 53 54

37

1

38

2

39

3

40

4

41

5

42

6

43

7

44

8

459

4610

47

11

48

12

49

13

50

141516171819202122232425

2627282930313233343536

55 56 57 61 62 63 64 69 70 75

767778798081828384858687888990919293949596979899100

SD

4S

D5

SD

6S

D7

SD

0S

D1

SD

2S

D3

SA

17S

A18

SA

19

SA

13S

A14

SA

15S

A16

SA0

AV

SS

SA1

ELC

S

SA2

EE

CS

SA3

EE

SK

SA4

EE

DA

TA

OU

T (

TD

O)

SA5

EE

DA

TA

IN

SA6

CH

IPS

EL

SA7

DV

SS

SA8D

VD

DSA9

DV

SS

SA10

DM

AR

Q2

SA11

DM

AC

K2

REFRESH

DM

AR

Q1

SA12

DM

AC

K1

DM

AR

Q0

DM

AC

K0

CS

OU

TS

D15

SD

14S

D13

SD

12D

VD

DD

VS

SS

D11

SD

10

SD9SD8MEMWMEMRINTRQ2INTRQ1INTRQ0IOCS16MEMCS16INTRQ3SHBE

DV

SS

DV

DD

DV

SS

IOR

IOW

AE

N (

TC

K)

IOC

HR

DY

DV

DD

DV

SS

RE

SE

T TESTSLEEP

BSTATUS/HC1DI+DI-CI+CI-

DO+DO-

AVDDAVSSTXD+TXD-AVSSAVDDRXD+RXD-RES

AVSSAVDDAVSS

XTAL1XTAL2

LINKLED/HC0LANLED

R26100

U9

LCDASO8.

1

2

3

4

R24

8R2

R25 8R2

C12560pF

Y120.000 MHzHC49SM

R23

4k99/1%

R224k7

LD2

LED yeTHT

R19

10k

123456

8

LD1LED gn

THT

C13100nF

L2

ferritetbd

JP4HEADER 1SIP1

1

R3410k0603

R20

C14100nF

ETHIRQ

-ETHWR

-ACTIVE

-SLEEP

SA[0..3]

SD[0..7]

-ETHRD

IOCHRDY

PS Schematics


26

VSS

VDD

V3.3

GND

-RESET

018906-0908

Figure 14. eZ80F92 Flash Module Schematics—IrDA Reset

power supervisor

IR-transceiver

(MMA 020 4)

open-drain

alternative:MaximMAX6802UR29D3

IRDA_TXD

IRDA_SD

IRDA_RXD

IRDA_TXD

IRDA_RXD

IRDA_SD

-RESET

V3.3

V3.3

C9100nF0603

R62R7, 0.25W1206

R568R

C11

330nFU5

ZHX1810

2

4

3

1

5

6

0TXD

SD

RXD

LEDA

VCC

GND T

C1010nF0603

U4

MAX6328UR29SOT-23-L3

2

13

RESET

GN

DV

DD

R32k20603

IRDA_RXD

IRDA_TXD

IRDA_SD

PS Schematics


27

nnector 2

PC1PC3PC5PC7

GND_EXTPD7

-DIS_IRDA

EZ80CLK

-NMI

-WAITGND_EXT

PB0PB2PB4PB6

PD0PD2PD4

TDITRIGOUTTMS

GND_EXT

JP2

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

018906-0908

Figure 15. eZ80F92 Flash Module Schematics—Headers

place near eZ80output (PHI)

=

=

==

(JTAG0 =)

coconnector 1

CLK_OUT

RTC_VDD

A[0..23]

EZ80CLK

IICSDA IICSDAIICSCL IICSCL

D[0..7]

-FLASHWE

-CS[0..3]

-DIS_FLASH

-DIS_IRDA

PB[0..7]

PC[0..7]

PD[0..7]

-RD-WR

-IOREQ

-INSTRD

-HALT_SLP

-BUSREQ -BUSREQ-BUSACK

-NMI

JTAG[1..4]

-RESET

V3.3_EXT

JTAG4 TMS

TDOJTAG1 TDI

JTAG3 TCKJTAG2 TRIGOUT

PB1PB3

PB5PB7

PD1PD3PD5

-CS3

V3.3_EXT

-FLASHWE

A0

A2

A4

A6

A8

A10

-CS2

GND_EXT

PC2PC4

RTC_VDD

PD6

GND_EXT

IICSCLIICSDA

TDO

TCK

-RESET

-MREQ

TDO

-CS_RAM

D3

A17A5

V3.3_EXT

GND_EXT

A7

A22

A1

A18 A16

GND_EXT

-RD

D5

GND_EXT

A9

A23-CS1

A13

A11

FUTURE_USE

GND_EXT

D0

A19

D6

-BUSACK

V3.3_EXT

-CS0

-INSTRD

A15

D1

A14

A3

D4

D7-IOREQ

A21

GND_EXT-MREQ

A12A20

-DIS_FLASH

-BUSREQ-WR

D2

-HALT_SLPV3.3_EXT

PC6

PC0

-WAIT-WAIT

V3.3

GND

R9

33

R84k7

R74k7

R1210k

R1110k

R134k7

R102k20603

JP1

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

R332k20603

V3.3_EXT

A[0..23]

CLK_OUT

-RESET

RTC_VDD

IICSDAIICSCL

D[0..7]

-FLASHWE

-CS[0..3]

-DIS_FLASH

-DIS_IRDA

PB[0..7]

PC[0..7]

PD[0..7]

-RD-WR

-IOREQ

-INSTRD

-HALT_SLP

-BUSACK

-WAIT

-BUSREQ

-NMI

JTAG[1..4]

GND_EXT

-MREQ

TDO

-CS_RAM

PS Schematics


28

plane

plane

purposes

’t stuff

JP3

HEADER 2SIP2

12

C51nF

C6100nF

018906-0908

Figure 16. eZ80F92 Flash Module Schematics—Power Supply

no power supply on board!

common power

common ground

for test

don

Input: VDD(=V3.3) = 3.3V –5%

Power: Pmax = 1.6W Ptyp = 0.4W

Current: Imax = 200mA (IrDA not in use) Imax = 460mA (IrDA in use) Ityp = 100mA

GND

GND

V3.3V3.3

V3.3

GND

C147uFTAJC

C247uFTAJC

C31nF

C4100nF

PCB1

E-NET Module Rev.B98Cxxxx-xxx

V3.3

GND

PS Schematics


29

=

=

=

ff

-ETHRD

-ETHWR

SD[0..7]

SA[0..3]

-SLEEP

-ACTIVE

-CSFLASH

-RESFLASH

IRDA_TXD0

IRDA_RXD1

IRDA_SD

ETHIRQ

35 0

R

R

-ETHRD

-ETHWR

SD[0..7]

SA[0..3]

ETHIRQ

-SLEEP

-ACTIVE

-CSFLASH

-RESFLASH

IRDA_TXD

IRDA_SD

IRDA_RXD

IOCHRDY

018906-0908

Figure 17. eZ80F92 Flash Module Schematics—Control Logic

=

=

====

=

don’t stu

=

PD3 and PD5not used here

-CS1 and-CS2not used here

only A0,A1,A2,A3are used here

-RD

-WR

VSS

VDD

D[0..7]

A[0..23]

D[0..7] SD[0..7]

A[0..23] SA[0..3]

SA0A0SA1A1SA2A2SA3A3

PD[0..7]

-CS[0..3]

-RESET

PD

PD

-RESET

-RD

-WR

-ETHRD

-ETHWR

-CS3 -CSETH

-CS0-CSFLASH

IRDA_SD

PD7

PD6

PD4

-DIS_IRDA

-DIS_FLASH

IR_SDPD2

DISABLE_FLASH

DISABLE_IRDA

-DIS_FLASH

-DIS_IRDA

-WAIT

-WAIT

V3.3

GND

R1710k0603

U2B

74LCX04TSSOP14

3 4

R

U2C

74LCX04TSSOP14

5 6

R3010k0603

R14 0U2D

74LCX32TSSOP14

12

1311

U6A

74LCX32TSSOP14

1

23

R15 0

U6B

74LCX32TSSOP14

4

56

U6D

74LCX32TSSOP14

12

1311

-RD

-WR

D[0..7]

A[0..23]

PD[0..7]

-CS[0..3]

-DIS_FLASH

-DIS_IRDA

-RESET

-WAIT

PS018906-0908 Customer Support


30

Customer Support

For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb.

For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com.

http://www.zilog.com/kb

http://support.zilog.com

ez80f92 flash moduletable 1 lists the installed components of the ez80f92 flash module. table 1....

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