fabrication process
DESCRIPTION
Lithography Resist coating + soft bake Exposure Post-exposure bake + development Etching Silicon etch Oxide Etch Post processing Dicing Substrate thinning Cleaving. Fabrication Process. Layer structure 205 Top Si layer 400nm Buried Oxide Wafer size 8” (200mm). - PowerPoint PPT PresentationTRANSCRIPT
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Fabrication Process
Lithography Resist coating + soft bake
Exposure
Post-exposure bake + development
Etching Silicon etch
Oxide Etch
Post processing Dicing
Substrate thinning
Cleaving
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Si-substrate
SiO2
Si205nm
400nm
Step 1: Bare SOI wafer
Layer structure 205 Top Si layer
400nm Buried Oxide
Wafer size 8” (200mm)
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Step 2: Photoresist Coating
Photoresist
Resist Shipley UV3
800nm thick
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Step 3: Soft baking of resist
Photoresist
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Step 4: Antireflective coating
AR-coating
AR coating No standing waves in resist
during lithography
40nm of NFC
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Step 5: Illumination
Deep UV Lithography Wavelength = 248nm
NA = 0.63
Dose = 10-40 mJ
Reduction = 4X
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Step 6: Post-exposure bake
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Step 7: Development
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Step 8: Silicon etchEtch properties
TCP9400PTX ICP-RIE Low pressure /high density
Cl2/HBr/He/O2 chemistry
Two-step break-through main etch
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Step 9: Oxide Etch
Etch properties Exelan
Dual frequency Medium pressure /medium density
CF4/CHF3 chemistry
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Step 10: Resist strip
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Step 11: Protective Resist Layer
750m
Substrate thinning = dangerous
1-3m resist cover
Wafer is diced into 3 x 3 cm2 dies for substrate thinning
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Glass plate
Bee’s wax
Step 12: Glue on glass plate
Glue = Bee’s wax Heated to ± 130°C
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Glass plate
Bee’s wax
Step 13: Substrate thinning
250m
Mechanical grinding Alumina powder
5-8 hours
Remove 500m
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Step 14: Cleaning and Cleaving