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8/16/2019 Fabrikasi IC

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IC FABRICATION


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Technology Background


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What is a Silicon Chip?

• A pattern of interconnected sitches and gates on thesurface of a crystal of se!iconductor "typically Si#

• These sitches and gates are !ade of – areas of n$type silicon

– areas of p$type silicon – areas of insulator – lines of conductor "interconnects# %oining areas together

• Alu!iniu!& Copper& Titaniu!& 'oly(denu!& polysilicon& tungsten

• The geo!etryof these areas is knon as the layout of the

chip• Connections fro! the chip to the outside orld are !adearound the edge of the chip to facilitate connections toother de)ices


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Sitches

• *igital e+uip!ent is largely co!posed of sitches• Sitches can (e (uilt fro! !any technologies

– relays "fro! hich the earliest co!puters ere (uilt# – ther!ionic )al)es

– transistors• The perfect digital sitch ould ha)e the

folloing, – sitch instantly

– use no poer – ha)e an in-nite resistance hen o. and /ero resistancehen on

• Real sitches are not like this0


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Se!iconductors and*oping• Adding trace a!ounts of certain !aterials to

se!iconductors alters the crystal structure and canchange their electrical properties – in particular it can change the nu!(er of free electrons or holes

• N$Type – se!iconductor has free electrons

– dopant is "typically# phosphorus& arsenic& anti!ony• 1$Type

– se!iconductor has free holes – dopant is "typically# (oron& indiu!& galliu!

• *opants are usually i!planted into the se!iconductor

using I!plant Technology& folloed (y ther!al process todi.use the dopants


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'etal$o2ide$se!iconductor "'OS#and related 34SI technology

• p'OS

• n'OS• C'OS• BiC'OS

• 5aAs 34SI , 3ery 4arge ScaleIC


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Basic 'OS Transistors

• 'ini!u! line idth• Transistor cross section

• Charge in)ersion channel• Source connected to su(strate• 6nhance!ent )s *epletion !ode

de)ices• p'OS are 789 ti!e sloer than n'OSdue to electron and hole !o(ilities


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Fa(rication Technology

• Silicon of e2tre!ely high purity – che!ically puri-ed then gron into large crystals

• Wafers – crystals are sliced into afers

– afer dia!eter is currently :9;!!& 7;;!!&


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• *i.erent parts of each die ill (e!ade 1$type or N$type "s!all a!ountof other ato!s intentionallyintroduced $ doping $i!plant#

• Interconnections are !ade ith!etal

• Insulation used is typically SiO78 SiNis also used8 Ne !aterials (eingin)estigated "lo$k dielectrics#


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• n'OS Fa(rication• C'OS Fa(rication

– p$ell process – n$ell process – tin$tu( process


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• All the de)ices on the afer are !ade at the sa!e ti!e• After the circuitry has (een placed on the chip

– the chip is o)erglassed "ith a passi)ation layer# to protect it – only those areas hich connect to the outside orld ill (e left

unco)ered "the pads#

• The afer -nally passes to a test station – test pro(es send test signal patterns to the chip and !onitor

the output of the chip

• The yield of a process is the percentage of die hich passthis testing

• The afer is then scri(ed and separated up into theindi)idual chips8 These are then packaged

• Chips are >(inned according to their perfor!ance


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C'OS Technology

• First proposed in the :@;s8 Was not seriously considereduntil the se)ere li!itations in poer density and dissipationoccurred in N'OS circuits

• No the do!inant technology in IC !anufacturing

• 6!ploys (oth p'OS and n'OS transistors to for! logicele!ents• The ad)antage of C'OS is that its logic ele!ents dra

signi-cant current only during the transition fro! one stateto another and )ery little current (eteen transitions $

hence poer is conser)ed8• In the case of an in)erter& in either logic state one of thetransistors is o.8 Since the transistors are in series& " no#current os8

• See tin$ell cross sections


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BiC'OS• A knon de-ciency of 'OS technology is its li!ited load dri)ing

capa(ilities "due to li!ited current sourcing and sinking a(ilities ofp'OS and n'OS transistors8• Bipolar transistors ha)e

– higher gain – (etter noise characteristics – (etter high fre+uency characteristics

• BiC'OS gates can (e an eDcient ay of speeding up 34SI circuits• See ta(le for co!parison (eteen C'OS and BiC'OS• C'OS fa(rication process can (e e2tended for BiC'OS• 62a!ple Applications

– C'OS $ 4ogic – BiC'OS$ IEO and dri)er circuits – 6C4$ critical high speed parts of the syste!


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'OS Transistor Structure


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'OS Transistor Structure


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'OS )ieed as Sitch


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Co!ple!entary 'OS


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In)erter 4ayout

Out In

V DD

PMOS

NMOS

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+


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Silicon IC processing

• Si!ilar to photographic printing – 62pose the silicon afer through a !ask – 1rocess the silicon afer

– Repeat se+uentially to pattern all the layers• 4ayout, A set of !asks that tell a fa(ricatorhat to pattern – For each layer in your circuit

– 4ayers are !etal& drainEsource i!plants& gate& etc8 – ou dra the layers

• Su(%ect to )endor$supplied spacing rules


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The afer• C/ochralski process

– 'elt silicon at :G79 HC – Add i!purities "dopants# – Spin and pull crystal

• Slice into afers – ;879!! to :8;!! thick

• 1olish one side


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Crystal and afer

Wand

(a finished 250lb crystal)

A polished wafer


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C'OS 1rocess at a 5lanceDefine active areas

Etch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers


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Fa(rication Steps• Start ith (lank afer "typically p$type here

N'OS is created#• First step ill (e to for! the n$ell "here

1'OS ould reside# – Co)er afer ith protecti)e layer of SiO7 "o2ide# – Re!o)e o2ide layer here n$ell should (e (uilt – I!plant or di.use n dopants into e2posed afer to

for! n$ell – Strip o. SiO7

p substrate


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O2idation

• 5ro SiO7 on top of Si afer – @;; :7;; C ith J7O or O7 in

o2idation furnace

p substrate

SiO2


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1hotoresist• 1hoto resist

– 1hotoresist is a light$sensiti)eorganic poly!er

– 1roperty changes heree2posed to light

• To types of photo resists"positi)e or negati)e# – 1ositi)e resists can (e re!o)ed

if e2posed to K3 light

– Negati)e resists cannot (ere!o)ed if e2posed to K3 light

p substrate

SiO2

Photoresist


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9/03 IEEE spectrum


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1atterning

• Jo epattern ande2pose the

resist – To !ake thepatterns eant on the

silicon

IEEE Spectrum, !"", p# $%


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9/03 IEEE spectrum


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4ithography

• 62pose photoresist to Kltra$)iolate"K3# light through the n$ell !ask

• Strip o. e2posed photo resist ithche!icals

p substrate

SiO2

Photoresist


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6tch

• 6tch o2ide ith hydrouoric acid "JF#• Only attacks o2ide here resist has (een

e2posed• N$ell pattern is transferred fro! the !ask to

silicon$di$o2ide surfaceL creates an opening tothe silicon surface

p substrate

SiO2

Photoresist


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Strip 1hotoresist

• Strip o. re!aining photoresist – Kse !i2ture of acids called piranah

etch

• Necessary so resist doesnt !elt inne2t step

p substrate

SiO2


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N$ell• N$ell is for!ed ith di.usion or ion i!plantation• *i.usion

– 1lace afer in furnace ith arsenic$rich gas – Jeat until As ato!s di.use into e2posed Si

• Ion I!planatation – Blast afer ith (ea! of As ions – Ions (locked (y SiO7& only enter e2posed Si

• SiO7 shields "or !asks# areas hich re!ain p$type

n well

SiO2


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Strip O2ide

• Strip o. the re!aining o2ide usingJF

• Su(se+uent steps in)ol)e si!ilarseries of steps

p substrate

n well


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1oly silicon"self$aligned gate technology#

• *eposit )ery thin layer of gate o2ide – = 7; M "$ ato!ic layers#

• Che!ical 3apor *eposition "C3*# of siliconlayer – 1lace afer in furnace ith Silane gas "SiJG# – For!s !any s!all crystals called polysilicon – Jea)ily doped to (e good conductor

Thin gate oxide

Polysilicon

p substraten well


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Self$Aligned 1rocess

• Kse gate$o2ideEpoly silicon and!asking to e2pose here ndopants should (e di.used or

i!planted• N$di.usion for!s n'OS source&

drain& and n$ell contact

p substraten well


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N$di.usionEi!plantation cont8

• Jistorically dopants ere di.used• Ksually high energy ion$

i!plantation used today• But n regions are still called

di.usion

n wellp substrate

n+n+ n+


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1$*i.usionEi!plantation

• Si!ilar set of steps for! pPdi.usionQ regions for 1'OS sourceand drain and su(strate contact

p+ iffusion

p substraten well

n+n+ n+p+p+p+


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Contacts

• No e need to ire together thede)ices

• Co)er chip ith thick -eld o2ide"FO#

• 6tch o2ide here contact cuts areneeded

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

!ontact


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'etali/ation

• Sputter on alu!inu! o)er hole afer• 5old is used in neer technology• 1attern to re!o)e e2cess !etal& lea)ing ires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal


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C'OS IN36RT6R

V DD V DD

V in 9 V DD V in 9 ;

V out V out

R n

R p

Out In

V DD

PMOS

NMOS


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Figure courtesy

Yan Borodovsky,

Intel

A 1entiu! cutaay

N ti l ; :


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National ;8:! processcutaay


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Ad)anced 'etalli/ation $ Copper

&opper 'ersus Aluminum

$0 lower resisti'ity

%0* less electromi+ration


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Interconnect I!pact on Chip


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