facing the hot chip challenge (again) the hot chip challenge (again) bill holt ... transistors/die...

1

Facing the Hot Chip ChallengeFacing the Hot Chip Challenge

(Again)(Again)

Bill HoltBill HoltGeneral ManagerGeneral Manager

Technology and Manufacturing GroupTechnology and Manufacturing Group

Intel CorporationIntel Corporation

Hot Chips 17Hot Chips 17

August, 2005August, 2005

22

Key MessagesKey Messages

The driving force behind MooreThe driving force behind Moore’’s Laws Law

Power has always been a considerationPower has always been a consideration

Process and design collaboration required toProcess and design collaboration required toaddress power challengesaddress power challenges

Technology Advances provide a transistorTechnology Advances provide a transistorbudget to support innovationbudget to support innovation

Efficient Design utilizes transistor budget toEfficient Design utilizes transistor budget todeliver product performancedeliver product performance

33

““Reduced costReduced cost is one of the big is one of the big

attractions of integratedattractions of integrated

electronics, and the costelectronics, and the cost

advantage continues to increaseadvantage continues to increase

as the technology evolvesas the technology evolves

toward the production of largertoward the production of larger

and larger circuit functions on aand larger circuit functions on a

single semiconductor substrate.single semiconductor substrate.””

Electronics, Volume 38,Electronics, Volume 38,

Number 8, April 19, 1965Number 8, April 19, 1965

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

TransistorsTransistors

Per DiePer Die

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010

Source: IntelSource: Intel

MooreMoore’’s Law - 1965s Law - 1965

1965 Data (Moore)1965 Data (Moore)

44

MooreMoore’’s Law - 2005s Law - 2005

40044004

80808080 808680868028680286

386386™™ Processor Processor486486™™ Processor Processor

PentiumPentium® ® ProcessorProcessorPentiumPentium®® II ProcessorII Processor

PentiumPentium®® III Processor III Processor

PentiumPentium®® 4 Processor 4 ProcessorItaniumItanium™™ ProcessorProcessor

TransistorsTransistors

Per DiePer Die

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010

80088008

ItaniumItanium™™ 22 ProcessorProcessor

1K1K

4K4K

64K64K

256K256K

1M1M

16M16M4M4M

64M64M

256M256M512M512M

1G1G 2G2G

128M128M

16K16K

1965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessor

MemoryMemory

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010


55Source: WSTS/Dataquest/IntelSource: WSTS/Dataquest/Intel

101033

101044

101055

101066

101077

101088

101099

10101010

’68 ’72 ’76 ’80 ’84 ’88 ’92 ’96 ’00

As the

number of

transistors

goes UP

The Economics of MooreThe Economics of Moore’’s Laws Law

’04

Cost per

transistor

goes DOWN

1010

1010--77

1010--66

1010--55

1010--44

1010--33

1010--22

1010--11

101000

66

65nm

300mm

Dual Core

Scaling: Scaling: The Fundamental Cost DriverThe Fundamental Cost Driver

90nm

300mm

130nm

200mm

180nm

200mm

250nm

200mm

350nm

200mm

OROR ==Twice theTwice the

circuitry in thecircuitry in the

same spacesame space

(architectural(architectural

innovation)innovation)

The sameThe same

circuitry in halfcircuitry in half

the spacethe space

(cost reduction)(cost reduction)

Half the die sizeHalf the die sizefor the samefor the same

capability thancapability thanin the priorin the prior

processprocess

77 Source: VLSIR Source: VLSIR

Wafer Size:Wafer Size: Enables Cost Efficiency Enables Cost Efficiency

0

100

200

300

400

500

1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015

Year That Industry Exceeds 3 Million wafers/yearYear That Industry Exceeds 3 Million wafers/year

Wafe

r D

iam

ete

r (m

m)

Wafe

r D

iam

ete

r (m

m)

ProjectedProjected

300mm300mm

200mm200mm

150mm150mm125mm125mm

100mm100mm75mm75mm

50mm50mm

450mm450mm

450 mm450 mmdevelopmentdevelopment

88

Processed Wafer CostProcessed Wafer Cost

Wafer size conversions offset trend ofWafer size conversions offset trend of

increasing wafer processing costincreasing wafer processing costSource: IntelSource: Intel

99

100 100 nanodollarsnanodollars per transistor per transistor

(1 cent = 100,000 transistors)(1 cent = 100,000 transistors)

Source: WSTS/Intel, 5/05Source: WSTS/Intel, 5/05

MooreMoore’’s Law + Bigger Wafers =s Law + Bigger Wafers =

Lower Cost/functionLower Cost/function

100 100 nanodollarsnanodollars per transistor per transistor

(1 cent = 100,000 transistors)(1 cent = 100,000 transistors)

1010

1010--77

1010--66

1010--55

1010--44

1010--33

1010--22

1010--11

101000

'68'68 '70'70 '72'72 '74'74 '76'76 '78'78 '80'80 '82'82 '84'84 '86'86 '88'88 '90'90 '92'92 '94'94 '96'96 '98'98 '00'00 '02'02 '04'04

1010







1111

Power challenges arePower challenges areneither new nor fundamentalneither new nor fundamental

““Will it be possible toWill it be possible to

remove the heatremove the heat

generated by 10generated by 10’’s ofs of

thousands ofthousands of

components?components?””G. MooreG. Moore, , Cramming more componentsCramming more components

onto integrated circuitsonto integrated circuits, Electronics,, Electronics,

Volume 38, Number 8, April 19, Volume 38, Number 8, April 19, 19651965

1212

““The The power barrierspower barriers now facing alternative semiconductor now facing alternative semiconductor

processes indicate that only CMOS will allow chip makers to capitalizeprocesses indicate that only CMOS will allow chip makers to capitalize

on the density that can be achieved with gate arrays and standard cells.on the density that can be achieved with gate arrays and standard cells.””

““Once, maybe twice a decade the electronics industry encounters a forceOnce, maybe twice a decade the electronics industry encounters a force

that affects not only the way circuits are physically designed but also thethat affects not only the way circuits are physically designed but also the

way the industry thinks. way the industry thinks. CMOS is just such a forceCMOS is just such a force..””

Source: Electronic Design, October 1984Source: Electronic Design, October 1984

MooreMoore’’s Law Preceded CMOSs Law Preceded CMOS

1313

Silicon Technology has Changed toSilicon Technology has Changed toIncrease Power EfficiencyIncrease Power Efficiency

19601960’’s: Bipolars: Bipolar

19701970’’s: PMOS, NMOSs: PMOS, NMOS

19801980’’s: CMOSs: CMOS

19901990’’s: Voltage scaling (P = CVs: Voltage scaling (P = CV22f)f)

20002000’’s: Power efficient scaling/designs: Power efficient scaling/design

1414

PMOSPMOSBipolarBipolar

MooreMoore’’s Law Will Outlive CMOSs Law Will Outlive CMOS

1960 1970 1980 1990 2000 2010 2020 2030

CMOSCMOS

1µm 100nm 10nm10µm

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010 1965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessor

MemoryMemory

10101111

10101212

10101313 VoltageVoltageScalingScaling

PwrPwr EffEffScalingScaling

New New NanoNano--structuresstructures

NMOSNMOS

KiloXtor

MegaXtor

GigaXtor

TeraXtor

Tra

nsis

tors

/Die

Tra

nsis

tors

/Die

Beyond CMOS?Beyond CMOS?Spin based?Spin based?Molecular?Molecular?Other?Other?

Through InnovationThrough InnovationSource: IntelSource: Intel

1515




Process and design collaborationProcess and design collaborationrequired to address power challengesrequired to address power challenges



1616

Process Advances Still Scale PowerProcess Advances Still Scale Power

but the rate has slowed and collaboration is requiredbut the rate has slowed and collaboration is required

.. 35µ

m35µ

m

.. 25µ

m25µ

m

.. 18µ

m18µ

m

.. 13µ

m13µ

m

90n

m90n

m

65n

m65n

m

45n

m45n

m

32n

m32n

m

CV

CV

22 S

calin

g S

calin

g

1717

Leakage becomes SignificantLeakage becomes Significant

Power scaling vs. process for the last 10 yearsPower scaling vs. process for the last 10 years

(includes frequency increasing with process speed)(includes frequency increasing with process speed)

No

rmali

zed

Pro

du

ct

Po

wer

No

rmali

zed

Pro

du

ct

Po

wer

LeakageLeakage

DynamicDynamic

00

0.20.2

0.40.4

0.60.6

0.80.8

11

1.21.2

.35µm.35µm .25µm.25µm .18µm.18µm .13µm.13µm 90nm90nm 65nm65nm

Strained Strained silicon silicon

reductionreduction

1818

Rela

tive P

ow

er

Den

sit

y

Rela

tive P

ow

er

Den

sit

y

(lo

g s

cale

)(l

og

scale

)

40044004

80088008

80808080

80858085

80868086

286286386386

486486PentiumPentium®®

processorsprocessors11

1010

100100

1,0001,000

’’7070 ’’8080 ’’9090 ’’0000 ’’1010

However, Power Density HasHowever, Power Density HasLeveled OffLeveled Off


1919

Effective Process and Design CollaborationEffective Process and Design CollaborationSucceeds in Power ImprovementsSucceeds in Power Improvements

Next Next generationgenerationproduct if product if 130nm130nm

130nm130nm 90nm 90nm processprocessonlyonly

ProcessProcessplusplusdesigndesignefficiencyefficiency

Rela

tive P

ow

er

Rela

tive P

ow

er

Process,Process,designdesignefficiency, efficiency, and frequencyand frequencyincreaseincrease

2020





Technology Advances provide aTechnology Advances provide atransistor budget to support innovationtransistor budget to support innovation


2121

Feature Size ScalingFeature Size Scaling

0.7x every

3 years

0.7x every

2 years

New technology generation every 2 yearsNew technology generation every 2 years

Silicon Technology AdvancesSilicon Technology Advances

2222

Transistor Gate Length ScalingTransistor Gate Length Scaling

GateGate

LengthLength

Transistor gate length ~60% of other minimum featuresTransistor gate length ~60% of other minimum features

2323

Key Density Indicator Continues to ScaleKey Density Indicator Continues to Scale

Pitch

Gate pitch continues to scale 0.7x per generation,Gate pitch continues to scale 0.7x per generation,

providing ~2x transistor density improvementsproviding ~2x transistor density improvements

2424

11

1010

100100

10001000

0.20.2 0.40.4 0.60.6 0.80.8 1.01.0 1.21.2 1.41.4 1.61.6

Transistor Drive Current Transistor Drive Current ((mA/mA/µµmm))

StdStd StdStdStrainStrain StrainStrain

+25% I+25% I ONON +10% I+10% I ONON

0.04x I0.04x I OFFOFF

0.20x I0.20x I OFFOFF

PMOSPMOS NMOSNMOS

Strained Silicon Improves TransistorStrained Silicon Improves TransistorPerformance and Leakage TodayPerformance and Leakage Today

TransistorTransistor

LeakageLeakage

CurrentCurrent

((nA/nA/µµmm))


2525

High-k Dielectric Can Reduce GateHigh-k Dielectric Can Reduce GateLeakage TomorrowLeakage Tomorrow

Silicon substrate

Gate

3.0nm High-k

Silicon substrate

1.2nm SiO2

Gate

LLowerower power power> 100x reduction> 100x reductionGate dielectricGate dielectric

leakageleakage

Faster transistorsFaster transistors60% greater60% greaterGate capacitanceGate capacitance

BenefitBenefitHigh-k vs. SiOHigh-k vs. SiO22


Process integration is the key challengeProcess integration is the key challenge

26

High

Performance

Ultra-Low

Power

CPU

Cell Phone

PDA

Mobile Chipset

Network Processor

Low

Power

Transistors Require Optimization to the ApplicationTransistors Require Optimization to the ApplicationPerformance vs. LeakagePerformance vs. Leakage

Optimized transistors can provide ~1000x lower leakageOptimized transistors can provide ~1000x lower leakage

2727

65 nm Generation Transistors Today65 nm Generation Transistors Today

35 nm gate length35 nm gate length

1.2 nm gate oxide1.2 nm gate oxide

220 nm gate pitch220 nm gate pitch

NiSi for low resistanceNiSi for low resistance

22NDND generation strained generation strained

silicon for enhancedsilicon for enhanced

performance/powerperformance/power

35 nm

NiSi

Si3N4

Si Substrate

NMOS

PMOS

SiGe SiGe

2828

Innovations Required to ReduceInnovations Required to ReduceInterconnect RC Interconnect RC ChallengesChallenges

Source: IDFSource: IDF

1

10

100

1000

10000

0.35 0.25 180nm 130nm 90nm 65nm

Process Technology

Dela

y (

ps

)

Clock PeriodClock Period

RC delay of 1mm interconnectRC delay of 1mm interconnect

Copper InterconnectCopper Interconnect

Low KLow K

3-D3-D

2929

3D Silicon Stacking3D Silicon Stacking

Wafer DieWafer Die

LogicLogic

Logic, Memory, or ?Logic, Memory, or ?

BottomBottom

WaferWafer

TopTop

ThinThin

WaferWafer


3030

65 nm Generation Interconnects65 nm Generation Interconnects

M8M8

M7M7

M6M6

M5M5

M4M4

M3M3

M2M2

M1M1

Cu LineCu Line

Cu ViaCu Via

CDOCDOLow-kLow-k

DielectricDielectric

3131

Si Substrate

Metal Gate

High-kTri-Gate

S

G

D

III-V

S

Carbon

Nanotube FET

Innovation-Enabled Pipeline in PlaceInnovation-Enabled Pipeline in Place

50 nm

35 nm

30 nm

SiGe S/DSiGe S/D

StrainedStrained

SiliconSilicon

Future options subject to changeFuture options subject to change

SiGe S/DSiGe S/D

StrainedStrained

SiliconSilicon

90 nm90 nm65 nm65 nm

45 nm45 nm32 nm32 nm

2003200320052005

2007200720092009

2011+2011+

Technology Generation

Technology Generation

20 nm

Manufacturing Development Research

10 nm

5 nm

Nanowire


3232






Efficient Design utilizes transistorEfficient Design utilizes transistorbudget to deliver product performancebudget to deliver product performance

3333

Power Reduction TechniquesPower Reduction Techniques

Optimum DesignOptimum Design

Leakage ControlLeakage Control

Active Power ReductionActive Power Reduction

Increase On-die MemoryIncrease On-die Memory

Multi-threadingMulti-threading

Dual Core and Multi-coreDual Core and Multi-core

Special Purpose HardwareSpecial Purpose Hardware

Function Integration through SOC/SIPFunction Integration through SOC/SIP

3434

Circuit Techniques ReduceCircuit Techniques ReduceSource Drain LeakageSource Drain Leakage

Body BiasBody Bias

+ + VeVe

VddVddVbpVbp

VbnVbn

- - VeVe

2 - 10X2 - 10X

Sleep TransistorSleep Transistor

2 - 1000X2 - 1000X

Stack EffectStack Effect

5 - 10X5 - 10X

Logic Logic

BlockBlock

Equal LoadingEqual Loading

LeakageLeakage

ReductionReduction

3535

Sleep Transistor Reduces SRAMSleep Transistor Reduces SRAMLeakage PowerLeakage Power

VVSSSS

VVDDDD

NMOSNMOS

SleepSleep

TransistorTransistor

SRAMSRAM

CacheCache

BlockBlock

70 70 MbitMbit SRAM leakage current map SRAM leakage current map

Without sleep transistorWithout sleep transistor With sleep transistorWith sleep transistor

Accessed blockAccessed block

>3x SRAM leakage reduction on inactive blocks>3x SRAM leakage reduction on inactive blocks


3636

Active Power ReductionActive Power Reduction

Slow Fast Slow

Lo

w S

up

ply

Vo

ltag

e

Hig

h S

up

ply

Vo

ltag

e

Multiple Supply

Voltages

Logic BlockFreq = 1

Vdd = 1

Throughput = 1

Power = 1

Area = 1

Pwr Den = 1

Vdd

Logic Block

Freq = 0.5

Vdd = 0.5

Throughput = 1

Power = 0.25

Area = 2

Pwr Den = 0.125

Vdd/2

Logic Block

Replicated Designs

3737

Dual CoreDual Core

3%3%

PowerPower

0.66%0.66%1%1%1%1%

PerformancePerformanceFrequencyFrequencyVoltageVoltage

Rule of thumb

Core

Cache

Core

Cache

Core

Voltage = 1

Freq = 1

Area = 1

Power = 1

Perf = 1

Voltage = -15%

Freq = -15%

Area = 2

Power = 1

Perf = ~1.8

In the same process technology…

3838

Special Purpose HardwareSpecial Purpose Hardware

2.23 mm x 3.54 mm, 260K transistors

Special purpose HWSpecial purpose HW——Best Best MipsMips/Watt/Watt

Special Purpose HW EngineSpecial Purpose HW Engine

Opportunities:Opportunities:

MPEG Encode/DecodeMPEG Encode/Decode

Speech recognitionSpeech recognition

GraphicsGraphics

3939

Value of IntegrationValue of Integration

Special-purpose hardware Special-purpose hardware more MIPS/mm² more MIPS/mm²

SIMD integer and FP instructions in several ISAsSIMD integer and FP instructions in several ISAs

1.5 - 4X1.5 - 4X<10%<10%<10%<10%MultimediaMultimedia

KernelsKernels

~1.4X~1.4X2X2X2X2XGeneralGeneral

PurposePurpose

PerformancePerformancePowerPowerDie AreaDie Area

Si Monolithic Polylithic

CPU

Special

HW

Memory

CMOS RF

Wireline

RF

Opto-

Electronics

Dense

Memory

Heterogeneous

Si, SiGe, GaAs

4040

Joint Power ReductionJoint Power ReductionTechnology RoadmapTechnology Roadmap

Multi-threaded Multi-coreMulti-threaded Multi-core

Increasing multi-processing Increasing multi-processing

Special purpose HW Special purpose HW

ShallowerShallower

pipelinespipelines

Large cachesLarge caches

Multi-threadingMulti-threading

Micro-Micro-

ArchitectureArchitecture

Sleep transistorsSleep transistors

Stack effectStack effect

Multiple supply voltagesMultiple supply voltages

Body BiasBody Bias

SizingSizing

Clock gatingClock gating

Circuits andCircuits and

DesignDesign

FinFETFinFET (Tri- (Tri-

Gate)Gate)

Metal GateMetal Gate

3D3D

Dual Dual VtVt (Le) (Le)

Strain engineeringStrain engineering

Low K ILDLow K ILD

Dual Dual VtVt

CopperCopper

ProcessProcess

TechnologyTechnology

Future options subject to changeFuture options subject to change

4141

Effective Process and Design CollaborationEffective Process and Design CollaborationSucceeds in Power ImprovementsSucceeds in Power Improvements

Next Next generationgenerationproduct if product if 130nm130nm

130nm130nm 90nm 90nm processprocessonlyonly

ProcessProcessplusplusdesigndesignefficiencyefficiency

Rela

tive P

ow

er

Rela

tive P

ow

er

Process,Process,designdesignefficiency, efficiency, and frequencyand frequencyincreaseincrease

4242

…… and it works and it works

130 nm 90 nm 130 nm 90 nm

MadisonMadison MontecitoMontecito

Cores/ThreadsCores/Threads 1/11/1 2/4 2/4

TransistorsTransistors 0.410.41 1.721.72 BillionBillion

L3 CacheL3 Cache 66 2424 MByteMByte

FrequencyFrequency 1.51.5 >1.7>1.7 GHzGHz

Relative PerformanceRelative Performance 11 >1.5x>1.5x

Thermal Design Power Thermal Design Power 130130 ~100~100 WattWatt


4343

Economics is driving force behind MooreEconomics is driving force behind Moore’’s Laws Law





ConclusionsConclusions

4444

Thank youThank you

facing the hot chip challenge (again) the hot chip challenge (again) bill holt ... transistors/die...

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