fairchildsemi 04powerseminar5
DESCRIPTION
What Every Designer Should Know About MOSFETs (Up to 200V)TRANSCRIPT
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What Every Designer Should Know AboutMOSFETs (Up to 200V)
Power Seminar 2004
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2Outline
Computer/Consumer SMD Switch Applications Synchronous Buck Regulators Node Voltage Overshoots MOSFET Body Diode & Avalanche Ruggedness Switch Timing and dV/dt Shoot Through Package and Layout Parasitics
Industrial Applications Paralleling Multiple MOSFETs Trench vs. Planar RC DrainSource Snubbers
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3Synchronous Buck Converters
HIGH SIDE (control) switch is ON for a short time Switching losses per cycle will be high as the full current and
the full input voltage need to be switched Due to the low duty cycle, the conduction losses will be much
less than for an equivalent Low Side switch
LOW SIDE (synchronous) switch is ON for most of the time Conduction losses will dominate Switching losses per cycle are lower as the full input current is
switched at the low side Schottky diode forward voltage
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4Synchronous Buck Converter
Duty Cycle = Vout / Vin
Each MOSFET sees a maximum voltage of Vin Vds(on) ofother MOSFET.
However
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5Outline
Computer/Consumer SMD Switch Applications Synchronous Buck Regulators
Node Voltage Overshoots MOSFET Body Diode & Avalanche Ruggedness Switch Timing and dV/dt Shoot Through Package and Layout Parasitics
Industrial Applications Paralleling Multiple MOSFETs Trench vs. Planar RC DrainSource Snubbers
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6Switch Node Spikes Higher than Input Voltage!(Notebook FDS6294 upper FET / FDS7088N3 x1 Lower FET)
VGSFDS7088N3
VDSFDS7088N3
Anti-parallel diode, switch timing, package inductance, board layout
Conditions:
Vin = 19V
Iout = 15A
Still air
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7As Switching Frequencies Increase
As MOSFETs switch faster, ringing will tend to increase.In spite of careful MOSFET structure design and choice of dopingdensities etc., the trend is towards an increasingly snappy diode.
The Ratio tb / ta is called SoftnessFactor and is key in reducing EMI
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8Making MOSFETs with a Faster Diode
SyncFet Adding an anti-parallel Schottky on same silicon. SyncFet is an order of magnitude trr and Qrr improvement over
the best co-packaged hybrid of a MOSFET and Schottky. We candesign MOSFETs with alternating MOSFET and Schottky strips tominimize trr and Qrr.
OR
Improving existing diode by creating recombination centers inbody-epitaxy interface.
Platinum doping is most popular method for softness. So far, not introduced in low voltage MOSFETs because trr and
Qrr are much lower than in high voltage MOSFETs.
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9Low Side FET Switching Waveforms no RCSnubber(Notebook FDS6294 upper FET / FDS6288 x2 Lower FET)
Vgs FDS6288
Vds FDS6288
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Low Side FET Switching Waveforms with 1.5nF,3.3 RC Snubber(Notebook FDS6294 upper FET / FDS6288 x2 Lower FET)
Vgs FDS6288
Vds FDS6288
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Low Side SyncFET Switching Waveforms(Notebook FDS6294 upper FET / FDS6688S x2 Lower FET)
VgsFDS6688S
VdsFDS6688S
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Converter Efficiency Comparison
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Thermal Camera Images(FDS6288 vs. FDS6688S, 19Vin, 1.3Vout@20A)
FDS6294 HS, FDS6288 LS FDS6294 HS, FDS6688S LS
FDS6294(83C)
FDS6288(80C)
FDS6688S(73C)
FDS6294(71C)
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Eas Single Pulse Avalanche Energy
Single pulsed avalanche energy ( ) guaranteed by test. Energy level to endure without fail
EAS
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Notebook FDS6294 upper FET / FDS7288N3 x2Lower FET(Lower FET switching waveforms) Zoom in of slide 20.
Conditions:
Vin = 19V
Iout = 15A
Still air
dVDS/dt = 9.6V/ns
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Avalanche Energy Rating :The Avalanche Current is the Key Parameter
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Outline
Computer/Consumer SMD Switch Applications Synchronous Buck Regulators Node Voltage Overshoots MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through Package and Layout Parasitics
Industrial Applications Paralleling Multiple MOSFETs Trench vs. Planar RC DrainSource Snubbers
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Shoot Through
Adaptive gate delay circuits prevent shoot-through in mostcases.
However, a phenomenon known as dv/dt or false turn-on can cause shoot-through to occur.
This problem shows up as poor efficiency and higherMOSFET temperatures in both MOSFETs and higher EMI.
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PWMIC - Switch Timing(AN-6005 Loss Calculations with Excel Spreadsheet)
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dV/dt Turn On
False turn on Possible to control externally
CGD = CrssCGS = Ciss CrssCDS = Coss Crss
RDriver
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dV/dt Resulting in False Turn On
dV/dt turn-on happens as you turn onthe high side MOSFET. The high dv/dtcouples with charge through Cgd of thelow side MOSFET and drives the gate ofthe low side MOSFET higher. This spikeis sufficient to turn on the lowerMOSFET and cause shoot-through.
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Notebook FDS6294 upper FET / Competition x1Lower FET(Lower FET switching waveforms) Second slope dV/dt inducedshoot through loss.
Conditions:
Vin = 19V
Iout = 15A
Still air
Doubleslopein Vds
Slopechangesin thisareawhereVgs > Vth
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Reducing Turn On dv/dt
dv/dt turn-on can also bereduced by increasing the risetime. This is achieved byadding a resistor in the bootcircuit to slow turn on of thehigh side MOSFET
If you must use a gateresistor, add a low dropSchottky in parallel
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Outline
Computer/Consumer SMD Switch Applications Synchronous Buck Regulators Node Voltage Overshoots MOSFET Body Diode & Avalanche Ruggedness Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications Paralleling Multiple MOSFETs Trench vs. Planar RC DrainSource Snubbers
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Parasitics in a Synchronous Buck Converter
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Notebook FDS6294 High Side FET / Competitionx1 Low Side FET
GatenoiseduringdVds/dt
Gate ringsbelow -1V.DuringdVds/dt,gate hasactuallyrung back topositive.
Gate L-C ringing can destroy gate drivers and cause false turn on.
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Go to www.fairchildsemi.com/models, click on FetBench
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Choose the Sync Buck Application
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Package Impedance Comparisons
Comparison of Electrical Characteristics of Various Power Packages
i)
LddnH
LggnH
Rdm
Rsm
Rgm
PackageDescription
2 x 2.5 mm BGA 0.056 0.011 0.032 0.05 0.16 0.79
4 x 3.5 mm BGA 0.064 0.006 0.034 0.02 0.06 0.95
5 x 5.5 mm BGA 0.048 0.006 0.041 0.01 0.04 0.78
0.744
SO-8 0.457 0.901 1.849 0.12 2.04 20.15
SO-8 Wireless 0.601 0.709 0.932 0.16 0.23 1.77
IPAK (TO-251) 2.920 3.490 4.630 0.25 0.74 8.18
DPAK (TO-252) 0.026 3.730 4.870 0.00 0.77 8.21
D2PAK (TO-263) 0.000 7.760 9.840 0.00 0.96 12.59
FLMP ( Large 3s)FLMP ( Large 7s) 0.194
0.943
0.921
0.002
0.002
0.245
0.137
2.046
2.038
0.000
0.000
LssnH
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BGA vs. SO-8 Same Die, Same Application
BGA MOSFETs SOIC MOSFETs
ch4 = SW node, Ch 3 = LDRV TR 4nS
ch1 = HDRV, Ch 2 = LDRVTR 20nS
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Package Impedances - Conclusions
IPAK is an inexpensive package taking up very little real estate butinductances are very high. Not suitable for high frequencies.
As switching frequencies increase, DPAK and SO-8 will bereplaced by BGAs and FLMPs.
You should not blindly use same package for high and low sideespecially if you can use a smaller package with lower parasiticsfor high side switches. Under 10m, 30V in 3x3 MLP.
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As Switching Frequencies Increase...
MORE FOCUS ON REDUCING PARASITICS : (DUAL MOSFET+ PWMIC) COMBINATIONS :
Hybrid Packaging Monolithic Solutions
Make your own combination with better packages with BGAs.
Pay attention to layout especially around switch nodes andgate circuits.
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Hybrid Synchronous Bucks
3-Paddle 5x6mm0.65mm pitch MLP
(Bottom View)
VIN
VSENPGNDAGND
LDRV
HDRVSW
COMP
VCC
SS
Q1
Q2
BOOT
PGOOD
SW
VSEN
P3
PGND
14
P1
COUT
VOUTL OUT
R2
R1
P2 VIN
BOOT8
SS
CSS
COMP
VCC
13
15
12
16
10
R
3
C1
11PGOOD
6.5 TO 24V
VOUT
FPWM#
9
+5
PWM
MOD-ULATOR
EN
VOUT
BOOTPVIN
PVIN
PVIN
PVIN
SW
SWSW
+5 VCCFPWM#
VSENSSCOMPPGOOD
EN
VOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P1GNDP2VIN
P3SW
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Hybrid Sync-Buck PCB Layout(Target Area < 0.3 sq in. for 5A, 12Vin)
I
n
d
u
c
t
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r
:
C
o
i
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t
r
o
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i
c
s
U
P
1
B
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R
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d
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:
C
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i
l
t
r
o
n
i
c
s
U
P
1
B
S
E
R
I
E
S
GND
VIN
P1
P2
P3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
0603Cap
1206Cap
1206Cap
1206Cap
1210 CAP
0603R
0603R 0603
R
0
.
5
"
0.5875 "
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FAN20XXMonolithic Synchronous Buck Family Overview
Over 90% Efficiency 3.0V to 5.5V VININ Programmable phase
clock synchronization Internal power MOSFETs Current and thermal limit Programmable auto-restart
on fault Current mode control
FAN 2011 and FAN2012 are examples
7
8SS
12I(LIM)13R(T)
C SS
VCC
15CLOCK
10EN
S W
FB
Q1
Q2PWM
MODULATORGND
14
PVIN
P1
COUT
VOUTL OUT
R2
R1
9 PGOODVOUT11
R(LIM)
RT
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Outline
Computer/Consumer SMD Switch Applications Synchronous Buck Regulators Node Voltage Overshoots MOSFET Body Diode & Avalanche Ruggedness Switch Timing and dV/dt Shoot Through Package and Layout Parasitics
Industrial Applications Paralleling Multiple MOSFETs Trench vs. Planar RC DrainSource Snubbers
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Industrial Low Voltage MOSFETS
Low Voltage MOSFETs in industrial applications are really verydifferent from those in surface mount DC-DC converters.
MOSFETs in industrial applications are closer to High VoltageMOSFETs in some design and critical parameters.
Planar MOSFETs have some advantages at high currents overTrench.
Industrial Applications UPS systems, Inverters, Battery PoweredMotor Drives (people movers), Automotive Audio etc.
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Paralleling Power MOSFETs in IndustrialApplications
MOSFET paralleling is generally easier than any other powersemiconductor device thanks to positive temperature coefficient
Applications such as UPS, Drives etc. have numerous paralleledMOSFETs. TO-220 and TO-263 (D2PAK) are the most popularpackage
As low voltage power MOSFET technologies evolve, what is bestfor high frequency dc-dc switching converters may not be best forthese industrial applications
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Parallel Operation of MOSFETsStatic and Dynamic Current Sharing
Circuit ParasiticsV
Ls Ls
Ld Ld
Rd Rd
Rload
Lload
Llayout
Kelvin source
Rg Rg
S1
G1
Rg1
S2
G2
Rg2
S3
G3
Rg3 Rg4
S4
G4
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Circuit Layout Considerations: DynamicConduction
Severe turn-on and turn-off current differences may result from mismatched devicesISL9N302AS3ST, reference Lot Y149 (devices #4 and #7)
1 i_high_vgsth2 i_low_vgsth
7.50U 22.5U 37.5U 52.5U 67.5U
time ( 7.5 s / div.)
12.0
36.0
60.0
84.0
108
i
_
h
i
g
h
_
v
g
s
t
h
,
i
_
l
o
w
_
v
g
s
t
h
i
n
a
m
p
s
P
l
o
t
1
1
2
5
14V
550
8u0.01
10V
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Dynamic Current Balancing20nH Added to Source
Switching current balance improved with intentional addition oflimited source inductance
ISL9N302AS3ST, reference Lot Y149 (devices #4 and #7)Note that the negative tempco of VGS(th) tends to increasecurrent Imbalance.
1 i_high_vgsth 2 i_low_vgsth
7.50U 22.5U 37.5U 52.5U 67.5Utime in secs
12.0
36.0
60.0
84.0
108
i_high_vgsth,
i_low_vgsth
in amps
Plot1
21
5
14V
550
8u0.01
10V
20nH 20nH
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Circuit Layout Considerations: DynamicConduction
Switching waveform balance obtained with 1 turn common modeinductor in series with device sources
Forces synchronized turn-on and turn-offISL9N302AS3ST, reference Lot Y149 (devices #4 and #7)
1 i_high_vgsth 2 i_low_vgsth
7.50U 22.5U 37.5U 52.5U 67.5Utime in secs
12.0
36.0
60.0
84.0
108
i_high_vgsth,
i_low_vgsth
in amps
Plot1
12
5
14V
550
8u0.01
10V1T
Magnetics IncYF40705-TCLmag = 2.5uH
Llk = 20nHK=0.992, r = 0.0001
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Summary: Circuit Layout Considerations
Use symmetrical layout to minimize & equalize parasiticimpedances
Use shared heat sink to match TJmax even if uneven currentresults TJmax has most profound effect on reliability Vgs(th) has a negative temperature coefficient
Use a fast gate drive signal: Less time spent in active region Dynamic current sharing improves with faster switching select the gate resistor as small as possible during switch on no ringing shall be allowed
Inductance inserted in FET source lead is very effective fordynamic current sharing Reduced switching speed and increased switching loss
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Outline
Computer/Consumer SMD Switch Applications Synchronous Buck Regulators Node Voltage Overshoots MOSFET Body Diode & Avalanche Ruggedness Switch Timing and dV/dt Shoot Through Package and Layout Parasitics
Industrial Applications Paralleling Multiple MOSFETs
Trench vs. Planar RC DrainSource Snubbers
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Planar vs. Trench MOSFETS
Planar
Trench
RDS(on) = RChannel + REpitaxial + RPackage
RDS(on) = RChannel + RJFET + REpitaxial + RPackage
RPackage
Drain
GateSourceSource
REpitaxial
RJFET
RChannel
Drain
GateGate
Source
RChannel
RPackage
REpitaxial
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HUF75545P3 FDB045AN08A0(Older Planar) (Newer Trench)
RDS(on) 10mW 4.5mW
Qg 235nC 138nC
Pd 270W 310W
trr (@ 25 C) 100ns 53ns
Qrr (@ 25 C) 300nC 54nC
75V MOSFET Technology Trends. Comparing MOSFETs of equal die size.
Comparison of MOSFET Key Parameters
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trr: Anti-parallel Diode Recovery
TestConditions:
VDD = 60VID = 20Adi/dt =
520 A/s
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Thermal Analysis
Worst Case for the inverter MOSFETs = Output short circuit
For this case a low RQjc is most important:
HUF75545P3 FDB045AN08A0
RQjc 0.55 K/W 0.48 K/W
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Maximum Current at Short CircuitTransconductance vs. Current Crowding
HUF75545P3
Older Planar
FDB045AN08A0
Newer Trench
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Outline
Computer/Consumer SMD Switch Applications Synchronous Buck Regulators Node Voltage Overshoots MOSFET Body Diode & Avalanche Ruggedness Switch Timing and dV/dt Shoot Through Package and Layout Parasitics
Industrial Applications Paralleling Multiple MOSFETs Trench vs. Planar
RC DrainSource Snubbers
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Adding Gate Resistors
Many applications needMOSFETs in parallel forextremely low on-resistance.Since costs are optimizedaround TO-220 die size, banksare common
Use of built-in resistor shows adecrease of circuit oscillationand EMI
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FDB3632 (NO RC Circuit Across FET)(Test Conditions: VDS = 50Vdc, ID = 40A, VGS = 10V, L=10uH, TJ = 25C)
Rge = 51
Eon = 164uJ
Rge = External Gate Resistor
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FDB3632 (With RC Circuit Across FET, D-S)(Test Conditions: VDS = 50Vdc, ID = 40A, VGS = 10V, L=10mH, TJ = 25C)
Rge = 51
Eon = 208uJ
R-C SnubberC=2000pFR=1
Rge = External Gate Resistor