familiarization with basic logic gates and digital counters

3
Experiment No : 08 Familiarization With Basic Logic Gates And digital Counters 4 Bit Counter : Schematic Diagram : Output Graph :

Upload: abdulbabul

Post on 30-Sep-2015

5 views

Category:

Documents


0 download

DESCRIPTION

it is also another production of pspice simulation software based counter making example with required graphs and schematic circuit diagram.

TRANSCRIPT

Experiment No : 08

Familiarization With Basic Logic Gates And digital Counters

4 Bit Counter :

Schematic Diagram :

Output Graph :

Mod 10 Counter :

Schematic Diagram :

Output Graph :

Time Time

0s0.2ms0.4ms0.6ms0.8ms1.0ms1.2ms1.4ms1.6ms1.8ms2.0ms

DSTM1:1

{w[3:0]}X012345678901234567

w3

w2

w1

w0

Time Time

0s0.5ms1.0ms1.5ms2.0ms2.5ms3.0ms

{D[3:0]}X0123456789ABCDEF0123456789AB

D3

U1:CLK

D2

D1

D0